Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

CONTENTS

PAGE

CHAPTER 1

ABOUT THIS MANUAL

1.1

INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL

1-1

1.2

OVERVIEW OF THE MODEL-SPECIFIC REGISTERS

1-4

1.3

NOTATIONAL CONVENTIONS

1-5

1.3.1

Bit and Byte Order

1-5

1.3.2

Reserved Bits and Software Compatibility

1-5

1.3.3

Instruction Operands

1-6

1.3.4

Hexadecimal and Binary Numbers

1-6

1.3.5

Segmented Addressing

1-6

1.3.6

Syntax for CPUID, CR, and MSR Values

1-7

1.3.7

Exceptions

1-7

1.4

RELATED LITERATURE

1-8

CHAPTER 2

MODEL-SPECIFIC REGISTERS (MSRS)

2.1

ARCHITECTURAL MSRS

2-3

2.2

MSRS IN THE INTEL® CORE™ 2 PROCESSOR FAMILY

2-68

2.3

MSRS IN THE 45 NM AND 32 NM INTEL ATOM® PROCESSOR FAMILY

2-82

2.4

MSRS IN INTEL PROCESSORS BASED ON SILVERMONT MICROARCHITECTURE

2-93

2.4.1

MSRs with Model-Specific Behavior in the Silvermont Microarchitecture

2-107

2.4.2

MSRs in Intel Atom® Processors Based on Airmont Microarchitecture

2-110

2.5

MSRS IN INTEL ATOM® PROCESSORS BASED ON GOLDMONT MICROARCHITECTURE

2-112

2.6

MSRS IN INTEL ATOM® PROCESSORS BASED ON GOLDMONT PLUS MICROARCHITECTURE

2-136

2.7

MSRS IN INTEL ATOM® PROCESSORS BASED ON TREMONT MICROARCHITECTURE

2-140

2.8

MSRS IN PROCESSORS BASED ON NEHALEM MICROARCHITECTURE

2-142

2.8.1

Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series

2-160

2.8.2

Additional MSRs in the Intel® Xeon® Processor 7500 Series

2-162

2.9

MSRS IN THE INTEL® XEON® PROCESSOR 5600 SERIES BASED ON WESTMERE MICROARCHITECTURE

2-176

2.10

MSRS IN THE INTEL® XEON® PROCESSOR E7 FAMILY BASED ON WESTMERE MICROARCHITECTURE

2-177

2.11

MSRS IN THE INTEL® PROCESSOR FAMILY BASED ON SANDY BRIDGE MICROARCHITECTURE

2-179

2.11.1

MSRs in the 2nd Generation Intel® Core™ Processor Family Based on Sandy Bridge Microarchitecture

2-199

2.11.2

MSRs in the Intel® Xeon® Processor E5 Family Based on Sandy Bridge Microarchitecture

2-203

2.11.3

Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 Family

2-207

2.12

MSRS IN THE 3RD GENERATION INTEL® CORE™ PROCESSOR FAMILY BASED ON IVY BRIDGE MICROARCHITECTURE. . . 2-210

2.12.1

MSRs in the Intel® Xeon® Processor E5 v2 Product Family Based on Ivy Bridge-E Microarchitecture

2-214

2.12.2

Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family

2-221

2.12.3

Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families

2-223

2.13

MSRS IN THE 4TH GENERATION INTEL® CORE™ PROCESSORS BASED ON HASWELL MICROARCHITECTURE

2-226

2.13.1

MSRs in the 4th Generation Intel® Core™ Processor Family Based on Haswell Microarchitecture

2-232

2.13.2

Additional Residency MSRs Supported in 4th Generation Intel® Core™ Processors

2-244

2.14

MSRS IN THE INTEL® XEON® PROCESSOR E5 V3 AND E7 V3 PRODUCT FAMILY

2-245

2.14.1

Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family

2-255

2.15

MSRS IN THE INTEL® CORE™ M PROCESSORS AND THE 5TH GENERATION INTEL® CORE™ PROCESSORS

2-265

2.16

MSRS IN THE INTEL® XEON® PROCESSOR E5 V4 FAMILY

2-269

2.16.1

Additional MSRs Supported in the Intel® Xeon® Processor D Product Family

2-280

2.16.2

Additional MSRs Supported in Intel® Xeon® Processors E5 v4 and E7 v4 Families

2-282

2.17

MSRS IN THE 6TH GENERATION, 7TH GENERATION, 8TH GENERATION, 9TH GENERATION, 10TH GENERATION, 11TH

GENERATION, 12TH GENERATION, AND 13TH GENERATION INTEL® CORE™ PROCESSORS, INTEL® XEON® SCALABLE

PROCESSOR FAMILY, 2ND, 3RD, AND 4TH GENERATION INTEL® XEON® SCALABLE PROCESSOR FAMILY, 8TH GENERATION

INTEL® CORE™ I3 PROCESSORS, AND INTEL® XEON® E PROCESSORS

2-285

2.17.1

MSRs Introduced in 7th Generation and 8th Generation Intel® Core™ Processors Based on Kaby Lake Microarchitecture

and Coffee Lake Microarchitecture

2-308

2.17.2

MSRs Specific to 8th Generation Intel® Core™ i3 Processors

2-310

2.17.3

MSRs Introduced in 10th Generation Intel® Core™ Processors

2-316

2.17.4

MSRs Introduced in the 11th Generation Intel® Core™ Processors based on Tiger Lake Microarchitecture

2-320

2.17.5

MSRs Introduced in the 12th and 13th Generation Intel® Core™ Processors Supporting Performance Hybrid

Architecture

2-323

2.17.6

MSRs Introduced in the Intel® Xeon® Scalable Processor Family

2-332

Vol. 4

iii

CONTENTS

PAGE

TABLES

Table 2-1.

CPUID Signature Values of DisplayFamily_DisplayModel

2-1

Table 2-2.

IA-32 Architectural MSRs

2-3

Table 2-3.

MSRs in Processors Based on Intel® Core™ Microarchitecture

2-68

Table 2-4.

MSRs in the 45 nm and 32 nm Intel Atom® Processor Family

2-82

Table 2-5.

MSRs Supported by Intel Atom® Processors with a CPUID Signature DisplayFamily_DisplayModel Value of

06_27H

2-93

Table 2-6.

MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom® Processors . . 2-94

Table 2-7.

MSRs Common to the Silvermont and Airmont Microarchitectures

2-102

Table 2-8.

Specific MSRs Supported by Intel Atom® Processors with a CPUID Signature DisplayFamily_DisplayModel Value

of 06_37H, 06_4AH, 06_5AH, or 06_5DH

2-107

Table 2-9.

Specific MSRs Supported by the Intel Atom® Processor E3000 Series with a CPUID Signature DisplayFamily_DisplayModel

Value of 06_37H

2-108

Table 2-10.

Specific MSRs Supported by Intel Atom® Processor C2000 Series with a CPUID Signature DisplayFamily_DisplayModel

Value of 06_4DH

2-109

Table 2-11.

MSRs in Intel Atom® Processors Based on Airmont Microarchitecture

2-110

Table 2-12.

MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture

2-113

Table 2-13.

MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture

2-136

Table 2-14.

MSRs in Intel Atom® Processors Based on Tremont Microarchitecture

2-141

Table 2-15.

MSRs in Processors Based on Nehalem Microarchitecture

2-142

Table 2-16.

Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series

2-160

Table 2-17.

Additional MSRs in the Intel® Xeon® Processor 7500 Series

2-162

Table 2-18.

Additional MSRs Supported by Intel® Processors Based on Westmere Microarchitecture

2-176

Table 2-19.

Additional MSRs Supported by the Intel® Xeon® Processor E7 Family

2-177

Table 2-20.

MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture

2-179

Table 2-21.

MSRs Supported by the 2nd Generation Intel® Core™ Processors (Sandy Bridge Microarchitecture)

2-199

Table 2-22.

Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors

2-201

Table 2-23.

Selected MSRs Supported by Intel® Xeon® Processors E5 Family Based on Sandy Bridge Microarchitecture

2-203

Table 2-24.

Uncore PMU MSRs in Intel® Xeon® Processor E5 Family

2-207

Table 2-25.

Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge Microarchitecture . .2-210

Table 2-26.

MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family Based on Ivy Bridge-E Microarchitecture .2-214

Table 2-27.

Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_3EH

2-221

Table 2-28.

Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families

2-223

Table 2-29.

Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures

2-227

Table 2-30.

MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture)

2-232

Table 2-31.

Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_45H

2-244

Table 2-32.

Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family

2-246

Table 2-33.

Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family

2-256

Table 2-34.

Additional MSRs Common to Processors Based on Broadwell Microarchitectures

2-265

Table 2-35.

Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors

2-268

Table 2-36.

Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family Based

on Broadwell Microarchitecture

2-269

Table 2-37.

Additional MSRs Supported by Intel® Xeon® Processor D with a CPUID Signature DisplayFamily_DisplayModel

Value of 06_56H

2-280

Table 2-38.

Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature DisplayFamily_DisplayModel

Value of 06_4FH

2-282

Table 2-39.

Additional MSRs Supported by 6th Generation, 7th Generation, 8th Generation, 9th Generation,

10th Generation, 11th Generation, 12th Generation, and 13th Generation Intel® Core™ Processors,

Intel® Xeon® Scalable Processor Family, 2nd, 3rd, and 4th Generation Intel® Xeon® Scalable Processor Family,

8th Generation Intel® Core™ i3 Processors, and Intel® Xeon® E Processors

2-286

Table 2-40.

Uncore PMU MSRs Supported by 6th Generation, 7th Generation, and 8th Generation Intel® Core™ Processors,

and 8th generation Intel® Core™ i3 Processors

2-306

Table 2-41.

Additional MSRs Supported by the 7th Generation and 8th Generation Intel® Core™ Processors Based on Kaby

Lake Microarchitecture and Coffee Lake Microarchitecture

2-308

Table 2-42.

Additional MSRs Supported by 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake

Microarchitecture

2-310

Table 2-43.

Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture

2-315

Table 2-44.

MSRs Supported by 10th Generation Intel® Core™ Processors Based on Ice Lake Microarchitecture

2-317

Table 2-45.

Additional MSRs Supported by the 11th Generation Intel® Core™ Processors Based on Tiger Lake

Microarchitecture

2-320

Table 2-46.

Additional MSRs Supported by the 12th and 13th Generation Intel® Core™ Processors Supporting Performance

vi Vol. 4

CONTENTS

PAGE

Hybrid Architecture

2-324

Table 2-47.

MSRs Supported by 12th and 13th Generation Intel® Core™ Processor P-core

2-327

Table 2-48.

MSRs Supported by 12th and 13th Generation Intel® Core™ Processor E-core

2-329

Table 2-49.

Uncore PMU MSRs Supported by 12th and 13th Generation Intel® Core™ Processors

2-329

Table 2-50.

MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature DisplayFamily_DisplayModel

Value of 06_55H

2-332

Table 2-51.

MSRs Supported by the 3rd Generation Intel® Xeon® Scalable Processor Family with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_6AH or 06_6CH

2-344

Table 2-52.

Additional MSRs Supported by the 4th Generation Intel® Xeon® Scalable Processor Family with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_8FH

2-346

Table 2-53.

Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature DisplayFamily_DisplayModel

Value of 06_57H or 06_85H

2-357

Table 2-54.

Additional MSRs Supported by the Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_85H

2-372

Table 2-55.

MSRs in the Pentium® 4 and Intel® Xeon® Processors

2-373

Table 2-56.

MSRs Unique to 64-bit Intel® Xeon® Processor MP with Up to an 8 MB L3 Cache

2-399

Table 2-57.

MSRs Unique to Intel® Xeon® Processor 7100 Series

2-399

Table 2-58.

MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV

2-400

Table 2-59.

MSRs in Pentium M Processors

2-409

Table 2-60.

MSRs in the P6 Family Processors

2-416

Table 2-61.

MSRs in the Pentium Processor

2-426

Vol. 4 vii

CHAPTER 1

ABOUT THIS MANUAL

The Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 4: Model-Specific Registers (order

number 335592) is part of a set that describes the architecture and programming environment of Intel^® 64 and IA-

32 architecture processors. Other volumes in this set are:

• Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture (order number

253665).

• Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D: Instruction Set

Reference (order numbers 253666, 253667, 326018, and 334569).

• The Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C, & 3D: System

Programming Guide (order numbers 253668, 253669, 326019, and 332831).

The Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, describes the basic architecture

and programming environment of Intel 64 and IA-32 processors. The Intel^® 64 and IA-32 Architectures Software

Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, describe the instruction set of the processor and the opcode struc-

ture. These volumes apply to application programmers and to programmers who write operating systems or exec-

utives. The Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C, & 3D, describe

the operating-system support environment of Intel 64 and IA-32 processors. These volumes target operating-

system and BIOS designers. In addition, the Intel^® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 3B, and the Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, address the

programming environment for classes of software that host operating systems. The Intel^® 64 and IA-32 Architec-

tures Software Developer’s Manual, Volume 4, describes the model-specific registers of Intel 64 and IA-32 proces-

sors.

1.1

INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL

This manual set includes information pertaining primarily to the most recent Intel 64 and IA-32 processors, which

include:

• Pentium^® processors

• P6 family processors

• Pentium^® 4 processors

• Pentium^® M processors

• Intel^® Xeon^® processors

• Pentium^® D processors

• Pentium^® processor Extreme Editions

•

64-bit Intel^® Xeon^® processors

• Intel^® Core™ Duo processor

• Intel^® Core™ Solo processor

• Dual-Core Intel^® Xeon^® processor LV

• Intel^® Core™ 2 Duo processor

• Intel^® Core™ 2 Quad processor Q6000 series

• Intel^® Xeon^® processor 3000, 3200 series

• Intel^® Xeon^® processor 5000 series

• Intel^® Xeon^® processor 5100, 5300 series

• Intel^® Core™ 2 Extreme processor X7000 and X6800 series

• Intel^® Core™ 2 Extreme QX6000 series

Vol. 4

1-1

ABOUT THIS MANUAL

•

Intel^® Xeon^® processor 7100 series

•

Intel^® Pentium^® Dual-Core processor

•

Intel^® Xeon^® processor 7200, 7300 series

•

Intel^® Core™ 2 Extreme QX9000 series

•

Intel^® Xeon^® processor 5200, 5400, 7400 series

•

Intel^® Core™ 2 Extreme processor QX9000 and X9000 series

•

Intel^® Core™ 2 Quad processor Q9000 series

•

Intel^® Core™ 2 Duo processor E8000, T9000 series

•

Intel Atom^® processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000,

C1000 series are built from 45 nm and 32 nm processes.

•

Intel^® Core™ i7 processor

•

Intel^® Core™ i5 processor

•

Intel^® Xeon^® processor E7-8800/4800/2800 product families

•

Intel^® Core™ i7-3930K processor

•

2nd generation Intel^® Core™ i7-2xxx, Intel^® Core™ i5-2xxx, Intel^® Core™ i3-2xxx processor series

•

Intel^® Xeon^® processor E3-1200 product family

•

Intel^® Xeon^® processor E5-2400/1400 product family

•

Intel^® Xeon^® processor E5-4600/2600/1600 product family

•

3rd generation Intel^® Core™ processors

•

Intel^® Xeon^® processor E3-1200 v2 product family

•

Intel^® Xeon^® processor E5-2400/1400 v2 product families

•

Intel^® Xeon^® processor E5-4600/2600/1600 v2 product families

•

Intel^® Xeon^® processor E7-8800/4800/2800 v2 product families

•

4th generation Intel^® Core™ processors

•

The Intel^® Core™ M processor family

•

Intel^® Core™ i7-59xx Processor Extreme Edition

•

Intel^® Core™ i7-49xx Processor Extreme Edition

•

Intel^® Xeon^® processor E3-1200 v3 product family

•

Intel^® Xeon^® processor E5-2600/1600 v3 product families

•

5th generation Intel^® Core™ processors

•

Intel^® Xeon^® processor D-1500 product family

•

Intel^® Xeon^® processor E5 v4 family

•

Intel Atom^® processor X7-Z8000 and X5-Z8000 series

•

Intel Atom^® processor Z3400 series

•

Intel Atom^® processor Z3500 series

•

6th generation Intel^® Core™ processors

•

Intel^® Xeon^® processor E3-1500m v5 product family

•

7th generation Intel^® Core™ processors

•

Intel^® Xeon Phi™ Processor 3200, 5200, 7200 Series

•

Intel^® Xeon^® Scalable Processor Family

•

8th generation Intel^® Core™ processors

•

Intel^® Xeon Phi™ Processor 7215, 7285, 7295 Series

•

Intel^® Xeon^® E processors

•

9th generation Intel^® Core™ processors

1-2

Vol. 4

ABOUT THIS MANUAL

• 2nd generation Intel^® Xeon^® Scalable Processor Family

•

10th generation Intel^® Core™ processors

•

11th generation Intel^® Core™ processors

• 3rd generation Intel^® Xeon^® Scalable Processor Family

•

12th generation Intel^® Core™ processors

•

13th generation Intel^® Core™ processors

• 4th generation Intel^® Xeon^® Scalable Processor Family

P6 family processors are IA-32 processors based on the P6 family microarchitecture. This includes the Pentium^®

Pro, Pentium^® II, Pentium^® III, and Pentium^® III Xeon^® processors.

The Pentium^® 4, Pentium^® D, and Pentium^® processor Extreme Editions are based on the Intel NetBurst^®micro-

architecture. Most early Intel^® Xeon^®processors are based on the Intel NetBurst^®microarchitecture. Intel Xeon

processor 5000, 7100 series are based on the Intel NetBurst^®microarchitecture.

The Intel^® Core™ Duo, Intel^® Core™ Solo and dual-core Intel^®Xeon^® processor LV are based on an improved

Pentium^® M processor microarchitecture.

The Intel^® Xeon^® processor 3000, 3200, 5100, 5300, 7200, and 7300 series, Intel^® Pentium^® dual-core, Intel^®

Core™ 2 Duo, Intel^® Core™ 2 Quad, and Intel^® Core™ 2 Extreme processors are based on Intel^®Core™ microar-

chitecture.

The Intel^® Xeon^® processor 5200, 5400, 7400 series, Intel^® Core™ 2 Quad processor Q9000 series, and Intel^®

Core™ 2 Extreme processors QX9000, X9000 series, Intel^® Core™ 2 processor E8000 series are based on

Enhanced Intel^®Core™ microarchitecture.

The Intel Atom^® processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000,

C1000 series are based on the Intel Atom^® microarchitecture and supports Intel 64 architecture.

P6 family, Pentium^® M, Intel^® Core™ Solo, Intel^® Core™ Duo processors, dual-core Intel^®Xeon^® processor LV,

and early generations of Pentium 4 and Intel Xeon processors support IA-32 architecture. The Intel^® Atom^TM

processor Z5xx series support IA-32 architecture.

The Intel^® Xeon^® processor 3000, 3200, 5000, 5100, 5200, 5300, 5400, 7100, 7200, 7300, 7400 series, Intel^®

Core™ 2 Duo, Intel^® Core™ 2 Extreme, Intel^® Core™ 2 Quad processors, Pentium^® D processors, Pentium^® Dual-

Core processor, newer generations of Pentium 4 and Intel Xeon processor family support Intel^® 64 architecture.

The Intel^® Core™ i7 processor and Intel^® Xeon^® processor 3400, 5500, 7500 series are based on 45 nm Nehalem

microarchitecture. Westmere microarchitecture is a 32 nm version of the Nehalem microarchitecture. Intel^®

Xeon^® processor 5600 series, Intel Xeon processor E7 and various Intel Core i7, i5, i3 processors are based on the

Westmere microarchitecture. These processors support Intel 64 architecture.

The Intel^® Xeon^® processor E5 family, Intel^® Xeon^® processor E3-1200 family, Intel^® Xeon^® processor E7-

8800/4800/2800 product families, Intel^® Core™ i7-3930K processor, and 2nd generation Intel^® Core™ i7-2xxx,

Intel^® Core^TM i5-2xxx, Intel^® Core™ i3-2xxx processor series are based on the Sandy Bridge microarchitecture and

support Intel 64 architecture.

The Intel^® Xeon^® processor E7-8800/4800/2800 v2 product families, Intel^® Xeon^® processor E3-1200 v2 product

family and 3rd generation Intel^® Core™ processors are based on the Ivy Bridge microarchitecture and support

Intel 64 architecture.

The Intel^® Xeon^® processor E5-4600/2600/1600 v2 product families, Intel^® Xeon^® processor E5-2400/1400 v2

product families and Intel^® Core™ i7-49xx Processor Extreme Edition are based on the Ivy Bridge-E microarchitec-

ture and support Intel 64 architecture.

The Intel^® Xeon^® processor E3-1200 v3 product family and 4th Generation Intel^® Core™ processors are based on

the Haswell microarchitecture and support Intel 64 architecture.

The Intel^® Xeon^® processor E5-2600/1600 v3 product families and the Intel^® Core™ i7-59xx Processor Extreme

Edition are based on the Haswell-E microarchitecture and support Intel 64 architecture.

The Intel Atom^® processor Z8000 series is based on the Airmont microarchitecture.

The Intel Atom^® processor Z3400 series and the Intel Atom^® processor Z3500 series are based on the Silvermont

microarchitecture.

Vol. 4

1-3

ABOUT THIS MANUAL

The Intel^® Core™ M processor family, 5th generation Intel^® Core™ processors, Intel^® Xeon^® processor D-1500

product family and the Intel^® Xeon^® processor E5 v4 family are based on the Broadwell microarchitecture and

support Intel 64 architecture.

The Intel^® Xeon^® Scalable Processor Family, Intel^® Xeon^® processor E3-1500m v5 product family and 6th gener-

ation Intel^® Core™ processors are based on the Skylake microarchitecture and support Intel 64 architecture.

The 7th generation Intel^® Core™ processors are based on the Kaby Lake microarchitecture and support Intel 64

architecture.

The Intel Atom^® processor C series, the Intel Atom^® processor X series, the Intel^® Pentium^® processor J series,

the Intel^® Celeron^® processor J series, and the Intel^® Celeron^® processor N series are based on the Goldmont

microarchitecture.

The Intel^® Xeon Phi™ Processor 3200, 5200, 7200 Series is based on the Knights Landing microarchitecture and

supports Intel 64 architecture.

The Intel^® Pentium^® Silver processor series, the Intel^® Celeron^® processor J series, and the Intel^® Celeron^®

processor N series are based on the Goldmont Plus microarchitecture.

The 8th generation Intel^® Core™ processors, 9th generation Intel^® Core™ processors, and Intel^® Xeon^® E proces-

sors are based on the Coffee Lake microarchitecture and support Intel 64 architecture.

The Intel^® Xeon Phi™ Processor 7215, 7285, 7295 Series is based on the Knights Mill microarchitecture and

supports Intel 64 architecture.

The 2nd generation Intel^® Xeon^® Scalable Processor Family is based on the Cascade Lake product and supports

Intel 64 architecture.

Some 10th generation Intel^® Core™ processors are based on the Ice Lake microarchitecture, and some are based

on the Comet Lake microarchitecture; both support Intel 64 architecture.

Some 11th generation Intel^® Core™ processors are based on the Tiger Lake microarchitecture, and some are

based on the Rocket Lake microarchitecture; both support Intel 64 architecture.

Some 3rd generation Intel^® Xeon^® Scalable Processor Family processors are based on the Cooper Lake product,

and some are based on the Ice Lake microarchitecture; both support Intel 64 architecture.

The 12th generation Intel^® Core™ processors are based on the Alder Lake performance hybrid architecture and

support Intel 64 architecture.

The 13th generation Intel^® Core™ processors are based on the Raptor Lake performance hybrid architecture and

support Intel 64 architecture.

The 4th generation Intel^® Xeon^® Scalable Processor Family is based on Sapphire Rapids microarchitecture and

supports Intel 64 architecture.

IA-32 architecture is the instruction set architecture and programming environment for Intel's 32-bit microproces-

sors. Intel^®64 architecture is the instruction set architecture and programming environment which is the superset

of Intel’s 32-bit and 64-bit architectures. It is compatible with the IA-32 architecture.

1.2

OVERVIEW OF THE MODEL-SPECIFIC REGISTERS

A description of this manual’s content follows:

Chapter 1 - About This Manual. Gives an overview of all volumes of the Intel^® 64 and IA-32 Architectures Soft-

ware Developer’s Manual. It also describes the notational conventions in these manuals and lists related Intel

manuals and documentation of interest to programmers and hardware designers.

Chapter 2 - Model-Specific Registers (MSRs). Lists the MSRs available in Intel processors, and describes their

functions.

1-4

Vol. 4

ABOUT THIS MANUAL

1.3

NOTATIONAL CONVENTIONS

This manual uses specific notation for data-structure formats, for symbolic representation of instructions, and for

hexadecimal and binary numbers. A review of this notation makes the manual easier to read.

1.3.1

Bit and Byte Order

In illustrations of data structures in memory, smaller addresses appear toward the bottom of the figure; addresses

increase toward the top. Bit positions are numbered from right to left. The numerical value of a set bit is equal to

two raised to the power of the bit position. Intel 64 and IA-32 processors are “little endian” machines; this means

the bytes of a word are numbered starting from the least significant byte. Figure 1-1 illustrates these conventions.

1.3.2

Reserved Bits and Software Compatibility

In many register and memory layout descriptions, certain bits are marked as reserved. When bits are marked as

reserved, it is essential for compatibility with future processors that software treat these bits as having a future,

though unknown, effect. The behavior of reserved bits should be regarded as not only undefined, but unpredict-

able. Software should follow these guidelines in dealing with reserved bits:

• Do not depend on the states of any reserved bits when testing the values of registers which contain such bits.

Mask out the reserved bits before testing.

• Do not depend on the states of any reserved bits when storing to memory or to a register.

• Do not depend on the ability to retain information written into any reserved bits.

• When loading a register, always load the reserved bits with the values indicated in the documentation, if any,

or reload them with values previously read from the same register.

NOTE

Avoid any software dependence upon the state of reserved bits in Intel 64 and IA-32 registers.

Depending upon the values of reserved register bits will make software dependent upon the

unspecified manner in which the processor handles these bits. Programs that depend upon

reserved values risk incompatibility with future processors.

Data Structure

Highest

24 23

16 15

Bit offset

Address

Lowest

Byte 3

Byte 2

Byte 1

Byte 0

Address

Byte Offset

Figure 1-1. Bit and Byte Order

Vol. 4

1-5

ABOUT THIS MANUAL

1.3.3

Instruction Operands

When instructions are represented symbolically, a subset of assembly language is used. In this subset, an instruc-

tion has the following format:

label: mnemonic argument1, argument2, argument3

where:

• A label is an identifier which is followed by a colon.

• A mnemonic is a reserved name for a class of instruction opcodes which have the same function.

• The operands argument1, argument2, and argument3 are optional. There may be from zero to three

operands, depending on the opcode. When present, they take the form of either literals or identifiers for data

items. Operand identifiers are either reserved names of registers or are assumed to be assigned to data items

declared in another part of the program (which may not be shown in the example).

When two operands are present in an arithmetic or logical instruction, the right operand is the source and the left

operand is the destination.

For example:

LOADREG: MOV EAX, SUBTOTAL

In this example LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX is the destination operand,

and SUBTOTAL is the source operand. Some assembly languages put the source and destination in reverse order.

1.3.4

Hexadecimal and Binary Numbers

Base 16 (hexadecimal) numbers are represented by a string of hexadecimal digits followed by the character H (for

example, F82EH). A hexadecimal digit is a character from the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D,

E, and F.

Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimes followed by the character B (for

example, 1010B). The “B” designation is only used in situations where confusion as to the type of number might

arise.

1.3.5

Segmented Addressing

The processor uses byte addressing. This means memory is organized and accessed as a sequence of bytes.

Whether one or more bytes are being accessed, a byte address is used to locate the byte or bytes memory. The

range of memory that can be addressed is called an address space.

The processor also supports segmented addressing. This is a form of addressing where a program may have many

independent address spaces, called segments. For example, a program can keep its code (instructions) and stack

in separate segments. Code addresses would always refer to the code space, and stack addresses would always

refer to the stack space. The following notation is used to specify a byte address within a segment:

Segment-register:Byte-address

For example, the following segment address identifies the byte at address FF79H in the segment pointed by the DS

DS:FF79H

The following segment address identifies an instruction address in the code segment. The CS register points to the

code segment and the EIP register contains the address of the instruction.

CS:EIP

1-6

Vol. 4

ABOUT THIS MANUAL

1.3.6

Syntax for CPUID, CR, and MSR Values

Obtain feature flags, status, and system information by using the CPUID instruction, by checking control register

bits, and by reading model-specific registers. We are moving toward a single syntax to represent this type of infor-

mation. See Figure 1-2.

CPUID Input and Output

CPUID.01H:EDX.SSE[bit 25] = 1

Input value for EAX register

Output register and feature flag or field

name with bit position(s)

Value (or range) of output

Control Register Values

CR4.OSFXSR[bit 9] = 1

Example CR name

Feature flag or field name

with bit position(s)

Value (or range) of output

Model-Specific Register Values

IA32_MISC_ENABLE.ENABLEFOPCODE[bit 2] = 1

Example MSR name

Feature flag or field name with bit position(s)

Value (or range) of output

Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation

1.3.7

Exceptions

An exception is an event that typically occurs when an instruction causes an error. For example, an attempt to

divide by zero generates an exception. However, some exceptions, such as breakpoints, occur under other condi-

tions. Some types of exceptions may provide error codes. An error code reports additional information about the

error. An example of the notation used to show an exception and error code is shown below:

#PF(fault code)

This example refers to a page-fault exception under conditions where an error code naming a type of fault is

reported. Under some conditions, exceptions which produce error codes may not be able to report an accurate

code. In this case, the error code is zero, as shown below for a general-protection exception:

#GP(0)

Vol. 4

1-7

ABOUT THIS MANUAL

1.4

RELATED LITERATURE

Literature related to Intel 64 and IA-32 processors is listed and viewable on-line at:

https://software.intel.com/en-us/articles/intel-sdm

More relevant links are:

• Intel^® Developer Zone:

https://software.intel.com/en-us

• Developer centers:

http://www.intel.com/content/www/us/en/hardware-developers/developer-centers.html

• Processor support general link:

http://www.intel.com/support/processors/

• Intel^® Hyper-Threading Technology (Intel^®HT Technology):

http://www.intel.com/technology/platform-technology/hyper-threading/index.htm

1-8

Vol. 4

CHAPTER 2

MODEL-SPECIFIC REGISTERS (MSRS)

This chapter lists MSRs across Intel processor families. All MSRs listed can be read with the RDMSR and written with

the WRMSR instructions. The scope of an MSR defines the set of processors that access the same MSR with RDMSR

and WRMSR. Thread-scope MSRs are unique to every logical processor. Core-scope MSRs are shared by the threads

in the same core; similarly for module-scope, die-scope, and package-scope.

When a processor package contains a single die, die-scope and package-scope are synonymous. When a package

contains multiple die, they are distinct.

NOTE

For information on hierarchical level types supported, refer to the CPUID Leaf 1FH definition for the

actual level type numbers: “V2 Extended Topology Enumeration Leaf” in the Intel^® 64 and IA-32

Architectures Software Developer’s Manual, Volume 2A. Also see Section 9.9.1, “Hierarchical

Mapping of Shared Resources,” in the Intel^®64 and IA-32 Architectures Software Developer’s

Manual, Volume 3A.

and the bit description describes individual bits in registers.

Model specific registers and its bit-fields may be supported for a finite range of processor families/models. To distin-

guish between different processor family and/or models, software must use CPUID.01H leaf function to query the

combination of DisplayFamily and DisplayModel to determine model-specific availability of MSRs (see CPUID

instruction in Chapter 3, “Instruction Set Reference, A-L,” in the Intel^® 64 and IA-32 Architectures Software Devel-

oper’s Manual, Volume 2A). Table 2-1 lists the signature values of DisplayFamily and DisplayModel for various

processor families or processor number series.

Table 2-1. CPUID Signature Values of DisplayFamily_DisplayModel

DisplayFamily_DisplayModel

Processor Families/Processor Number Series

06_85H

Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series based on Knights Mill microarchitecture

06_57H

Intel® Xeon Phi™ Processor 3200, 5200, 7200 Series based on Knights Landing microarchitecture

06_8FH

4th generation Intel® Xeon® Scalable Processor Family based on Sapphire Rapids microarchitecture

06_BAH, 06_B7H, 06_BFH

13th generation Intel® Core™ processors supporting Raptor Lake performance hybrid architecture

06_97H, 06_9AH

12th generation Intel® Core™ processors supporting Alder Lake performance hybrid architecture

06_8CH, 06_8DH

11th generation Intel® Core™ processors based on Tiger Lake microarchitecture

06_A7H

11th generation Intel® Core™ processors based on Rocket Lake microarchitecture

06_7DH, 06_7EH

10th generation Intel® Core™ processors based on Ice Lake microarchitecture

06_A5H, 06_A6H

10th generation Intel® Core™ processors based on Comet Lake microarchitecture

06_66H

Intel® Core™ processors based on Cannon Lake microarchitecture

06_8EH, 06_9EH

7th generation Intel® Core™ processors based on Kaby Lake microarchitecture, 8th and 9th generation

Intel® Core™ processors based on Coffee Lake microarchitecture, Intel® Xeon® E processors based on

Coffee Lake microarchitecture

06_6AH, 06_6CH

3rd generation Intel® Xeon® Scalable Processor Family based on Ice Lake microarchitecture

06_55H

Intel® Xeon® Scalable Processor Family based on Skylake microarchitecture, 2nd generation Intel®

Xeon® Scalable Processor Family based on Cascade Lake product, and 3rd generation Intel® Xeon®

Scalable Processor Family based on Cooper Lake product

06_4EH, 06_5EH

6th generation Intel Core processors and Intel Xeon processor E3-1500m v5 product family and E3-

1200 v5 product family based on Skylake microarchitecture

Vol. 4

2-1

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-1. CPUID Signature Values of DisplayFamily_DisplayModel (Contd.)

DisplayFamily_DisplayModel

Processor Families/Processor Number Series

06_56H

Intel Xeon processor D-1500 product family based on Broadwell microarchitecture

06_4FH

Intel Xeon processor E5 v4 Family based on Broadwell microarchitecture, Intel Xeon processor E7 v4

Family, Intel Core i7-69xx Processor Extreme Edition

06_47H

5th generation Intel Core processors, Intel Xeon processor E3-1200 v4 product family based on

Broadwell microarchitecture

06_3DH

Intel Core M-5xxx Processor, 5th generation Intel Core processors based on Broadwell

microarchitecture

06_3FH

Intel Xeon processor E5-4600/2600/1600 v3 product families, Intel Xeon processor E7 v3 product

families based on Haswell-E microarchitecture, Intel Core i7-59xx Processor Extreme Edition

06_3CH, 06_45H, 06_46H

4th Generation Intel Core processor and Intel Xeon processor E3-1200 v3 product family based on

Haswell microarchitecture

06_3EH

Intel Xeon processor E7-8800/4800/2800 v2 product families based on Ivy Bridge-E

microarchitecture

06_3EH

Intel Xeon processor E5-2600/1600 v2 product families and Intel Xeon processor E5-2400 v2

product family based on Ivy Bridge-E microarchitecture, Intel Core i7-49xx Processor Extreme Edition

06_3AH

3rd Generation Intel Core Processor and Intel Xeon processor E3-1200 v2 product family based on Ivy

Bridge microarchitecture

06_2DH

Intel Xeon processor E5 Family based on Sandy Bridge microarchitecture, Intel Core i7-39xx

Processor Extreme Edition

06_2FH

Intel Xeon Processor E7 Family

06_2AH

Intel Xeon processor E3-1200 product family; 2nd Generation Intel Core i7, i5, i3 Processors 2xxx

Series

06_2EH

Intel Xeon processor 7500, 6500 series

06_25H, 06_2CH

Intel Xeon processors 3600, 5600 series, Intel Core i7, i5, and i3 Processors

06_1EH, 06_1FH

Intel Core i7 and i5 Processors

06_1AH

Intel Core i7 Processor, Intel Xeon processor 3400, 3500, 5500 series

06_1DH

Intel Xeon processor MP 7400 series

06_17H

Intel Xeon processor 3100, 3300, 5200, 5400 series, Intel Core 2 Quad processors 8000, 9000

series

06_0FH

Intel Xeon processor 3000, 3200, 5100, 5300, 7300 series, Intel Core 2 Quad processor 6000 series,

Intel Core 2 Extreme 6000 series, Intel Core 2 Duo 4000, 5000, 6000, 7000 series processors, Intel

Pentium dual-core processors

06_0EH

Intel Core Duo, Intel Core Solo processors

06_0DH

Intel Pentium M processor

06_86H, 06_96H, 06_9CH

Intel Atom® processors, Intel® Celeron® processors, Intel® Pentium® processors, and Intel® Pentium®

Silver processors based on Tremont Microarchitecture

06_7AH

Intel Atom processors based on Goldmont Plus microarchitecture

06_5FH

Intel Atom processors based on Goldmont microarchitecture (Denverton)

06_5CH

Intel Atom processors based on Goldmont microarchitecture

06_4CH

Intel Atom processor X7-Z8000 and X5-Z8000 series based on Airmont microarchitecture

06_5DH

Intel Atom processor X3-C3000 based on Silvermont microarchitecture

06_5AH

Intel Atom processor Z3500 series

06_4AH

Intel Atom processor Z3400 series

06_37H

Intel Atom processor E3000 series, Z3600 series, Z3700 series

06_4DH

Intel Atom processor C2000 series

2-2 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-1. CPUID Signature Values of DisplayFamily_DisplayModel (Contd.)

DisplayFamily_DisplayModel

Processor Families/Processor Number Series

06_36H

Intel Atom processor S1000 Series

06_1CH, 06_26H, 06_27H,

Intel Atom processor family, Intel Atom processor D2000, N2000, E2000, Z2000, C1000 series

06_35H, 06_36H

0F_06H

Intel Xeon processor 7100, 5000 Series, Intel Xeon Processor MP, Intel Pentium 4, Pentium D

processors

0F_03H, 0F_04H

Intel Xeon processor, Intel Xeon processor MP, Intel Pentium 4, Pentium D processors

06_09H

Intel Pentium M processor

0F_02H

Intel Xeon Processor, Intel Xeon processor MP, Intel Pentium 4 processors

0F_0H, 0F_01H

Intel Xeon Processor, Intel Xeon processor MP, Intel Pentium 4 processors

06_7H, 06_08H, 06_0AH,

Intel Pentium III Xeon processor, Intel Pentium III processor

06_0BH

06_03H, 06_05H

Intel Pentium II Xeon processor, Intel Pentium II processor

06_01H

Intel Pentium Pro processor

05_01H, 05_02H, 05_04H

Intel Pentium processor, Intel Pentium processor with MMX Technology

The Intel® Quark™ SoC X1000 processor can be identified by the signature of DisplayFamily_DisplayModel = 05_09H and

SteppingID = 0

2.1

ARCHITECTURAL MSRS

Many MSRs have carried over from one generation of IA-32 processors to the next and to Intel 64 processors. A

subset of MSRs and associated bit fields, which do not change on future processor generations, are now considered

architectural MSRs. For historical reasons (beginning with the Pentium 4 processor), these “architectural MSRs”

were given the prefix “IA32_”. Table 2-2 lists the architectural MSRs, their addresses, their current names, their

names in previous IA-32 processors, and bit fields that are considered architectural. MSR addresses outside Table

2-2 and certain bit fields in an MSR address that may overlap with architectural MSR addresses are model-specific.

Code that accesses a model-specific MSR and that is executed on a processor that does not support that MSR will

generate an exception.

Architectural MSR or individual bit fields in an architectural MSR may be introduced or transitioned at the granu-

larity of certain processor family/model or the presence of certain CPUID feature flags. The right-most column of

Table 2-2 provides information on the introduction of each architectural MSR or its individual fields. This informa-

tion is expressed either as signature values of “DF_DM” (see Table 2-1) or via CPUID flags.

Certain bit field position may be related to the maximum physical address width, the value of which is expressed

as “MAXPHYADDR” in Table 2-2. “MAXPHYADDR” is reported by CPUID.8000_0008H leaf.

MSR address range between 40000000H - 4000FFFFH is marked as a specially reserved range. All existing and

future processors will not implement any features using any MSR in this range.

Table 2-2. IA-32 Architectural MSRs

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

IA32_P5_MC_ADDR (P5_MC_ADDR)

See Section 2.23, “MSRs in Pentium

Pentium Processor

Processors.”

(05_01H)

IA32_P5_MC_TYPE (P5_MC_TYPE)

See Section 2.23, “MSRs in Pentium

DF_DM = 05_01H

Processors.”

IA32_MONITOR_FILTER_SIZE

See Section 9.10.5, “Monitor/Mwait

0F_03H

Address Range Determination.”

Vol. 4

2-3

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

10H

IA32_TIME_STAMP_COUNTER

See Section 18.17, “Time-Stamp Counter.”

05_01H

(TSC)

17H

IA32_PLATFORM_ID

Platform ID (R/O)

06_01H

(MSR_PLATFORM_ID )

The operating system can use this MSR to

determine “slot” information for the

processor and the proper microcode update

to load.

49:0

Reserved

52:50

Platform Id (R/O)

Contains information concerning the

intended platform for the processor.

52 51

0 Processor Flag 0

1 Processor Flag 1

0 Processor Flag 2

1 Processor Flag 3

0 Processor Flag 4

1 Processor Flag 5

0 Processor Flag 6

1 Processor Flag 7

63:53

Reserved

1BH

IA32_APIC_BASE

This register holds the APIC base address,

06_01H

permitting the relocation of the APIC

(APIC_BASE)

memory map. See Section 11.4.4, “Local

APIC Status and Location,” and Section

11.4.5, “Relocating the Local APIC

Registers.”

7:0

Reserved

BSP flag (R/W)

Reserved

Enable x2APIC mode.

06_1AH

APIC Global Enable (R/W)

(MAXPHYADDR - 1):12

APIC Base (R/W)

63: MAXPHYADDR

Reserved

3AH

IA32_FEATURE_CONTROL

Control Features in Intel 64 Processor (R/W)

If any one enumeration

condition for defined bit

field holds.

2-4 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

Lock bit (R/WO): (1 = locked).

If any one enumeration

condition for defined bit

When set, locks this MSR from being

field position greater than

written; writes to this bit will result in

bit 0 holds.

GP(0).

Note: Once the Lock bit is set, the contents

of this register cannot be modified.

Therefore the lock bit must be set after

configuring support for Intel Virtualization

Technology and prior to transferring control

to an option ROM or the OS. Hence, once

the Lock bit is set, the entire

IA32_FEATURE_CONTROL contents are

preserved across RESET when PWRGOOD is

not deasserted.

Enable VMX inside SMX operation (R/WL)

If CPUID.01H:ECX[5] = 1

This bit enables a system executive to use

&& CPUID.01H:ECX[6] = 1

VMX in conjunction with SMX to support

Intel® Trusted Execution Technology.

BIOS must set this bit only when the CPUID

function 1 returns VMX feature flag and

SMX feature flag set (ECX bits 5 and 6

respectively).

Enable VMX outside SMX operation (R/WL)

If CPUID.01H:ECX[5] = 1

This bit enables VMX for a system

executive that does not require SMX.

BIOS must set this bit only when the CPUID

function 1 returns the VMX feature flag set

(ECX bit 5).

7:3

Reserved

14:8

SENTER Local Function Enables (R/WL)

If CPUID.01H:ECX[6] = 1

When set, each bit in the field represents

an enable control for a corresponding

SENTER function. This field is supported

only if CPUID.1:ECX.[bit 6] is set.

SENTER Global Enable (R/WL)

If CPUID.01H:ECX[6] = 1

This bit must be set to enable SENTER leaf

functions. This bit is supported only if

CPUID.1:ECX.[bit 6] is set.

Reserved

SGX Launch Control Enable (R/WL)

If CPUID.(EAX=07H,

ECX=0H): ECX[30] = 1

This bit must be set to enable runtime re-

configuration of SGX Launch Control via the

IA32_SGXLEPUBKEYHASHn MSR.

SGX Global Enable (R/WL)

If CPUID.(EAX=07H,

ECX=0H): EBX[2] = 1

This bit must be set to enable SGX leaf

functions.

Reserved

Vol. 4

2-5

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

LMCE On (R/WL)

If IA32_MCG_CAP[27] = 1

When set, system software can program

the MSRs associated with LMCE to

configure delivery of some machine check

exceptions to a single logical processor.

63:21

Reserved

3BH

IA32_TSC_ADJUST

Per Logical Processor TSC Adjust (R/Write

If CPUID.(EAX=07H,

to clear)

ECX=0H): EBX[1] = 1

63:0

THREAD_ADJUST

Local offset value of the IA32_TSC for a

logical processor. Reset value is zero. A

write to IA32_TSC will modify the local

offset in IA32_TSC_ADJUST and the

content of IA32_TSC, but does not affect

the internal invariant TSC hardware.

48H

IA32_SPEC_CTRL

Speculation Control (R/W)

If any one of the

enumeration conditions for

The MSR bits are defined as logical

defined bit field positions

processor scope. On some core

holds.

implementations, the bits may impact

sibling logical processors on the same core.

This MSR has a value of 0 after reset and is

unaffected by INIT# or SIPI#.

Indirect Branch Restricted Speculation

If CPUID.(EAX=07H,

(IBRS). Restricts speculation of indirect

ECX=0):EDX[26]=1

branch.

Single Thread Indirect Branch Predictors

If CPUID.(EAX=07H,

(STIBP). Prevents indirect branch

ECX=0):EDX[27]=1

predictions on all logical processors on the

core from being controlled by any sibling

logical processor in the same core.

Speculative Store Bypass Disable (SSBD)

If CPUID.(EAX=07H,

delays speculative execution of a load until

ECX=0):EDX[31]=1

the addresses for all older stores are

known.

IPRED_DIS_U

If CPUID.(EAX=07H,

ECX=2):EDX[1]=1

If 1, enables IPRED_DIS control for CPL3.

IPRED_DIS_S

If CPUID.(EAX=07H,

ECX=2):EDX[1]=1

If 1, enables IPRED_DIS control for

CPL0/1/2.

RRSBA_DIS_U

If CPUID.(EAX=07H,

ECX=2):EDX[2]=1

If 1, disables RRSBA behavior for CPL3.

RRSBA_DIS_S

If CPUID.(EAX=07H,

ECX=2):EDX[2]=1

If 1, disables RRSBA behavior for CPL0/1/2.

2-6 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

PSFD

If CPUID.(EAX=07H,

ECX=2):EDX[0]=1

If 1, disables Fast Store Forwarding

Predictor. Note that setting bit 2 (SSBD)

also disables this.

DDPD_U

If CPUID.(EAX=07H,

ECX=2):EDX[3]=1

If 1, disables the Data Dependent

Prefetcher that examines data values in

memory while CPL = 3. Note that setting bit

2 (SSBD) also disables this.

Reserved

BHI_DIS_S

If CPUID.(EAX=07H,

ECX=2):EDX[4]=1

When ‘1, enables BHI_DIS_S behavior.

63:11

Reserved

49H

IA32_PRED_CMD

Prediction Command (WO)

If any one of the

enumeration conditions for

Gives software a way to issue commands

defined bit field positions

that affect the state of predictors.

holds.

Indirect Branch Prediction Barrier (IBPB)

If CPUID.(EAX=07H,

ECX=0):EDX[26]=1

63:1

Reserved

4EH

IA32_PPIN_CTL

Protected Processor Inventory Number

If CPUID.(EAX=07H,

Enable Control (R/W)

ECX=01H):EBX[0]=1¹

LockOut (R/WO)

If 0, indicates that further writes to

IA32_PPIN_CTL is allowed.

If 1, indicates that further writes to

IA32_PPIN_CTL is disallowed. Writing 1 to

this bit is only permitted if the Enable_PPIN

bit is clear.

The Privileged System Software Inventory

Agent should read IA32_PPIN_CTL[bit 1] to

determine if IA32_PPIN is accessible.

The Privileged System Software Inventory

Agent is not expected to write to this MSR.

Enable_PPIN (R/W)

If 1, indicates that IA32_PPIN is accessible

using RDMSR.

If 0, indicates that IA32_PPIN is

inaccessible using RDMSR. Any attempt to

read IA32_PPIN will cause #GP.

63:2

Reserved

Vol. 4

2-7

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

4FH

IA32_PPIN

Protected Processor Inventory Number

If CPUID.(EAX=07H,

(R/O)

ECX=01H):EBX[0]=1¹

63:0

Protected Processor Inventory Number

(R/O)

A unique value within a given CPUID

family/model/stepping signature that a

privileged inventory initialization agent can

access to identify each physical processor,

when access to IA32_PPIN is enabled.

Access to IA32_PPIN is permitted only if

IA32_PPIN_CTL[bits 1:0] = ‘10b’.

79H

121

IA32_BIOS_UPDT_TRIG

BIOS Update Trigger (W)

06_01H

(BIOS_UPDT_TRIG)

Executing a WRMSR instruction to this MSR

causes a microcode update to be loaded

into the processor. See Section 10.11.6,

“Microcode Update Loader.”

A processor may prevent writing to this

MSR when loading guest states on VM

entries or saving guest states on VM exits.

8BH

139

IA32_BIOS_SIGN_ID

BIOS Update Signature (R/W)

06_01H

(BIOS_SIGN/BBL_CR_D3)

Returns the microcode update signature

following the execution of CPUID.01H.

A processor may prevent writing to this

MSR when loading guest states on VM

entries or saving guest states on VM exits.

31:0

Reserved

63:32

It is recommended that this field be pre-

loaded with zero prior to executing CPUID.

If the field remains zero following the

execution of CPUID, this indicates that no

microcode update is loaded. Any non-zero

value is the microcode update signature.

2-8 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

8CH

140

IA32_SGXLEPUBKEYHASH0

IA32_SGXLEPUBKEYHASH[63:0] (R/W)

Bits 63:0 of the SHA256 digest of the

SIGSTRUCT.MODULUS for SGX Launch

Enclave. On reset, the default value is the

digest of Intel’s signing key.

Read permitted If

8DH

141

IA32_SGXLEPUBKEYHASH1

IA32_SGXLEPUBKEYHASH[127:64] (R/W)

CPUID.(EAX=12H,ECX=0H):

Bits 127:64 of the SHA256 digest of the

EAX[0]=1 &&

SIGSTRUCT.MODULUS for SGX Launch

CPUID.(EAX=07H,

Enclave. On reset, the default value is the

ECX=0H):ECX[30]=1.

digest of Intel’s signing key.

Write permitted if

8EH

142

IA32_SGXLEPUBKEYHASH2

IA32_SGXLEPUBKEYHASH[191:128] (R/W)

CPUID.(EAX=12H,ECX=0H):

EAX[0]=1 &&

Bits 191:128 of the SHA256 digest of the

IA32_FEATURE_CONTROL[

SIGSTRUCT.MODULUS for SGX Launch

17] = 1 &&

Enclave. On reset, the default value is the

IA32_FEATURE_CONTROL[

digest of Intel’s signing key.

0] = 1.

8FH

143

IA32_SGXLEPUBKEYHASH3

IA32_SGXLEPUBKEYHASH[255:192] (R/W)

Bits 255:192 of the SHA256 digest of the

SIGSTRUCT.MODULUS for SGX Launch

Enclave. On reset, the default value is the

digest of Intel’s signing key.

9BH

155

IA32_SMM_MONITOR_CTL

SMM Monitor Configuration (R/W)

If CPUID.01H: ECX[5]=1 ||

CPUID.01H: ECX[6] = 1

Valid (R/W)

Reserved

Controls SMI unblocking by VMXOFF (see

If IA32_VMX_MISC[28]

Section 32.14.4).

11:3

Reserved

31:12

MSEG Base (R/W)

63:32

Reserved

9EH

158

IA32_SMBASE

Base address of the logical processor’s

If IA32_VMX_MISC[15]

SMRAM image (R/O, SMM only).

BCH

188

IA32_MISC_PACKAGE_CTLS

Power Filtering Control (R/W)

IA32_ARCH_CAPABILITIES

This MSR has a value of 0 after reset and is

[10] = 1

unaffected by INIT# or SIPI#.

ENERGY_FILTERING_ENABLE (R/W)

IA32_ARCH_CAPABILITIES

If set, RAPL MSRs report filtered processor

[11] = 1

power consumption data.

This bit can be changed from 0 to 1, but

cannot be changed from 1 to 0. After

setting, all attempts to clear it are ignored

until the next processor reset.

63:1

Reserved.

Vol. 4

2-9

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

BDH

189

IA32_XAPIC_DISABLE_STATUS

xAPIC Disable Status (R/O)

If CPUID.(EAX-07H,

ECX=0):EDX[29]=1 and

IA32_ARCH_CAPABILITIES

[21] = 1

LEGACY_XAPIC_DISABLED

When set, indicates that the local APIC is in

x2APIC mode (IA32_APIC_BASE.EXTD = 1)

and that attempts to clear

IA32_APIC_BASE.EXTD will fail (e.g.,

WRMSR will #GP).

63:1

Reserved

C1H

193

IA32_PMC0

General Performance Counter 0 (R/W)

If CPUID.0AH: EAX[15:8] >

(PERFCTR0)

C2H

194

IA32_PMC1

General Performance Counter 1 (R/W)

If CPUID.0AH: EAX[15:8] >

(PERFCTR1)

C3H

195

IA32_PMC2

General Performance Counter 2 (R/W)

If CPUID.0AH: EAX[15:8] >

C4H

196

IA32_PMC3

General Performance Counter 3 (R/W)

If CPUID.0AH: EAX[15:8] >

C5H

197

IA32_PMC4

General Performance Counter 4 (R/W)

If CPUID.0AH: EAX[15:8] >

C6H

198

IA32_PMC5

General Performance Counter 5 (R/W)

If CPUID.0AH: EAX[15:8] >

C7H

199

IA32_PMC6

General Performance Counter 6 (R/W)

If CPUID.0AH: EAX[15:8] >

C8H

200

IA32_PMC7

General Performance Counter 7 (R/W)

If CPUID.0AH: EAX[15:8] >

CFH

207

IA32_CORE_CAPABILITIES

IA32 Core Capabilities Register

If CPUID.(EAX=07H,

ECX=0):EDX[30] = 1

63:0

Reserved.

No architecturally defined

bits.

E1H

225

IA32_UMWAIT_CONTROL

UMWAIT Control (R/W)

C0.2 is not allowed by the OS. Value of “1”

means all C0.2 requests revert to C0.1.

Reserved

31:2

Determines the maximum time in TSC-

quanta that the processor can reside in

either C0.1 or C0.2. A zero value indicates

no maximum time. The maximum time

value is a 32-bit value where the upper 30

bits come from this field and the lower two

bits are zero.

E7H

231

IA32_MPERF

TSC Frequency Clock Counter (R/Write to

If CPUID.06H: ECX[0] = 1

clear)

2-10 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

63:0

C0_MCNT: C0 TSC Frequency Clock Count

Increments at fixed interval (relative to TSC

freq.) when the logical processor is in C0.

Cleared upon overflow / wrap-around of

IA32_APERF.

E8H

232

IA32_APERF

Actual Performance Clock Counter (R/Write

If CPUID.06H: ECX[0] = 1

to clear)

63:0

C0_ACNT: C0 Actual Frequency Clock Count

Accumulates core clock counts at the

coordinated clock frequency, when the

logical processor is in C0.

Cleared upon overflow / wrap-around of

IA32_MPERF.

FEH

254

IA32_MTRRCAP

MTRR Capability (R/O)

06_01H

(MTRRcap)

See Section 12.11.2.1,

“IA32_MTRR_DEF_TYPE MSR.”

7:0

VCNT: The number of variable memory type

ranges in the processor.

Fixed range MTRRs are supported when

set.

Reserved

WC Supported when set.

SMRR Supported when set.

PRMRR supported when set.

63:13

Reserved

10AH

266

IA32_ARCH_CAPABILITIES

Enumeration of Architectural Features

If CPUID.(EAX=07H,

(R/O)

ECX=0):EDX[29]=1

RDCL_NO: The processor is not susceptible

to Rogue Data Cache Load (RDCL).

IBRS_ALL: The processor supports

enhanced IBRS.

RSBA: The processor supports RSB

Alternate. Alternative branch predictors

may be used by RET instructions when the

RSB is empty. SW using retpoline may be

affected by this behavior.

SKIP_L1DFL_VMENTRY: A value of 1

indicates the hypervisor need not flush the

L1D on VM entry.

SSB_NO: Processor is not susceptible to

Speculative Store Bypass.

MDS_NO: Processor is not susceptible to

Microarchitectural Data Sampling (MDS).

Vol. 4

2-11

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

IF_PSCHANGE_MC_NO: The processor is not

susceptible to a machine check error due to

modifying the size of a code page without

TLB invalidation.

TSX_CTRL: If 1, indicates presence of

IA32_TSX_CTRL MSR.

TAA_NO: If 1, processor is not affected by

TAA.

MCU_CONTROL: If 1, the processor

supports the IA32_MCU_CONTROL MSR.

MISC_PACKAGE_CTLS: The processor

supports IA32_MISC_PACKAGE_CTLS MSR.

ENERGY_FILTERING_CTL: The processor

supports setting and reading the

IA32_MISC_PACKAGE_CTLS[0]

(ENERGY_FILTERING_ENABLE) bit.

DOITM: If 1, the processor supports Data

Operand Independent Timing Mode.

SBDR_SSDP_NO: The processor is not

affected by either the Shared Buffers Data

Read (SBDR) vulnerability or the Sideband

Stale Data Propagator (SSDP).

FBSDP_NO: The processor is not affected

by the Fill Buffer Stale Data Propagator

(FBSDP).

PSDP_NO: The processor is not affected by

vulnerabilities involving the Primary Stale

Data Propagator (PSDP).

Reserved

FB_CLEAR: If 1, the processor supports

overwrite of fill buffer values as part of

MD_CLEAR operations with the VERW

instruction.

FB_CLEAR_CTRL: If 1, the processor

supports the IA32_MCU_OPT_CTRL MSR

and allows software to set bit 3 of that

MSR (FB_CLEAR_DIS).

RRSBA: A value of 1 indicates the processor

may have the RRSBA alternate prediction

behavior, if not disabled by RRSBA_DIS_U

or RRSBA_DIS_S.

BHI_NO: A value of 1 indicates BHI_NO

branch prediction behavior, regardless of

the value of IA32_SPEC_CTRL[BHI_DIS_S]

MSR bit.

2-12 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

XAPIC_DISABLE_STATUS: Enumerates that

the IA32_XAPIC_DISABLE_STATUS MSR

exists, and that bit 0 specifies whether the

legacy xAPIC is disabled and APIC state is

locked to x2APIC.

Reserved

OVERCLOCKING_STATUS: If set, the

IA32_OVERCLOCKING_STATUS MSR exists.

PBRSB_NO: If 1, the processor is not

affected by issues related to Post-Barrier

Return Stack Buffer Predictions.

63:25

Reserved

10BH

267

IA32_FLUSH_CMD

Flush Command (WO)

If any one of the

enumeration conditions for

Gives software a way to invalidate

defined bit field positions

structures with finer granularity than other

holds.

architectural methods.

L1D_FLUSH: Writeback and invalidate the

If CPUID.(EAX=07H,

L1 data cache.

ECX=0):EDX[28]=1

63:1

Reserved

10FH

271

IA32_TSX_FORCE_ABORT

TSX Force Abort

If CPUID.(EAX=07H,

ECX=0):EDX[13]=1

RTM_FORCE_ABORT

R/W, Default: 0

If 1, all RTM transactions abort with EAX

If CPUID.(EAX=07H,ECX=0):

code 0.

EDX[11]=1, bit 0 is always

1 and writes to change it

are ignored.

If SDV_ENABLE_RTM is 1,

bit 0 is always 0 and writes

to change it are ignored.

TSX_CPUID_CLEAR

R/W, Default: 0

When set,

Can be set only if

CPUID.(EAX=07H,ECX=0):EBX[11]=0 and

CPUID.(EAX=07H,ECX=0):

CPUID.(EAX=07H,ECX=0):EBX[4]=0.

EDX[11]=1 or if

SDV_ENABLE_RTM is 1.

SDV_ENABLE_RTM

R/W, Default: 0

When set,

If 0, can be set only if

CPUID.(EAX=07H,ECX=0):EDX[11]=0 and

CPUID.(EAX=07H,ECX=0):

the processor may not force abort RTM.

EDX[11]=1.

This unsupported mode should only be

used for software development and not for

production usage.

63:3

Reserved

Vol. 4

2-13

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

122H

290

IA32_TSX_CTRL

Thread scope. Not

architecturally serializing.

Available when

CPUID.ARCH_CAP(EAX=7H,

ECX = 0):EDX[29] = 1 and

IA32_ARCH_CAPABILITIES.

bit 7 = 1.

RTM_DISABLE

When set to 1, XBEGIN will always abort

with EAX code 0.

TSX_CPUID_CLEAR

When set to 1, CPUID.07H.EBX.RTM [bit 11]

and CPUID.07H.EBX.HLE [bit 4] report 0.

When set to 0 and the SKU supports TSX,

these bits will return 1.

63:2

Reserved

123H

291

IA32_MCU_OPT_CTRL

Microcode Update Option Control (R/W)

If CPUID.(EAX=07H,

ECX=0):EDX[9]=1 or

IA32_ARCH_CAPABILITIES

[18] = 1 or

IA32_ARCH_CAPABILITIES.

FB_CLEAR_CTRL=1

RNGDS_MITG_DIS (R/W)

If CPUID.(EAX=07H,

ECX=0):EDX[9]=1

If 0 (default), SRBDS mitigation is enabled

for RDRAND and RDSEED.

If 1, SRBDS mitigation is disabled for

RDRAND and RDSEED executed outside of

Intel SGX enclaves.

RTM_ALLOW

Read/Write

If 0, XBEGIN will always abort with EAX

Setting RTM_LOCKED

code 0.

prevents writes to this bit.

If 1, XBEGIN behavior depends on the value

of IA32_TSX_CTRL[RTM_DISABLE].

RTM_LOCKED

Read-Only status bit

When 1, RTM_ALLOW is locked at zero,

writes to RTM_ALLOW will be ignored.

FB_CLEAR_DIS

IA32_ARCH_CAPABILITIES.

If 1, prevents the VERW instruction from

FB_CLEAR_CTRL=1

performing an FB_CLEAR action.

GDS_MITG_DIS

If 0, the Gather Data Sampling mitigation is

enabled (patch load time default).

If 1 on all threads for a given core, the

Gather Data Sampling mitigation is disabled.

2-14 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

GDS_MITG_LOCK

If 0, not locked, and GDS_MITG_DIS is under

OS control.

If 1, locked and GDS_MITG_DIS is forced to

0 (writes are ignored).

63:6

Reserved

174H

372

IA32_SYSENTER_CS

SYSENTER_CS_MSR (R/W)

06_01H

15:0

CS Selector.

31:16

Not used.

Can be read and written.

63:32

Not used.

Writes ignored; reads

return zero.

175H

373

IA32_SYSENTER_ESP

SYSENTER_ESP_MSR (R/W)

06_01H

176H

374

IA32_SYSENTER_EIP

SYSENTER_EIP_MSR (R/W)

06_01H

179H

377

IA32_MCG_CAP (MCG_CAP)

Global Machine Check Capability (R/O)

06_01H

7:0

Count: Number of reporting banks.

MCG_CTL_P: IA32_MCG_CTL is present if

this bit is set.

MCG_EXT_P: Extended machine check state

registers are present if this bit is set.

MCP_CMCI_P: Support for corrected MC

06_01H

error event is present.

MCG_TES_P: Threshold-based error status

15:12

Reserved

23:16

MCG_EXT_CNT: Number of extended

machine check state registers present.

MCG_SER_P: The processor supports

software error recovery if this bit is set.

Reserved

MCG_ELOG_P: Indicates that the processor

06_3EH

allows platform firmware to be invoked

when an error is detected so that it may

provide additional platform specific

information in an ACPI format “Generic

Error Data Entry” that augments the data

included in machine check bank registers.

MCG_LMCE_P: Indicates that the processor

06_3EH

supports extended state in

IA32_MCG_STATUS and associated MSR

necessary to configure Local Machine Check

Exception (LMCE).

63:28

Reserved

Vol. 4

2-15

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

17AH

378

IA32_MCG_STATUS

Global Machine Check Status (R/W0)

06_01H

(MCG_STATUS)

RIPV. Restart IP valid.

06_01H

EIPV. Error IP valid.

06_01H

MCIP. Machine check in progress.

06_01H

LMCE_S

IA32_MCG_CAP.LMCE_P[27

] =1

63:4

Reserved

17BH

379

IA32_MCG_CTL (MCG_CTL)

Global Machine Check Control (R/W)

If IA32_MCG_CAP.CTL_P[8]

180H-

384-

Reserved

06_0EH²

185H

389

186H

390

IA32_PERFEVTSEL0

Performance Event Select Register 0 (R/W)

If CPUID.0AH: EAX[15:8] >

(PERFEVTSEL0)

7:0

Event Select: Selects a performance event

logic unit.

15:8

UMask: Qualifies the microarchitectural

condition to detect on the selected event

logic.

USR: Counts while in privilege level is not

ring 0.

OS: Counts while in privilege level is ring 0.

Edge: Enables edge detection if set.

PC: Enables pin control.

INT: Enables interrupt on counter overflow.

AnyThread: When set to 1, it enables

counting the associated event conditions

occurring across all logical processors

sharing a processor core. When set to 0, the

counter only increments the associated

event conditions occurring in the logical

processor which programmed the MSR.

EN: Enables the corresponding performance

counter to commence counting when this

bit is set.

INV: Invert the CMASK.

31:24

CMASK: When CMASK is not zero, the

corresponding performance counter

increments each cycle if the event count is

greater than or equal to the CMASK.

63:32

Reserved

2-16 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

187H

391

IA32_PERFEVTSEL1

Performance Event Select Register 1 (R/W)

If CPUID.0AH: EAX[15:8] >

(PERFEVTSEL1)

188H

392

IA32_PERFEVTSEL2

Performance Event Select Register 2 (R/W)

If CPUID.0AH: EAX[15:8] >

189H

393

IA32_PERFEVTSEL3

Performance Event Select Register 3 (R/W)

If CPUID.0AH: EAX[15:8] >

18AH

394

IA32_PERFEVTSEL4

Performance Event Select Register 4 (R/W)

If CPUID.0AH: EAX[15:8] >

18BH

395

IA32_PERFEVTSEL5

Performance Event Select Register 5 (R/W)

If CPUID.0AH: EAX[15:8] >

18CH

396

IA32_PERFEVTSEL6

Performance Event Select Register 6 (R/W)

If CPUID.0AH: EAX[15:8] >

18DH

397

IA32_PERFEVTSEL7

Performance Event Select Register 7 (R/W)

If CPUID.0AH: EAX[15:8] >

18AH-

394-

Reserved

06_0EH³

194H

404

195H

405

IA32_OVERCLOCKING_STATUS

Overclocking Status (R/O)

IA32_ARCH_CAPABILITIES[bit 23]

enumerates support for this MSR.

Overclocking Utilized

Indicates if specific forms of overclocking

have been enabled on this boot or reset

cycle: 0 indicates no, 1 indicates yes.

Undervolt Protection

Indicates if the “Dynamic OC Undervolt

Protection” security feature is active: 0

indicates disabled, 1indicates enabled.

Overclocking Secure Status

Indicates that overclocking capabilities have

been unlocked by BIOS, with or without

overclocking: 0 indicates Not Secured, 1

indicates Secure.

63:4

Reserved

196H-

406-

Reserved

06_0EH³

197H

407

198H

408

IA32_PERF_STATUS

Current Performance Status (R/O)

0F_03H

See Section 15.1.1, “Software Interface For

Initiating Performance State Transitions.”

15:0

Current Performance State Value.

63:16

Reserved

Vol. 4

2-17

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

199H

409

IA32_PERF_CTL

Performance Control MSR (R/W)

0F_03H

Software makes a request for a new

Performance state (P-State) by writing this

MSR. See Section 15.1.1, “Software

Interface For Initiating Performance State

Transitions.”

15:0

Target performance State Value.

31:16

Reserved

Intel® Dynamic Acceleration Technology

06_0FH (Mobile only)

Engage (R/W)

When set to 1: Disengages Intel Dynamic

Acceleration Technology.

63:33

Reserved

19AH

410

IA32_CLOCK_MODULATION

Clock Modulation Control (R/W)

If CPUID.01H:EDX[22] = 1

See Section 15.8.3, “Software Controlled

Clock Modulation.”

Extended On-Demand Clock Modulation

If CPUID.06H:EAX[5] = 1

Duty Cycle.

3:1

On-Demand Clock Modulation Duty Cycle:

If CPUID.01H:EDX[22] = 1

Specific encoded values for target duty

cycle modulation.

On-Demand Clock Modulation Enable: Set 1

If CPUID.01H:EDX[22] = 1

to enable modulation.

63:5

Reserved

19BH

411

IA32_THERM_INTERRUPT

Thermal Interrupt Control (R/W)

If CPUID.01H:EDX[22] = 1

Enables and disables the generation of an

interrupt on temperature transitions

detected with the processor’s thermal

sensors and thermal monitor.

See Section 15.8.2, “Thermal Monitor.”

High-Temperature Interrupt Enable

If CPUID.01H:EDX[22] = 1

Low-Temperature Interrupt Enable

If CPUID.01H:EDX[22] = 1

PROCHOT# Interrupt Enable

If CPUID.01H:EDX[22] = 1

FORCEPR# Interrupt Enable

If CPUID.01H:EDX[22] = 1

Critical Temperature Interrupt Enable

If CPUID.01H:EDX[22] = 1

7:5

Reserved

14:8

Threshold #1 Value

If CPUID.01H:EDX[22] = 1

Threshold #1 Interrupt Enable

If CPUID.01H:EDX[22] = 1

22:16

Threshold #2 Value

If CPUID.01H:EDX[22] = 1

Threshold #2 Interrupt Enable

If CPUID.01H:EDX[22] = 1

Power Limit Notification Enable

If CPUID.06H:EAX[4] = 1

Hardware Feedback Notification Enable

If CPUID.06H:EAX[24] = 1

2-18 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

63:26

Reserved

19CH

412

IA32_THERM_STATUS

Thermal Status Information (R/O)

If CPUID.01H:EDX[22] = 1

Contains status information about the

processor’s thermal sensor and automatic

thermal monitoring facilities.

See Section 15.8.2, “Thermal Monitor.”

Thermal Status (R/O)

If CPUID.01H:EDX[22] = 1

Thermal Status Log (R/W)

If CPUID.01H:EDX[22] = 1

PROCHOT # or FORCEPR# event (R/O)

If CPUID.01H:EDX[22] = 1

PROCHOT # or FORCEPR# log (R/WC0)

If CPUID.01H:EDX[22] = 1

Critical Temperature Status (R/O)

If CPUID.01H:EDX[22] = 1

Critical Temperature Status log (R/WC0)

If CPUID.01H:EDX[22] = 1

Thermal Threshold #1 Status (R/O)

If CPUID.01H:ECX[8] = 1

Thermal Threshold #1 log (R/WC0)

If CPUID.01H:ECX[8] = 1

Thermal Threshold #2 Status (R/O)

If CPUID.01H:ECX[8] = 1

Thermal Threshold #2 log (R/WC0)

If CPUID.01H:ECX[8] = 1

Power Limitation Status (R/O)

If CPUID.06H:EAX[4] = 1

Power Limitation log (R/WC0)

If CPUID.06H:EAX[4] = 1

Current Limit Status (R/O)

If CPUID.06H:EAX[7] = 1

Current Limit log (R/WC0)

If CPUID.06H:EAX[7] = 1

Cross Domain Limit Status (R/O)

If CPUID.06H:EAX[7] = 1

Cross Domain Limit log (R/WC0)

If CPUID.06H:EAX[7] = 1

22:16

Digital Readout (R/O)

If CPUID.06H:EAX[0] = 1

26:23

Reserved

30:27

Resolution in Degrees Celsius (R/O)

If CPUID.06H:EAX[0] = 1

Reading Valid (R/O)

If CPUID.06H:EAX[0] = 1

63:32

Reserved

1A0H

416

IA32_MISC_ENABLE

Enable Misc. Processor Features (R/W)

Allows a variety of processor functions to

be enabled and disabled.

Fast-Strings Enable

0F_0H

When set, the fast-strings feature (for REP

MOVS and REP STORS) is enabled (default).

When clear, fast-strings are disabled.

2:1

Reserved

Vol. 4

2-19

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

Automatic Thermal Control Circuit Enable

0F_0H

(R/W)

1 = Setting this bit enables the thermal

control circuit (TCC) portion of the

Intel Thermal Monitor feature. This

allows the processor to automatically

reduce power consumption in

response to TCC activation.

0 = Disabled.

Note: In some products clearing this bit

might be ignored in critical thermal

conditions, and TM1, TM2, and adaptive

thermal throttling will still be activated.

The default value of this field varies with

product. See respective tables where

default value is listed.

6:4

Reserved

Performance Monitoring Available (R)

0F_0H

1 = Performance monitoring enabled.

0 = Performance monitoring disabled.

10:8

Reserved

Branch Trace Storage Unavailable (R/O)

0F_0H

1 = Processor doesn’t support branch

trace storage (BTS).

0 = BTS is supported.

Processor Event Based Sampling (PEBS)

06_0FH

Unavailable (R/O)

1 = PEBS is not supported.

0 = PEBS is supported.

15:13

Reserved

Enhanced Intel SpeedStep Technology

If CPUID.01H: ECX[7] =1

Enable (R/W)

0= Enhanced Intel SpeedStep Technology

disabled.

1 = Enhanced Intel SpeedStep Technology

enabled.

Reserved

2-20 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

ENABLE MONITOR FSM (R/W)

0F_03H

When this bit is set to 0, the MONITOR

feature flag is not set (CPUID.01H:ECX[bit

3] = 0). This indicates that

MONITOR/MWAIT are not supported.

Software attempts to execute

MONITOR/MWAIT will cause #UD when this

bit is 0.

When this bit is set to 1 (default),

MONITOR/MWAIT are supported

(CPUID.01H:ECX[bit 3] = 1).

If the SSE3 feature flag ECX[0] is not set

(CPUID.01H:ECX[bit 0] = 0), the OS must

not attempt to alter this bit. BIOS must

leave it in the default state. Writing this bit

when the SSE3 feature flag is set to 0 may

generate a #GP exception.

21:19

Reserved

Limit CPUID Maxval (R/W)

0F_03H

When this bit is set to 1, CPUID.00H returns

a maximum value in EAX[7:0] of 2.

BIOS should contain a setup question that

allows users to specify when the installed

OS does not support CPUID functions

greater than 2.

Before setting this bit, BIOS must execute

the CPUID.0H and examine the maximum

value returned in EAX[7:0]. If the maximum

value is greater than 2, this bit is

supported.

Otherwise, this bit is not supported. Setting

this bit when the maximum value is not

greater than 2 may generate a #GP

exception.

Setting this bit may cause unexpected

behavior in software that depends on the

availability of CPUID leaves greater than 2.

xTPR Message Disable (R/W)

If CPUID.01H:ECX[14] = 1

When set to 1, xTPR messages are

disabled. xTPR messages are optional

messages that allow the processor to

inform the chipset of its priority.

Vol. 4

2-21

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

63:24

Reserved

Note: Some older processors defined one of

these bits as a disable for the execute-

disable feature of paging. If a processor

supports this bit, this information is

provided in the model-specific tables. See

Table 2-3 for the definition of this bit.

1B0H

432

IA32_ENERGY_PERF_BIAS

Performance Energy Bias Hint (R/W)

If CPUID.6H:ECX[3] = 1

3:0

Power Policy Preference:

0 indicates preference to highest

performance.

15 indicates preference to maximize

energy saving.

63:4

Reserved

1B1H

433

IA32_PACKAGE_THERM_STATUS

Package Thermal Status Information (R/O)

If CPUID.06H: EAX[6] = 1

Contains status information about the

package’s thermal sensor.

See Section 15.9, “Package Level Thermal

Management.”

Pkg Thermal Status (R/O)

Pkg Thermal Status Log (R/W)

Pkg PROCHOT # event (R/O)

Pkg PROCHOT # log (R/WC0)

Pkg Critical Temperature Status (R/O)

Pkg Critical Temperature Status Log

(R/WC0)

Pkg Thermal Threshold #1 Status (R/O)

Pkg Thermal Threshold #1 Log (R/WC0)

Pkg Thermal Threshold #2 Status (R/O)

Pkg Thermal Threshold #1 Log (R/WC0)

Pkg Power Limitation Status (R/O)

Pkg Power Limitation Log (R/WC0)

15:12

Reserved

22:16

Pkg Digital Readout (R/O)

25:23

Reserved

Hardware Feedback Interface Structure

If CPUID.06H:EAX.[19] = 1

Change Status

63:27

Reserved

2-22 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

1B2H

434

IA32_PACKAGE_THERM_INTERRUPT

Pkg Thermal Interrupt Control (R/W)

If CPUID.06H: EAX[6] = 1

Enables and disables the generation of an

interrupt on temperature transitions

detected with the package’s thermal

sensor.

See Section 15.9, “Package Level Thermal

Management.”

Pkg High-Temperature Interrupt Enable

Pkg Low-Temperature Interrupt Enable

Pkg PROCHOT# Interrupt Enable

Reserved

Pkg Overheat Interrupt Enable

7:5

Reserved

14:8

Pkg Threshold #1 Value

Pkg Threshold #1 Interrupt Enable

22:16

Pkg Threshold #2 Value

Pkg Threshold #2 Interrupt Enable

Pkg Power Limit Notification Enable

Hardware Feedback Interrupt Enable

If CPUID.06H:EAX.[19] = 1

63:26

Reserved

1C4H

452

IA32_XFD

Extended Feature Disable Control (R/W)

CPUID.(EAX=0DH,ECX=1):

Controls which XSAVE-enabled features are

temporarily disabled.

EAX[4] = 1

See Section 13.14 of the Intel^® 64 and

IA-32 Architectures Software Developer’s

Manual, Volume 1.

1C5H

453

IA32_XFD_ERR

Extended Feature Disable Error Code (R/W)

Reports which XSAVE-enabled features

CPUID.(EAX=0DH,ECX=1):

EAX[4] = 1

caused a fault due to being disabled.

See Section 13.14 of the Intel^® 64 and

IA-32 Architectures Software Developer’s

Manual, Volume 1.

1D9H

473

IA32_DEBUGCTL

Trace/Profile Resource Control (R/W)

06_0EH

(MSR_DEBUGCTLA, MSR_DEBUGCTLB)

LBR: Setting this bit to 1 enables the

06_01H

processor to record a running trace of the

most recent branches taken by the

processor in the LBR stack.

BTF: Setting this bit to 1 enables the

06_01H

processor to treat EFLAGS.TF as single-step

on branches instead of single-step on

instructions.

Vol. 4

2-23

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

BLD: Enable OS bus-lock detection. See

If (CPUID.(EAX=07H,

Section 18.3.1.6 of the Intel^® 64 and IA-32

ECX=0):ECX[24] = 1)

Architectures Software Developer’s

Manual, Volume 3B.

5:3

Reserved

TR: Setting this bit to 1 enables branch

06_0EH

trace messages to be sent.

BTS: Setting this bit enables branch trace

06_0EH

messages (BTMs) to be logged in a BTS

buffer.

BTINT: When clear, BTMs are logged in a

06_0EH

BTS buffer in circular fashion. When this bit

is set, an interrupt is generated by the BTS

facility when the BTS buffer is full.

1: BTS_OFF_OS: When set, BTS or BTM is

06_0FH

skipped if CPL = 0.

BTS_OFF_USR: When set, BTS or BTM is

06_0FH

skipped if CPL > 0.

FREEZE_LBRS_ON_PMI: When set, the LBR

If CPUID.01H: ECX[15] = 1

stack is frozen on a PMI request.

&& CPUID.0AH: EAX[7:0] >

FREEZE_PERFMON_ON_PMI: When set,

If CPUID.01H: ECX[15] = 1

each ENABLE bit of the global counter

&& CPUID.0AH: EAX[7:0] >

control MSR are frozen (address 38FH) on a

PMI request.

ENABLE_UNCORE_PMI: When set, enables

06_1AH

the logical processor to receive and

generate PMI on behalf of the uncore.

FREEZE_WHILE_SMM: When set, freezes

perfmon and trace messages while in SMM.

IA32_PERF_CAPABILITIES[

12] = 1

RTM_DEBUG: When set, enables DR7 debug

If (CPUID.(EAX=07H,

bit on XBEGIN.

ECX=0):EBX[11] = 1)

63:16

Reserved

1DDH

477

IA32_LER_FROM_IP

Last Event Record Source IP Register (R/W)

63:0

FROM_IP

Reset Value: 0

The source IP of the recorded branch or

event, in canonical form.

1DEH

478

IA32_LER_TO_IP

Last Event Record Destination IP Register

(R/W)

63:0

TO_IP

Reset Value: 0

The destination IP of the recorded branch

or event, in canonical form.

1E0H

480

IA32_LER_INFO

Last Event Record Info Register (R/W)

2-24 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

55:0

Undefined, may be zero or non-zero. Writes

Reset Value: 0

of non- zero values do not fault, but reads

may return a different value.

59:56

BR_TYPE

Reset Value: 0

The branch type recorded by this LBR.

Encodings match those of

IA32_LBR_x_INFO.

Undefined, may be zero or non-zero. Writes

Reset Value: 0

of non- zero values do not fault, but reads

may return a different value.

TSX_ABORT

Reset Value: 0

This LBR record is a TSX abort. On

processors that do not support Intel® TSX

(CPUID.07H.EBX.HLE[bit 4]=0 and

CPUID.07H.EBX.RTM[bit 11]=0), this bit is

undefined.

IN_TSX

Reset Value: 0

This LBR record records a branch that

retired during a TSX transaction. On

processors that do not support Intel® TSX

(CPUID.07H.EBX.HLE[bit 4]=0 and

CPUID.07H.EBX.RTM[bit 11]=0), this bit is

undefined.

MISPRED

Reset Value: 0

The recorded branch taken/not-taken

resolution (for conditional branches) or

target (for any indirect branch, including

RETs) was mispredicted.

1F2H

498

IA32_SMRR_PHYSBASE

SMRR Base Address (Writeable only in

SMM)

IA32_MTRRCAP.SMRR[11]

= 1

Base address of SMM memory range.

7:0

Type. Specifies memory type of the range.

11:8

Reserved

31:12

PhysBase

SMRR physical Base Address.

63:32

Reserved

1F3H

499

IA32_SMRR_PHYSMASK

SMRR Range Mask (Writeable only in SMM)

If IA32_MTRRCAP[SMRR] =

Range Mask of SMM memory range.

10:0

Reserved

Valid

Enable range mask.

31:12

PhysMask

SMRR address range mask.

63:32

Reserved

Vol. 4

2-25

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

1F8H

504

IA32_PLATFORM_DCA_CAP

DCA Capability (R)

If CPUID.01H: ECX[18] = 1

1F9H

505

IA32_CPU_DCA_CAP

If set, CPU supports Prefetch-Hint type.

If CPUID.01H: ECX[18] = 1

1FAH

506

IA32_DCA_0_CAP

DCA type 0 Status and Control register.

If CPUID.01H: ECX[18] = 1

DCA_ACTIVE: Set by HW when DCA is fuse-

enabled and no defeatures are set.

2:1

TRANSACTION

6:3

DCA_TYPE

10:7

DCA_QUEUE_SIZE

12:11

Reserved

16:13

DCA_DELAY: Writes will update the register

but have no HW side-effect.

23:17

Reserved

SW_BLOCK: SW can request DCA block by

setting this bit.

Reserved

HW_BLOCK: Set when DCA is blocked by HW

(e.g., CR0.CD = 1).

31:27

Reserved

200H

512

IA32_MTRR_PHYSBASE0

See Section 12.11.2.3, “Variable Range

If IA32_MTRRCAP[7:0] > 0

(MTRRphysBase0)

MTRRs.”

201H

513

IA32_MTRR_PHYSMASK0

MTRRphysMask0

If IA32_MTRRCAP[7:0] > 0

202H

514

IA32_MTRR_PHYSBASE1

MTRRphysBase1

If IA32_MTRRCAP[7:0] > 1

203H

515

IA32_MTRR_PHYSMASK1

MTRRphysMask1

If IA32_MTRRCAP[7:0] > 1

204H

516

IA32_MTRR_PHYSBASE2

MTRRphysBase2

If IA32_MTRRCAP[7:0] > 2

205H

517

IA32_MTRR_PHYSMASK2

MTRRphysMask2

If IA32_MTRRCAP[7:0] > 2

206H

518

IA32_MTRR_PHYSBASE3

MTRRphysBase3

If IA32_MTRRCAP[7:0] > 3

207H

519

IA32_MTRR_PHYSMASK3

MTRRphysMask3

If IA32_MTRRCAP[7:0] > 3

208H

520

IA32_MTRR_PHYSBASE4

MTRRphysBase4

If IA32_MTRRCAP[7:0] > 4

209H

521

IA32_MTRR_PHYSMASK4

MTRRphysMask4

If IA32_MTRRCAP[7:0] > 4

20AH

522

IA32_MTRR_PHYSBASE5

MTRRphysBase5

If IA32_MTRRCAP[7:0] > 5

20BH

523

IA32_MTRR_PHYSMASK5

MTRRphysMask5

If IA32_MTRRCAP[7:0] > 5

20CH

524

IA32_MTRR_PHYSBASE6

MTRRphysBase6

If IA32_MTRRCAP[7:0] > 6

20DH

525

IA32_MTRR_PHYSMASK6

MTRRphysMask6

If IA32_MTRRCAP[7:0] > 6

20EH

526

IA32_MTRR_PHYSBASE7

MTRRphysBase7

If IA32_MTRRCAP[7:0] > 7

20FH

527

IA32_MTRR_PHYSMASK7

MTRRphysMask7

If IA32_MTRRCAP[7:0] > 7

210H

528

IA32_MTRR_PHYSBASE8

MTRRphysBase8

If IA32_MTRRCAP[7:0] > 8

211H

529

IA32_MTRR_PHYSMASK8

MTRRphysMask8

If IA32_MTRRCAP[7:0] > 8

212H

530

IA32_MTRR_PHYSBASE9

MTRRphysBase9

If IA32_MTRRCAP[7:0] > 9

2-26 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

213H

531

IA32_MTRR_PHYSMASK9

MTRRphysMask9

If IA32_MTRRCAP[7:0] > 9

250H

592

IA32_MTRR_FIX64K_00000

MTRRfix64K_00000

If CPUID.01H:

EDX.MTRR[12] =1

258H

600

IA32_MTRR_FIX16K_80000

MTRRfix16K_80000

If CPUID.01H:

EDX.MTRR[12] =1

259H

601

IA32_MTRR_FIX16K_A0000

MTRRfix16K_A0000

If CPUID.01H:

EDX.MTRR[12] =1

268H

616

IA32_MTRR_FIX4K_C0000

See Section 12.11.2.2, “Fixed Range

If CPUID.01H:

(MTRRfix4K_C0000 )

MTRRs.”

EDX.MTRR[12] =1

269H

617

IA32_MTRR_FIX4K_C8000

MTRRfix4K_C8000

If CPUID.01H:

EDX.MTRR[12] =1

26AH

618

IA32_MTRR_FIX4K_D0000

MTRRfix4K_D0000

If CPUID.01H:

EDX.MTRR[12] =1

26BH

619

IA32_MTRR_FIX4K_D8000

MTRRfix4K_D8000

If CPUID.01H:

EDX.MTRR[12] =1

26CH

620

IA32_MTRR_FIX4K_E0000

MTRRfix4K_E0000

If CPUID.01H:

EDX.MTRR[12] =1

26DH

621

IA32_MTRR_FIX4K_E8000

MTRRfix4K_E8000

If CPUID.01H:

EDX.MTRR[12] =1

26EH

622

IA32_MTRR_FIX4K_F0000

MTRRfix4K_F0000

If CPUID.01H:

EDX.MTRR[12] =1

26FH

623

IA32_MTRR_FIX4K_F8000

MTRRfix4K_F8000

If CPUID.01H:

EDX.MTRR[12] =1

277H

631

IA32_PAT

IA32_PAT (R/W)

If CPUID.01H:

EDX.MTRR[16] =1

2:0

PA0

7:3

Reserved

10:8

PA1