Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

581H

1409

IA32_RTIT_ADDR0_B

Region 0 End Address (R/W)

If (CPUID.(EAX=07H,

ECX=1):EAX[2:0] > 0)

47:0

Virtual Address

63:48

SignExt_VA

582H

1410

IA32_RTIT_ADDR1_A

Region 1 Start Address (R/W)

If (CPUID.(EAX=07H,

ECX=1):EAX[2:0] > 1)

47:0

Virtual Address

63:48

SignExt_VA

583H

1411

IA32_RTIT_ADDR1_B

Region 1 End Address (R/W)

If (CPUID.(EAX=07H,

ECX=1):EAX[2:0] > 1)

47:0

Virtual Address

63:48

SignExt_VA

584H

1412

IA32_RTIT_ADDR2_A

Region 2 Start Address (R/W)

If (CPUID.(EAX=07H,

ECX=1):EAX[2:0] > 2)

47:0

Virtual Address

63:48

SignExt_VA

585H

1413

IA32_RTIT_ADDR2_B

Region 2 End Address (R/W)

If (CPUID.(EAX=07H,

ECX=1):EAX[2:0] > 2)

47:0

Virtual Address

63:48

SignExt_VA

586H

1414

IA32_RTIT_ADDR3_A

Region 3 Start Address (R/W)

If (CPUID.(EAX=07H,

ECX=1):EAX[2:0] > 3)

47:0

Virtual Address

63:48

SignExt_VA

587H

1415

IA32_RTIT_ADDR3_B

Region 3 End Address (R/W)

If (CPUID.(EAX=07H,

ECX=1):EAX[2:0] > 3)

47:0

Virtual Address

63:48

SignExt_VA

600H

1536

IA32_DS_AREA

DS Save Area (R/W)

If( CPUID.01H:EDX.DS[21] =

Points to the linear address of the first byte

of the DS buffer management area, which

is used to manage the BTS and PEBS

buffers.

See Section 20.6.3.4, “Debug Store (DS)

Mechanism.”

63:0

The linear address of the first byte of the

DS buffer management area, if IA-32e

mode is active.

31:0

The linear address of the first byte of the

DS buffer management area, if not in IA-

32e mode.

63:32

Reserved if not in IA-32e mode.

Vol. 4

2-45

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

6A0H

1696

IA32_U_CET

Configure User Mode CET (R/W)

Bits 1:0 are defined if

CPUID.(EAX=07H,

ECX=0H):ECX.CET_SS[07]

= 1.

Bits 5:2 and bits 63:10 are

defined if

CPUID.(EAX=07H,

ECX=0H):EDX.CET_IBT[20]

= 1.

SH_STK_EN: When set to 1, enable shadow

stacks at CPL3.

WR_SHSTK_EN: When set to 1, enables the

WRSSD/WRSSQ instructions.

ENDBR_EN: When set to 1, enables indirect

branch tracking.

LEG_IW_EN: Enable legacy compatibility

treatment for indirect branch tracking.

NO_TRACK_EN: When set to 1, enables use

of no-track prefix for indirect branch

tracking.

SUPPRESS_DIS: When set to 1, disables

suppression of CET indirect branch tracking

on legacy compatibility.

9:6

Reserved; must be zero.

SUPPRESS: When set to 1, indirect branch

tracking is suppressed. This bit can be

written to 1 only if TRACKER is written as

IDLE.

TRACKER: Value of the indirect branch

tracking state machine. Values: IDLE (0),

WAIT_FOR_ENDBRANCH(1).

63:12

EB_LEG_BITMAP_BASE: Linear address bits

63:12 of a legacy code page bitmap used

for legacy compatibility when indirect

branch tracking is enabled.

If the processor does not support Intel 64

architecture, these fields have only 32 bits;

bits 63:32 of the MSRs are reserved. On

processors that support Intel 64

architecture this value cannot represent a

non-canonical address. In protected mode,

only 31:0 are used.

6A2H

1698

IA32_S_CET

Configure Supervisor Mode CET (R/W)

See IA32_U_CET (6A0H)

for reference; similar

format.

2-46 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

6A4H

1700

IA32_PL0_SSP

Linear address to be loaded into SSP on

If CPUID.(EAX=07H,

transition to privilege level 0. (R/W)

ECX=0H):ECX.CET_SS[07]

= 1

If the processor does not support Intel 64

architecture, these fields have only 32 bits;

bits 63:32 of the MSRs are reserved. On

processors that support Intel 64

architecture this value cannot represent a

non-canonical address. In protected mode,

only 31:0 are loaded. Bits 1:0 of the MSR

must be 0. Transitions to privilege level 0

will check that bit 2 is also 0.

6A5H

1701

IA32_PL1_SSP

Linear address to be loaded into SSP on

If CPUID.(EAX=07H,

transition to privilege level 1. (R/W)

ECX=0H):ECX.CET_SS[07]

= 1

If the processor does not support Intel 64

architecture, these fields have only 32 bits;

bits 63:32 of the MSRs are reserved. On

processors that support Intel 64

architecture this value cannot represent a

non-canonical address. In protected mode,

only 31:0 are loaded. Bits 1:0 of the MSR

must be 0. Transitions to privilege level 1

from a higher privilege level will check that

bit 2 is also 0.

6A6H

1702

IA32_PL2_SSP

Linear address to be loaded into SSP on

If CPUID.(EAX=07H,

transition to privilege level 2. (R/W)

ECX=0H):ECX.CET_SS[07]

= 1

If the processor does not support Intel 64

architecture, these fields have only 32 bits;

bits 63:32 of the MSRs are reserved. On

processors that support Intel 64

architecture this value cannot represent a

non-canonical address. In protected mode,

only 31:0 are loaded. Bits 1:0 of the MSR

must be 0. Transitions to privilege level 2

from a higher privilege level will check that

bit 2 is also 0.

6A7H

1703

IA32_PL3_SSP

Linear address to be loaded into SSP on

If CPUID.(EAX=07H,

transition to privilege level 3. (R/W)

ECX=0H):ECX.CET_SS[07]

= 1

If the processor does not support Intel 64

architecture, these fields have only 32 bits;

bits 63:32 of the MSRs are reserved. On

processors that support Intel 64

architecture this value cannot represent a

non-canonical address. In protected mode,

only 31:0 are loaded. Bits 1:0 of the MSR

must be 0.

Vol. 4

2-47

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

6A8H

1704

IA32_INTERRUPT_SSP_TABLE_ADDR

Linear address of a table of seven shadow

If CPUID.(EAX=07H,

stack pointers that are selected in IA-32e

ECX=0H):ECX.CET_SS[07]

mode using the IST index (when not 0) from

= 1

the interrupt gate descriptor. (R/W)

This MSR is not present on processors that

do not support Intel 64 architecture. This

field cannot represent a non-canonical

address.

6E0H

1760

IA32_TSC_DEADLINE

TSC Target of Local APIC’s TSC Deadline

If CPUID.01H:ECX.[24] = 1

Mode (R/W)

6E1H

1761

IA32_PKRS

Specifies the PK permissions associated

If CPUID.(EAX=07H,

with each protection domain for supervisor

ECX=0H):ECX.PKS [31] = 1

pages (R/W)

31:0

For domain i (i between 0 and 15), bits 2i

and 2i+1 contain the AD and WD

permissions, respectively.

63:32

Reserved.

770H

1904

IA32_PM_ENABLE

Enable/disable HWP (R/W)

If CPUID.06H:EAX.[7] = 1

HWP_ENABLE (R/W1-Once)

If CPUID.06H:EAX.[7] = 1

See Section 15.4.2, “Enabling HWP.”

63:1

Reserved

771H

1905

IA32_HWP_CAPABILITIES

HWP Performance Range Enumeration

If CPUID.06H:EAX.[7] = 1

(R/O)

7:0

Highest_Performance

If CPUID.06H:EAX.[7] = 1

See Section 15.4.3, “HWP Performance

Range and Dynamic Capabilities.”

15:8

Guaranteed_Performance

If CPUID.06H:EAX.[7] = 1

See Section 15.4.3, “HWP Performance

Range and Dynamic Capabilities.”

23:16

Most_Efficient_Performance

If CPUID.06H:EAX.[7] = 1

See Section 15.4.3, “HWP Performance

Range and Dynamic Capabilities”.

31:24

Lowest_Performance

If CPUID.06H:EAX.[7] = 1

See Section 15.4.3, “HWP Performance

Range and Dynamic Capabilities.”

63:32

Reserved

772H

1906

IA32_HWP_REQUEST_PKG

Power Management Control Hints for All

If CPUID.06H:EAX.[11] = 1

Logical Processors in a Package (R/W)

7:0

Minimum_Performance

If CPUID.06H:EAX.[11] = 1

See Section 15.4.4, “Managing HWP.”

15:8

Maximum_Performance

If CPUID.06H:EAX.[11] = 1

See Section 15.4.4, “Managing HWP.”

2-48 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

23:16

Desired_Performance

If CPUID.06H:EAX.[11] = 1

See Section 15.4.4, “Managing HWP.”

31:24

Energy_Performance_Preference

If CPUID.06H:EAX.[11] = 1

See Section 15.4.4, “Managing HWP.”

CPUID.06H:EAX.[10] = 1

41:32

Activity_Window

If CPUID.06H:EAX.[11] = 1

See Section 15.4.4, “Managing HWP.”

CPUID.06H:EAX.[9] = 1

63:42

Reserved

773H

1907

IA32_HWP_INTERRUPT

Control HWP Native Interrupts (R/W)

If CPUID.06H:EAX.[8] = 1

EN_Guaranteed_Performance_Change

If CPUID.06H:EAX.[8] = 1

See Section 15.4.6, “HWP Notifications.”

EN_Excursion_Minimum

If CPUID.06H:EAX.[8] = 1

See Section 15.4.6, “HWP Notifications.”

63:2

Reserved

774H

1908

IA32_HWP_REQUEST

Power Management Control Hints to a

If CPUID.06H:EAX.[7] = 1

Logical Processor (R/W)

7:0

Minimum_Performance

If CPUID.06H:EAX.[7] = 1

See Section 15.4.4, “Managing HWP.”

15:8

Maximum_Performance

If CPUID.06H:EAX.[7] = 1

See Section 15.4.4, “Managing HWP.”

23:16

Desired_Performance

If CPUID.06H:EAX.[7] = 1

See Section 15.4.4, “Managing HWP.”

31:24

Energy_Performance_Preference

If CPUID.06H:EAX.[7] = 1

&& CPUID.06H:EAX.[10] =

See Section 15.4.4, “Managing HWP.”

41:32

Activity_Window

If CPUID.06H:EAX.[7] = 1

&& CPUID.06H:EAX.[9] = 1

See Section 15.4.4, “Managing HWP.”

Package_Control

If CPUID.06H:EAX.[7] = 1

&& CPUID.06H:EAX.[11] =

See Section 15.4.4, “Managing HWP.”

63:43

Reserved

775H

1909

IA32_PECI_HWP_REQUEST_INFO

7:0

Minimum Performance

(MINIMUM_PERFORMANCE): Used by OS to

read the latest value of PECI minimum

performance input. Default value is 0.

15:8

Maximum Performance

(MAXIMUM_PERFORMANCE): Used by OS to

read the latest value of PECI maximum

performance input. Default value is 0.

23:16

Reserved.

Vol. 4

2-49

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

31:24

Energy Performance Preference

(ENERGY_PERFORMANCE_PREFERENCE):

Used by OS to read the latest value of PECI

Energy Performance Preference input.

Default value is 0.

59:32

Reserved.

EPP PECI Override (EPP_PECI_OVERRIDE):

Indicates whether PECI is currently

overriding the Energy Performance

Preference input. If set to ‘1’, PECI is

overriding the Energy Performance

Preference input. If clear (0), OS has control

over Energy Performance Preference input.

Default value is 0.

Reserved.

Max PECI Override (MAX_PECI_OVERRIDE):

Indicates whether PECI is currently

overriding the Maximum Performance

input. If set to ‘1’, PECI is overriding the

Maximum Performance input. If clear (0), OS

has control over Maximum Performance

input. Default value is 0.

Min PECI Override (MIN_PECI_OVERRIDE):

Indicates whether PECI is currently

overriding the Minimum Performance input.

If set to ‘1’, PECI is overriding the Minimum

Performance input. If clear (0), OS has

control over Minimum Performance input.

Default value is 0.

776H

1910

IA32_HWP_CTL

If CPUID.06H:EAX.[22] = 1

PKG_CTL_POLARITY

If CPUID.06H:EAX.[22] = 1

Defines which HWP Request MSR is used

whether Thread level or package level.

When package MSR is used, the thread MSR

valid bits define which thread MSR fields

override the package.

Default value is 0.

63:1

Reserved

777H

1911

IA32_HWP_STATUS

Log bits indicating changes to Guaranteed &

If CPUID.06H:EAX.[7] = 1

excursions to Minimum (R/W)

Guaranteed_Performance_Change (R/WC0)

If CPUID.06H:EAX.[7] = 1

See Section 15.4.5, “HWP Feedback.”

Reserved

Excursion_To_Minimum (R/WC0)

If CPUID.06H:EAX.[7] = 1

See Section 15.4.5, “HWP Feedback.”

2-50 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

63:3

Reserved

802H

2050

IA32_X2APIC_APICID

x2APIC ID Register (R/O)

If CPUID.01H:ECX[21] = 1

&& IA32_APIC_BASE.[10] =

803H

2051

IA32_X2APIC_VERSION

x2APIC Version Register (R/O)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

808H

2056

IA32_X2APIC_TPR

x2APIC Task Priority Register (R/W)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

80AH

2058

IA32_X2APIC_PPR

x2APIC Processor Priority Register (R/O)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

80BH

2059

IA32_X2APIC_EOI

x2APIC EOI Register (W/O)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

80DH

2061

IA32_X2APIC_LDR

x2APIC Logical Destination Register (R/O)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

80FH

2063

IA32_X2APIC_SIVR

x2APIC Spurious Interrupt Vector Register

If CPUID.01H:ECX.[21] = 1

(R/W)

&& IA32_APIC_BASE.[10] =

810H

2064

IA32_X2APIC_ISR0

x2APIC In-Service Register Bits 31:0 (R/O)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

811H

2065

IA32_X2APIC_ISR1

x2APIC In-Service Register Bits 63:32 (R/O)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

812H

2066

IA32_X2APIC_ISR2

x2APIC In-Service Register Bits 95:64 (R/O)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

813H

2067

IA32_X2APIC_ISR3

x2APIC In-Service Register Bits 127:96

If CPUID.01H:ECX.[21] = 1

(R/O)

&& IA32_APIC_BASE.[10] =

814H

2068

IA32_X2APIC_ISR4

x2APIC In-Service Register Bits 159:128

If CPUID.01H:ECX.[21] = 1

(R/O)

&& IA32_APIC_BASE.[10] =

815H

2069

IA32_X2APIC_ISR5

x2APIC In-Service Register Bits 191:160

If CPUID.01H:ECX.[21] = 1

(R/O)

&& IA32_APIC_BASE.[10] =

816H

2070

IA32_X2APIC_ISR6

x2APIC In-Service Register Bits 223:192

If CPUID.01H:ECX.[21] = 1

(R/O)

&& IA32_APIC_BASE.[10] =

817H

2071

IA32_X2APIC_ISR7

x2APIC In-Service Register Bits 255:224

If CPUID.01H:ECX.[21] = 1

(R/O)

&& IA32_APIC_BASE.[10] =

Vol. 4

2-51

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

818H

2072

IA32_X2APIC_TMR0

x2APIC Trigger Mode Register Bits 31:0

If CPUID.01H:ECX.[21] = 1

(R/O)

&& IA32_APIC_BASE.[10] =

819H

2073

IA32_X2APIC_TMR1

x2APIC Trigger Mode Register Bits 63:32

If CPUID.01H:ECX.[21] = 1

(R/O)

&& IA32_APIC_BASE.[10] =

81AH

2074

IA32_X2APIC_TMR2

x2APIC Trigger Mode Register Bits 95:64

If CPUID.01H:ECX.[21] = 1

(R/O)

&& IA32_APIC_BASE.[10] =

81BH

2075

IA32_X2APIC_TMR3

x2APIC Trigger Mode Register Bits 127:96

If CPUID.01H:ECX.[21] = 1

(R/O)

&& IA32_APIC_BASE.[10] =

81CH

2076

IA32_X2APIC_TMR4

x2APIC Trigger Mode Register Bits

If CPUID.01H:ECX.[21] = 1

159:128 (R/O)

&& IA32_APIC_BASE.[10] =

81DH

2077

IA32_X2APIC_TMR5

x2APIC Trigger Mode Register Bits

If CPUID.01H:ECX.[21] = 1

191:160 (R/O)

&& IA32_APIC_BASE.[10] =

81EH

2078

IA32_X2APIC_TMR6

x2APIC Trigger Mode Register Bits

If ( CPUID.01H:ECX.[21] = 1

223:192 (R/O)

&& IA32_APIC_BASE.[10] =

81FH

2079

IA32_X2APIC_TMR7

x2APIC Trigger Mode Register Bits

If CPUID.01H:ECX.[21] = 1

255:224 (R/O)

&& IA32_APIC_BASE.[10] =

820H

2080

IA32_X2APIC_IRR0

x2APIC Interrupt Request Register Bits

If CPUID.01H:ECX.[21] = 1

31:0 (R/O)

&& IA32_APIC_BASE.[10] =

821H

2081

IA32_X2APIC_IRR1

x2APIC Interrupt Request Register Bits

If CPUID.01H:ECX.[21] = 1

63:32 (R/O)

&& IA32_APIC_BASE.[10] =

822H

2082

IA32_X2APIC_IRR2

x2APIC Interrupt Request Register Bits

If CPUID.01H:ECX.[21] = 1

95:64 (R/O)

&& IA32_APIC_BASE.[10] =

823H

2083

IA32_X2APIC_IRR3

x2APIC Interrupt Request Register Bits

If CPUID.01H:ECX.[21] = 1

127:96 (R/O)

&& IA32_APIC_BASE.[10] =

824H

2084

IA32_X2APIC_IRR4

x2APIC Interrupt Request Register Bits

If CPUID.01H:ECX.[21] = 1

159:128 (R/O)

&& IA32_APIC_BASE.[10] =

825H

2085

IA32_X2APIC_IRR5

x2APIC Interrupt Request Register Bits

If CPUID.01H:ECX.[21] = 1

191:160 (R/O)

&& IA32_APIC_BASE.[10] =

826H

2086

IA32_X2APIC_IRR6

x2APIC Interrupt Request Register Bits

If CPUID.01H:ECX.[21] = 1

223:192 (R/O)

&& IA32_APIC_BASE.[10] =

2-52 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

827H

2087

IA32_X2APIC_IRR7

x2APIC Interrupt Request Register Bits

If CPUID.01H:ECX.[21] = 1

255:224 (R/O)

&& IA32_APIC_BASE.[10] =

828H

2088

IA32_X2APIC_ESR

x2APIC Error Status Register (R/W)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

82FH

2095

IA32_X2APIC_LVT_CMCI

x2APIC LVT Corrected Machine Check

If CPUID.01H:ECX.[21] = 1

Interrupt Register (R/W)

&& IA32_APIC_BASE.[10] =

830H

2096

IA32_X2APIC_ICR

x2APIC Interrupt Command Register (R/W)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

832H

2098

IA32_X2APIC_LVT_TIMER

x2APIC LVT Timer Interrupt Register (R/W)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

833H

2099

IA32_X2APIC_LVT_THERMAL

x2APIC LVT Thermal Sensor Interrupt

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

834H

2100

IA32_X2APIC_LVT_PMI

x2APIC LVT Performance Monitor Interrupt

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

835H

2101

IA32_X2APIC_LVT_LINT0

x2APIC LVT LINT0 Register (R/W)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

836H

2102

IA32_X2APIC_LVT_LINT1

x2APIC LVT LINT1 Register (R/W)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

837H

2103

IA32_X2APIC_LVT_ERROR

x2APIC LVT Error Register (R/W)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

838H

2104

IA32_X2APIC_INIT_COUNT

x2APIC Initial Count Register (R/W)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

839H

2105

IA32_X2APIC_CUR_COUNT

x2APIC Current Count Register (R/O)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

83EH

2110

IA32_X2APIC_DIV_CONF

x2APIC Divide Configuration Register (R/W)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

83FH

2111

IA32_X2APIC_SELF_IPI

x2APIC Self IPI Register (W/O)

If CPUID.01H:ECX.[21] = 1

&& IA32_APIC_BASE.[10] =

981H

2433

IA32_TME_CAPABILITY

Memory Encryption Capability MSR

If CPUID.07H:ECX.[13] = 1

Support for AES-XTS 128-bit encryption

algorithm.

(NIST standard)

Vol. 4

2-53

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

Support for AES-XTS 128-bit encryption

with integrity algorithm.

Support for AES-XTS 256-bit encryption

algorithm.

30:3

Reserved.

TME encryption bypass supported.

35:32

MK_TME_MAX_KEYID_BITS

Number of bits which can be allocated for

usage as key identifiers for multi-key

memory encryption.

4 bits allow for a maximum value of 15,

which could address 32K keys.

Zero if TME-MK is not supported.

50:36

MK_TME_MAX_KEYS

Indicates the maximum number of keys

which are available for usage.

This value may not be a power of 2.

KeyID 0 is specially reserved and is not

accounted for in this field.

63:51

Reserved.

982H

2434

IA32_TME_ACTIVATE

Memory Encryption Activation MSR

If CPUID.07H:ECX.[13] = 1

This MSR is used to lock the MSRs listed

below. Any write to the following MSRs will

be ignored after they are locked. The lock is

reset when CPU is reset.

• IA32_TME_ACTIVATE

• IA32_TME_EXCLUDE_MASK

• IA32_TME_EXCLUDE_BASE

Note that IA32_TME_EXCLUDE_MASK and

IA32_TME_EXCLUDE_BASE must be

configured before IA32_TME_ACTIVATE.

Lock R/O - Will be set upon successful

WRMSR (or first SMI); written value ignored.

Hardware Encryption Enable

This bit also enables TME-MK; TME-MK

cannot be enabled without enabling

encryption hardware.

Key Select

0: Create a new TME key (expected

cold/warm boot).

1: Restore the TME key from storage

(Expected when resume from standby).

2-54 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

Save TME Key for Standby

Save key into storage to be used when

resume from standby.

Note: This may not be supported in all

processors.

7:4

TME Policy/Encryption Algorithm

Only algorithms enumerated in

IA32_TME_CAPABILITY are allowed.

For example:

0000 - AES-XTS-128.

0001 - AES-XTS-128 with integrity.

0010 - AES-XTS-256.

Other values are invalid.

30:8

Reserved.

TME Encryption Bypass Enable

When encryption hardware is enabled:

• Total Memory Encryption is enabled

using a CPU generated ephemeral key

based on a hardware random number

generator when this bit is set to 0.

• Total Memory Encryption is bypassed (no

encryption/decryption for KeyID0) when

this bit is set to 1.

Software must inspect Hardware

Encryption Enable (bit 1) and TME

encryption bypass Enable (bit 31) to

determine if TME encryption is enabled.

35:32

MK_TME_KEYID_BITS

Reserved if TME-MK is not enumerated,

otherwise:

The number of key identifier bits to allocate

to TME-MK usage. Similar to enumeration,

this is an encoded value.

Writing a value greater than

MK_TME_MAX_KEYID_BITS will result in

#GP.

Writing a non-zero value to this field will

#GP if bit 1 of EAX (Hardware Encryption

Enable) is not also set to ‘1, as encryption

hardware must be enabled to use TME-MK.

Example: To support 255 keys, this field

would be set to a value of 8.

47:36

Reserved.

Vol. 4

2-55

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

63:48

MK_TME_CRYPTO_ALGS

Reserved if TME-MK is not enumerated,

otherwise:

Bit 48: AES-XTS 128.

Bit 49: AES-XTS 128 with integrity.

Bit 50: AES-XTS 256.

Bit 63:51: Reserved (#GP)

Bitmask for BIOS to set which encryption

algorithms are allowed for TME-MK, would

be later enforced by the key loading ISA (‘1

= allowed).

983H

2435

IA32_TME_EXCLUDE_MASK

Memory Encryption Exclude Mask

If CPUID.07H:ECX.[13] = 1

10:0

Reserved.

Enable: When set to ‘1’, then

TME_EXCLUDE_BASE and

TME_EXCLUDE_MASK are used to define an

exclusion region for TME/TME-MK (for

KeyID=0).

MAXPHYSADDR-1:12

TMEEMASK: This field indicates the bits

that must match TMEEBASE in order to

qualify as a TME/TME-MK (for KeyID=0)

exclusion memory range access.

63:MAXPHYSADDR

Reserved; must be zero.

984H

2436

IA32_TME_EXCLUDE_BASE

Memory Encryption Exclude Base

IF CPUID.07H:ECX.[13] = 1

11:0

Reserved.

MAXPHYSADDR-1:12

TMEEBASE: Base physical address to be

excluded for TME/TME-MK (for KeyID=0)

encryption.

63:MAXPHYSADDR

Reserved; must be zero.

985H

2437

IA32_UINTR_RR

User Interrupt Request Register (R/W)

CPUID.07H.01H:EDX[13]=1

63:0

UIRR

Bitmap of requested user interrupt vectors.

986H

2438

IA32_UINTR_HANDLER

User Interrupt Handler Address (R/W)

CPUID.07H.01H:EDX[13]=1

63:0

UIHANDLER

User interrupt handler linear address.

987H

2439

IA32_UINTR_STACKADJUST

User Interrupt Stack Adjustment (R/W)

CPUID.07H.01H:EDX[13]=1

LOAD_RSP

User interrupt stack mode.

2:1

Reserved.

2-56 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

63:3

STACK_ADJUST

Stack adjust value.

988H

2440

IA32_UINTR_MISC

User-Interrupt Target-Table Size and

Notification Vector (R/W)

CPUID.07H.01H:EDX[13]=1

31:0

UITTSZ

The highest index of a valid entry in the

user-interrupt target table. Valid entries are

indices 0..UITTSZ (inclusive).

39:32

UINV

User-interrupt notification vector.

63:40

Reserved.

989H

2441

IA32_UINTR_PD

User Interrupt PID Address (R/W)

CPUID.07H.01H:EDX[13]=1

5:0

Reserved.

63:6

UPIDADDR

User-interrupt notification processing

accesses a UPID at this linear address.

98AH

2442

IA32_UINTR_TT

User-Interrupt Target Table (R/W)

CPUID.07H.01H:EDX[13]=1

SENDUIPI_ENABLE

User-interrupt target table is valid.

3:1

Reserved.

63:4

UITTADDR

User-interrupt target table base linear

address.

990H

2448

IA32_COPY_STATUS⁵

Status of Most Recent Platform to Local or

If ((CPUID.19H:EBX[4] = 1)

Local to Platform Copies (R/O)

&& (CPUID.(07H,0).ECX[23]

= 1))

IWKEY_COPY_SUCCESSFUL

If ((CPUID.19H:EBX[4] = 1)

Status of most recent copy to or from

&& (CPUID.(07H,0).ECX[23]

= 1))

IWKeyBackup

63:1

Reserved

991H

2449

IA32_IWKEYBACKUP_STATUS⁵

Information about IWKeyBackup Register

If ((CPUID.19H:EBX[4] = 1)

(R/O)

&& (CPUID.(07H,0).ECX[23]

=1))

Vol. 4

2-57

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

Backup/Restore Valid

IF ((CPUID.19H:EBX[4] = 1)

&& (CPUID.(07H,0).ECX[23]

Cleared when a write to IWKeyBackup is

=1))

initiated, and then set when the latest

write of IWKeyBackup has been written to

storage that persists across S3/S4 sleep

state. If S3/S4 is entered between when an

IWKeyBackup write occurs and when this

bit is set, then IWKeyBackup may not be

recovered after S3/S4 exit. During S3/S4

sleep state exit (system wake up), this bit is

cleared. It is set again when IWKeyBackup is

restored from persistent storage and thus

available to be copied to IWKey using

IA32_COPY_PLATFORM_TO_LOCAL MSR.

Another write to IWKeyBackup (via

IA32_COPY_LOCAL_TO_PLATFORM MSR)

may fail if a previous write has not yet set

this bit.

Reserved

Backup Key Storage Read/Write Error

IF ((CPUID.19H:EBX[4] = 1)

&& (CPUID.(07H,0).ECX[23]

Updated prior to backup/restore valid being

=1))

set. Set when an error is encountered while

backing up or restoring a key to persistent

storage.

IWKeyBackup Consumed

IF ((CPUID.19H:EBX[4] = 1)

&& (CPUID.(07H,0).ECX[23]

Set after the previous backup operation has

=1))

been consumed by the platform. This does

not indicate that the system is ready for a

second IWKeyBackup write as the previous

IWKeyBackup write may still need to set

Backup/restore valid.

63:4

Reserved

C80H

3200

IA32_DEBUG_INTERFACE

Silicon Debug Feature Control (R/W)

If CPUID.01H:ECX.[11] = 1

Enable (R/W)

If CPUID.01H:ECX.[11] = 1

BIOS set 1 to enable Silicon debug features.

Default is 0.

29:1

Reserved

Lock (R/W): If 1, locks any further change to

If CPUID.01H:ECX.[11] = 1

the MSR. The lock bit is set automatically on

the first SMI assertion even if not explicitly

set by BIOS. Default is 0.

Debug Occurred (R/O): This “sticky bit” is set

If CPUID.01H:ECX.[11] = 1

by hardware to indicate the status of bit 0.

Default is 0.

63:32

Reserved

C81H

3201

IA32_L3_QOS_CFG

L3 QOS Configuration (R/W)

If ( CPUID.(EAX=10H,

ECX=1):ECX.[2] = 1 )

2-58 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

Enable (R/W)

Set 1 to enable L3 CAT masks and COS to

operate in Code and Data Prioritization

(CDP) mode.

63:1

Reserved. Attempts to write to reserved

bits result in a #GP(0).

C82H

3202

IA32_L2_QOS_CFG

L2 QOS Configuration (R/W)

If ( CPUID.(EAX=10H,

ECX=2):ECX.[2] = 1 )

Enable (R/W)

Set 1 to enable L2 CAT masks and COS to

operate in Code and Data Prioritization

(CDP) mode.

63:1

Reserved. Attempts to write to reserved

bits result in a #GP(0).

C83H

3203

IA32_L3_IO_QOS_CFG

L3 I/O QOS Configuration (R/W)

If ( CPUID.(EAX=0FH,

ECX=1):EAX.[10:9] = 1 )

This MSR is used to enable the I/O RDT

features.

L3 I/O RDT Allocation Enable

L3 I/O RDT Monitoring Enable

63:2

Reserved

C8DH

3213

IA32_QM_EVTSEL

Monitoring Event Select Register (R/W)

If ( CPUID.(EAX=07H,

ECX=0):EBX.[12] = 1 )

7:0

Event ID: ID of a supported monitoring

event to report via IA32_QM_CTR.

31: 8

Reserved

N+31:32

Resource Monitoring ID: ID for monitoring

N = Ceil (Log₂ (

hardware to report monitored data via

CPUID.(EAX= 0FH,

IA32_QM_CTR.

ECX=0H).EBX[31:0] +1))

63:N+32

Reserved

C8EH

3214

IA32_QM_CTR

Monitoring Counter Register (R/O)

If ( CPUID.(EAX=07H,

ECX=0):EBX.[12] = 1 )

61:0

Resource Monitored Data

Unavailable: If 1, indicates data for this

RMID is not available or not monitored for

this resource or RMID.

Error: If 1, indicates an unsupported RMID

or event type was written to

IA32_PQR_QM_EVTSEL.

C8FH

3215

IA32_PQR_ASSOC

Resource Association Register (R/W)

If ( (CPUID.(EAX=07H,

ECX=0):EBX[12] =1) or

(CPUID.(EAX=07H,

ECX=0):EBX[15] =1 ) )

Vol. 4

2-59

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

N-1:0

Resource Monitoring ID (R/W): ID for

N = Ceil (Log₂ (

monitoring hardware to track internal

CPUID.(EAX= 0FH,

operation, e.g., memory access.

ECX=0H).EBX[31:0] +1))

31:N

Reserved

63:32

COS (R/W): The class of service (COS) to

If ( CPUID.(EAX=07H,

enforce (on writes); returns the current COS

ECX=0):EBX.[15] = 1 )

when read.

C90H

3216

Reserved MSR Address Space for CAT

See Section 18.19.4.1, “Enumeration and

Mask Registers

Detection Support of Cache Allocation

Technology.”

D8FH

3471

C90H

3216

IA32_L3_MASK_0

L3 CAT Mask for COS0 (R/W)

If (CPUID.(EAX=10H,

ECX=0H):EBX[1] != 0)

31:0

Capacity Bit Mask (R/W)

63:32

Reserved

C90H+

3216+n

IA32_L3_MASK_n

L3 CAT Mask for COSn (R/W)

n = CPUID.(EAX=10H,

ECX=1H):EDX[15:0]

31:0

Capacity Bit Mask (R/W)

63:32

Reserved

D10H

3344

Reserved MSR Address Space for L2

See Section 18.19.4.1, “Enumeration and

CAT Mask Registers

Detection Support of Cache Allocation

Technology.”

D4FH

3407

D10H

3344

IA32_L2_MASK_0

L2 CAT Mask for COS0 (R/W)

If (CPUID.(EAX=10H,

ECX=0H):EBX[2] != 0)

31:0

Capacity Bit Mask (R/W)

63:32

Reserved

D10H+

3344+n

IA32_L2_MASK_n

L2 CAT Mask for COSn (R/W)

n = CPUID.(EAX=10H,

ECX=2H):EDX[15:0]

31:0

Capacity Bit Mask (R/W)

63:32

Reserved

D90H

3472

IA32_BNDCFGS

Supervisor State of MPX Configuration

If (CPUID.(EAX=07H,

(R/W)

ECX=0H):EBX[14] = 1)

EN: Enable Intel MPX in supervisor mode.

BNDPRESERVE: Preserve the bounds

registers for near branch instructions in the

absence of the BND prefix.

2-60 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

11:2

Reserved, must be zero.

63:12

Base Address of Bound Directory.

D91H

3473

IA32_COPY_LOCAL_TO_PLATFORM⁵

Copy Local State to Platform State (W)

IF ((CPUID.19H:EBX[4] = 1)

&& (CPUID.(EAX=07H,

ECX=0H).ECX[23] = 1))

IWKeyBackup

IF ((CPUID.19H:EBX[4] = 1)

&& (CPUID.(EAX=07H,

Copy IWKey to IWKeyBackup

ECX=0H).ECX[23] = 1))

63:1

Reserved

D92H

3474

IA32_COPY_PLATFORM_TO_LOCAL⁵

Copy Platform State to Local State (W)

IF ((CPUID.19H:EBX[4] = 1)

&& (CPUID.(EAX=07H,

ECX=0H).ECX[23] = 1))

IWKeyBackup

IF ((CPUID.19H:EBX[4] = 1)

&& (CPUID.(EAX=07H,

Copy IWKeyBackup to IWKey

ECX=0H).ECX[23] = 1))

63:1

Reserved

D93H

3475

IA32_PASID

Process Address Space Identifier (R/W)

19:0

Process address space identifier (PASID).

Specifies the PASID of the currently

running software thread.

30:20

Reserved

Valid. Execution of ENQCMD causes a #GP if

this bit is clear.

63:32

Reserved

DA0H

3488

IA32_XSS

Extended Supervisor State Mask (R/W)

If( CPUID.(0DH, 1):EAX.[3] =

7:0

Reserved.

PT State (R/W)

Reserved.

PASID State (R/W)

CET_U State (R/W)

CET_S State (R/W)

HDC State (R/W)

UINTR State (R/W)

LBR State (R/W)

HWP State (R/W)

63:17

Reserved.

DB0H

3504

IA32_PKG_HDC_CTL

Package Level Enable/disable HDC (R/W)

If CPUID.06H:EAX.[13] = 1

Vol. 4

2-61

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

HDC_Pkg_Enable (R/W)

If CPUID.06H:EAX.[13] = 1

Force HDC idling or wake up HDC-idled

logical processors in the package. See

Section 15.5.2, “Package level Enabling

HDC.”

63:1

Reserved

DB1H

3505

IA32_PM_CTL1

Enable/disable HWP (R/W)

If CPUID.06H:EAX.[13] = 1

HDC_Allow_Block (R/W)

If CPUID.06H:EAX.[13] = 1

Allow/Block this logical processor for

package level HDC control. See Section

15.5.3.

63:1

Reserved

DB2H

3506

IA32_THREAD_STALL

Per-Logical_Processor_ID HDC Idle

If CPUID.06H:EAX.[13] = 1

Residency (R/0)

63:0

Stall_Cycle_Cnt (R/W)

If CPUID.06H:EAX.[13] = 1

Stalled cycles due to HDC forced idle on this

logical processor. See Section 15.5.4.1.

1200H

4608

IA32_LBR_x_INFO

Last Branch Record Entry X Info Register

(R/W)

An attempt to read or write

121FH

4639

IA32_LBR_x_INFO such that x ≥

IA32_LBR_DEPTH.DEPTH will #GP.

15:0

CYC_CNT

Reset Value: 0

The elapsed CPU cycles (saturating) since

the last LBR was recorded. See Section

18.1.3.3.

55:16

Undefined, may be zero or non-zero. Writes

Reset Value: 0

of non- zero values do not fault, but reads

may return a different value.

59:56

BR_TYPE

Reset Value: 0

The branch type recorded by this LBR.

Encodings:

0000B: COND

0001B: JMP Indirect

0010B: JMP Direct

0011B: CALL Indirect

0100B: CALL Direct

0101B: RET

011xB: Reserved

1xxxB: Other Branch

CYC_CNT_VALID

Reset Value: 0

CYC_CNT value is valid. See Section

19.1.3.3.

2-62 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

TSX_ABORT

Reset Value: 0

This LBR record is a TSX abort. On

processors that do not support Intel TSX

(CPUID.07H.EBX.HLE[bit 4]=0 and

CPUID.07H.EBX.RTM[bit 11]=0), this bit is

undefined.

IN_TSX

Reset Value: 0

This LBR record records a branch that

retired during a TSX transaction. On

processors that do not support Intel TSX

(CPUID.07H.EBX.HLE[bit 4]=0 and

CPUID.07H.EBX.RTM[bit 11]=0), this bit is

undefined.

MISPRED

Reset Value: 0

The recorded branch direction (conditional

branch) or target (indirect branch) was

mispredicted.

1406H

5126

IA32_MCU_CONTROL

MCU Control (R/W)

CPUID.07H.0H:EDX[29]=1

Controls the behavior of the Microcode

Update Trigger MSR,

MSR.IA32_ARCH_CAPABILI

IA32_BIOS_UPDT_TRIG.

TIES.MCU_CONTROL=1

LOCK

Once set, further writes to this MSR will

cause a #GP(0) fault. Bypassed during SMM

if EN_SMM_BYPASS (bit 2) is set.

DIS_MCU_LOAD

If this bit is set on a given logical processor,

then any subsequent attempts to load a

microcode update by that logical processor

will be silently dropped (WRMSR 0x79 has

no effect).

EN_SMM_BYPASS

If set, then writes to IA32_MCU_CONTROL

are allowed during SMM regardless of the

LOCK bit. This enables BIOS to Opt-In to the

SMM Bypass functionality.

63:3

Reserved.

14CEH

5326

IA32_LBR_CTL

Last Branch Record Enabling and

Configuration Register (R/W)

LBREn

Reset Value: 0

When set, enables LBR recording.

Reset Value: 0

When set, allows LBR recording when CPL

== 0.

Vol. 4

2-63

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

USR

Reset Value: 0

When set, allows LBR recording when CPL

!= 0.

CALL_STACK

Reset Value: 0

When set, records branches in call-stack

mode. See Section 19.1.2.4.

15:4

Reserved

Reset Value: 0

COND

When set, records taken conditional

branches. See Section 19.1.2.3.

NEAR_REL_JMP

When set, records near relative JMPs. See

Section 19.1.2.3.

NEAR_IND_JMP

When set, records near indirect JMPs. See

Section 19.1.2.3.

NEAR_REL_CALL

When set, records near relative CALLs. See

Section 19.1.2.3.

NEAR_IND_CALL

When set, records near indirect CALLs. See

Section 19.1.2.3.

NEAR_RET

When set, records near RETs. See Section

19.1.2.3.

OTHER_BRANCH

When set, records other branches. See

Section 19.1.2.3.

63:23

Reserved

14CFH

5327

IA32_LBR_DEPTH

Last Branch Record Maximum Stack Depth

N:0

DEPTH

Reset Value: Varies

The number of LBRs to be used for

recording. Supported values are indicated

by the bitmap in

CPUID.(EAX=01CH,ECX=0):EAX[7:0]. The

reset value will match the maximum

supported by the CPU. Writes of

unsupported values will #GP fault.

63:N+1

Reserved

Reset Value: 0

2-64 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

1500H

5376

IA32_LBR_x_FROM_IP

Last Branch Record entry X source IP

An attempt to read or write

151FH

5407

IA32_LBR_x_FROM_IP such that x ≥

IA32_LBR_DEPTH.DEPTH will #GP.

63:0

FROM_IP

Reset Value: 0

The source IP of the recorded branch or

event, in canonical form. Writes to bits

above MAXLINADDR-1 are ignored.

1600H

5632

IA32_LBR_x_TO_IP

Last Branch Record Entry X Destination IP

An attempt to read or write

161FH

5663

IA32_LBR_x_TO_IP such that x ≥

IA32_LBR_DEPTH.DEPTH will #GP.

63:0

TO_IP

Reset Value: 0

The destination IP of the recorded branch

or event, in canonical form. Writes to bits

above MAXLINADDR-1 are ignored.

17D0H

6096

IA32_HW_FEEDBACK_PTR

Hardware Feedback Interface Pointer

If CPUID.06H:EAX.[19] = 1

Valid (R/W)

When set to 1, indicates a valid pointer is

programmed into the ADDR field of the

MSR.

11:1

Reserved

(MAXPHYADDR-1):12

ADDR (R/W)

Physical address of the page frame of the

first page of the hardware feedback

interface structure.

63:MAXPHYADDR

Reserved

17D1H

6097

IA32_HW_FEEDBACK_CONFIG

Hardware Feedback Interface Configuration

If CPUID.06H:EAX.[19] = 1

Enable (R/W)

When set to 1, enables the hardware

feedback interface.

63:1

Reserved

17D2H

6098

IA32_THREAD_FEEDBACK_CHAR

Thread Feedback Characteristics (R/O)

If CPUID.06H:EAX.[23] = 1

7:0

Application Class ID, pointing into the Intel

Thread Director structure.

62:8

Reserved

Vol. 4

2-65

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

Valid bit. When set to 1 the OS Scheduler

can use the Class ID (in bits 7:0) for its

scheduling decisions.

If this bit is 0, the Class ID field should be

ignored. It is recommended that the OS

uses the last known Class ID of the

software thread for its scheduling

decisions.

17D4H

6100

IA32_HW_FEEDBACK_THREAD_CONFI

Hardware Feedback Thread Configuration

(R/W)

Enables Intel Thread Director. When set to

1, logical processor scope Intel Thread

Director is enabled. Default is 0 (disabled).

63:1

Reserved

17DAH

6106

IA32_HRESET_ENABLE

History Reset Enable (R/W)

Enable reset of the Intel Thread Director

history.

31:1

Reserved for other capabilities that can be

reset by the HRESET instruction.

63:32

Reserved

1B01H

6913

IA32_UARCH_MISC_CTL

IA32_ARCH_CAPABILITIES[

12]=1

Data Operand Independent Timing Mode

(DOITM)

IA32_ARCH_CAPABILITIES[

12]=1

63:1

Reserved

4000_

Reserved MSR Address Space

All existing and future processors will not

0000H

implement MSRs in this range.

4000_

00FFH

C000_

IA32_EFER

Extended Feature Enables

If (

0080H

CPUID.80000001H:EDX.[2

0] ||

CPUID.80000001H:EDX.[2

9])

SYSCALL Enable: IA32_EFER.SCE (R/W)

Enables SYSCALL/SYSRET instructions in

64-bit mode.

7:1

Reserved

IA-32e Mode Enable: IA32_EFER.LME (R/W)

Enables IA-32e mode operation.

Reserved

2-66 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-2. IA-32 Architectural MSRs (Contd.)

Architectural MSR Name / Bit Fields

Address

(Former MSR Name)

MSR/Bit Description

Comment

Hex

Decimal

IA-32e Mode Active: IA32_EFER.LMA (R)

Indicates IA-32e mode is active when set.

Execute Disable Bit Enable: IA32_EFER.NXE

(R/W)

63:12

Reserved

C000_

IA32_STAR

System Call Target Address (R/W)

0081H

CPUID.80000001:EDX.[29]

= 1

C000_

IA32_LSTAR

IA-32e Mode System Call Target Address

0082H

(R/W)

CPUID.80000001:EDX.[29]

= 1

Target RIP for the called procedure when

SYSCALL is executed in 64-bit mode.

C000_

IA32_CSTAR

IA-32e Mode System Call Target Address

0083H

(R/W)

CPUID.80000001:EDX.[29]

= 1

Not used, as the SYSCALL instruction is not

recognized in compatibility mode.

C000_

IA32_FMASK

System Call Flag Mask (R/W)

0084H

CPUID.80000001:EDX.[29]

= 1

C000_

IA32_FS_BASE

Map of BASE Address of FS (R/W)

0100H

CPUID.80000001:EDX.[29]

= 1

C000_

IA32_GS_BASE

Map of BASE Address of GS (R/W)

0101H

CPUID.80000001:EDX.[29]

= 1

C000_

IA32_KERNEL_GS_BASE

Swap Target of BASE Address of GS (R/W)

0102H

CPUID.80000001:EDX.[29]

= 1

C000_

IA32_TSC_AUX

Auxiliary TSC (R/W)

If CPUID.80000001H:

0103H

EDX[27] = 1 or

CPUID.(EAX=7,ECX=0):ECX[

bit 22] = 1

31:0

AUX: Auxiliary signature of TSC.

63:32

Reserved

NOTES:

1. Some older processors may have supported this MSR as model-specific and do not enumerate it with CPUID.

2. In processors based on Intel NetBurst® microarchitecture, MSR addresses 180H-197H are supported, software must treat them as

model-specific. Starting with Intel Core Duo processors, MSR addresses 180H-185H, 188H-197H are reserved.

3. The *_ADDR MSRs may or may not be present; this depends on flag settings in IA32_MCi_STATUS. See Section 16.3.2.3 and Section

16.3.2.4 for more information.

4. MAXPHYADDR is reported by CPUID.80000008H:EAX[7:0].

5. Further details on Key Locker and usage of this MSR can be found here:

https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.

Vol. 4

2-67

MODEL-SPECIFIC REGISTERS (MSRS)

2.2

MSRS IN THE INTEL® CORE™ 2 PROCESSOR FAMILY

Table 2-3 lists model-specific registers (MSRs) for the Intel Core 2 processor family and for Intel Xeon processors

based on Intel Core microarchitecture, architectural MSR addresses are also included in Table 2-3. These proces-

sors have a CPUID Signature DisplayFamily_DisplayModel value of 06_0FH, see Table 2-1.

MSRs listed in Table 2-2 and Table 2-3 are also supported by processors based on the Enhanced Intel Core microar-

chitecture. Processors based on the Enhanced Intel Core microarchitecture have a CPUID Signature DisplayFami-

ly_DisplayModel value of 06_17H.

The column “Shared/Unique” applies to multi-core processors based on Intel Core microarchitecture. “Unique”

means each processor core has a separate MSR, or a bit field in an MSR governs only a core independently.

“Shared” means the MSR or the bit field in an MSR address governs the operation of both processor cores.

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture

Shared/

Address

Unique

Bit Description

Hex

Dec

IA32_P5_MC_ADDR

Unique

See Section 2.23, “MSRs in Pentium Processors.”

IA32_P5_MC_TYPE

Unique

See Section 2.23, “MSRs in Pentium Processors.”

IA32_MONITOR_FILTER_SIZE

Unique

See Section 9.10.5, “Monitor/Mwait Address Range

Determination,” and Table 2-2.

10H

IA32_TIME_STAMP_COUNTER

Unique

See Section 18.17, “Time-Stamp Counter,” and see

Table 2-2.

17H

IA32_PLATFORM_ID

Shared

Platform ID (R)

See Table 2-2.

17H

MSR_PLATFORM_ID

Shared

Model Specific Platform ID (R)

7:0

Reserved

12:8

Maximum Qualified Ratio (R)

The maximum allowed bus ratio.

49:13

Reserved

52:50

See Table 2-2.

63:53

Reserved

1BH

IA32_APIC_BASE

Unique

See Section 11.4.4, “Local APIC Status and Location,” and

Table 2-2.

2AH

MSR_EBL_CR_POWERON

Shared

Processor Hard Power-On Configuration (R/W)

Enables and disables processor features; (R) indicates

current processor configuration.

Reserved

Data Error Checking Enable (R/W)

1 = Enabled; 0 = Disabled

Note: Not all processors implement R/W.

Response Error Checking Enable (R/W)

1 = Enabled; 0 = Disabled

Note: Not all processor implements R/W.

2-68 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

MCERR# Drive Enable (R/W)

1 = Enabled; 0 = Disabled

Note: Not all processors implement R/W.

Address Parity Enable (R/W)

1 = Enabled; 0 = Disabled

Note: Not all processors implement R/W.

Reserved

BINIT# Driver Enable (R/W)

1 = Enabled; 0 = Disabled

Note: Not all processors implement R/W.

Output Tri-state Enabled (R/O)

1 = Enabled; 0 = Disabled

Execute BIST (R/O)

1 = Enabled; 0 = Disabled

MCERR# Observation Enabled (R/O)

1 = Enabled; 0 = Disabled

Intel TXT Capable Chipset. (R/O)

1 = Present; 0 = Not Present

BINIT# Observation Enabled (R/O)

1 = Enabled; 0 = Disabled

Reserved

1 MByte Power on Reset Vector (R/O)

1 = 1 MByte; 0 = 4 GBytes

Reserved

17:16

APIC Cluster ID (R/O)

N/2 Non-Integer Bus Ratio (R/O)

0 = Integer ratio; 1 = Non-integer ratio

Reserved

21: 20

Symmetric Arbitration ID (R/O)

26:22

Integer Bus Frequency Ratio (R/O)

3AH

MSR_FEATURE_CONTROL

Unique

Control Features in Intel 64 Processor (R/W)

See Table 2-2.

Unique

SMRR Enable (R/WL)

When this bit is set and the lock bit is set, this makes the

SMRR_PHYS_BASE and SMRR_PHYS_MASK registers

read visible and writeable while in SMM.

Vol. 4

2-69

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

40H

MSR_LASTBRANCH_0_FROM_IP

Unique

Last Branch Record 0 From IP (R/W)

One of four pairs of last branch record registers on the

last branch record stack. The From_IP part of the stack

contains pointers to the source instruction. See also:

• Last Branch Record Stack TOS at 1C9H.

• Section 18.5.

41H

MSR_LASTBRANCH_1_FROM_IP

Unique

Last Branch Record 1 From IP (R/W)

See description of MSR_LASTBRANCH_0_FROM_IP.

42H

MSR_LASTBRANCH_2_FROM_IP

Unique

Last Branch Record 2 From IP (R/W)

See description of MSR_LASTBRANCH_0_FROM_IP.

43H

MSR_LASTBRANCH_3_FROM_IP

Unique

Last Branch Record 3 From IP (R/W)

See description of MSR_LASTBRANCH_0_FROM_IP.

60H

MSR_LASTBRANCH_0_TO_IP

Unique

Last Branch Record 0 To IP (R/W)

One of four pairs of last branch record registers on the

last branch record stack. This To_IP part of the stack

contains pointers to the destination instruction.

61H

MSR_LASTBRANCH_1_TO_IP

Unique

Last Branch Record 1 To IP (R/W)

See description of MSR_LASTBRANCH_0_TO_IP.

62H

MSR_LASTBRANCH_2_TO_IP

Unique

Last Branch Record 2 To IP (R/W)

See description of MSR_LASTBRANCH_0_TO_IP.

63H

MSR_LASTBRANCH_3_TO_IP

Unique

Last Branch Record 3 To IP (R/W)

See description of MSR_LASTBRANCH_0_TO_IP.

79H

121

IA32_BIOS_UPDT_TRIG

Unique

BIOS Update Trigger Register (W)

See Table 2-2.

8BH

139

IA32_BIOS_SIGN_ID

Unique

BIOS Update Signature ID (R/W)

See Table 2-2.

A0H

160

MSR_SMRR_PHYSBASE

Unique

System Management Mode Base Address register (WO in

SMM)

Model-specific implementation of SMRR-like interface,

read visible and write only in SMM.

11:0

Reserved

31:12

PhysBase: SMRR physical Base Address.

63:32

Reserved

A1H

161

MSR_SMRR_PHYSMASK

Unique

System Management Mode Physical Address Mask

Model-specific implementation of SMRR-like interface,

read visible and write only in SMM.

10:0

Reserved

Valid: Physical address base and range mask are valid.

31:12

PhysMask: SMRR physical address range mask.

2-70 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

63:32

Reserved

C1H

193

IA32_PMC0

Unique

Performance Counter Register

See Table 2-2.

C2H

194

IA32_PMC1

Unique

Performance Counter Register

See Table 2-2.

CDH

205

MSR_FSB_FREQ

Shared

Scaleable Bus Speed (R/O)

This field indicates the intended scaleable bus clock speed

for processors based on Intel Core microarchitecture.

2:0

•

101B: 100 MHz (FSB 400)

•

001B: 133 MHz (FSB 533)

•

011B: 167 MHz (FSB 667)

•

010B: 200 MHz (FSB 800)

•

000B: 267 MHz (FSB 1067)

•

100B: 333 MHz (FSB 1333)

133.33 MHz should be utilized if performing calculation

with System Bus Speed when encoding is 001B.

166.67 MHz should be utilized if performing calculation

with System Bus Speed when encoding is 011B.

266.67 MHz should be utilized if performing calculation

with System Bus Speed when encoding is 000B.

333.33 MHz should be utilized if performing calculation

with System Bus Speed when encoding is 100B.

63:3

Reserved

CDH

205

MSR_FSB_FREQ

Shared

Scaleable Bus Speed (R/O)

This field indicates the intended scaleable bus clock speed

for processors based on Enhanced Intel Core

microarchitecture.

2:0

•

101B: 100 MHz (FSB 400)

•

001B: 133 MHz (FSB 533)

•

011B: 167 MHz (FSB 667)

•

010B: 200 MHz (FSB 800)

•

000B: 267 MHz (FSB 1067)

•

100B: 333 MHz (FSB 1333)

•

110B: 400 MHz (FSB 1600)

133.33 MHz should be utilized if performing calculation

with System Bus Speed when encoding is 001B.

166.67 MHz should be utilized if performing calculation

with System Bus Speed when encoding is 011B.

266.67 MHz should be utilized if performing calculation

with System Bus Speed when encoding is 110B.

333.33 MHz should be utilized if performing calculation

with System Bus Speed when encoding is 111B.

63:3

Reserved

Vol. 4

2-71

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

E7H

231

IA32_MPERF

Unique

Maximum Performance Frequency Clock Count (R/W)

See Table 2-2.

E8H

232

IA32_APERF

Unique

Actual Performance Frequency Clock Count (R/W)

See Table 2-2.

FEH

254

IA32_MTRRCAP

Unique

See Table 2-2.

Unique

SMRR Capability Using MSR 0A0H and 0A1H (R)

174H

372

IA32_SYSENTER_CS

Unique

See Table 2-2.

175H

373

IA32_SYSENTER_ESP

Unique

See Table 2-2.

176H

374

IA32_SYSENTER_EIP

Unique

See Table 2-2.

179H

377

IA32_MCG_CAP

Unique

See Table 2-2.

17AH

378

IA32_MCG_STATUS

Unique

Global Machine Check Status

RIPV

When set, bit indicates that the instruction addressed by

the instruction pointer pushed on the stack (when the

machine check was generated) can be used to restart the

program. If cleared, the program cannot be reliably

restarted.

EIPV

When set, bit indicates that the instruction addressed by

the instruction pointer pushed on the stack (when the

machine check was generated) is directly associated with

the error.

MCIP

When set, bit indicates that a machine check has been

generated. If a second machine check is detected while

this bit is still set, the processor enters a shutdown state.

Software should write this bit to 0 after processing a

machine check exception.

63:3

Reserved

186H

390

IA32_PERFEVTSEL0

Unique

See Table 2-2.

187H

391

IA32_PERFEVTSEL1

Unique

See Table 2-2.

198H

408

IA32_PERF_STATUS

Shared

See Table 2-2.

198H

408

MSR_PERF_STATUS

Shared

Current performance status. See Section 15.1.1,

“Software Interface For Initiating Performance State

Transitions.”

15:0

Current Performance State Value

30:16

Reserved

XE Operation (R/O).

If set, XE operation is enabled. Default is cleared.

39:32

Reserved

2-72 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

44:40

Maximum Bus Ratio (R/O)

Indicates maximum bus ratio configured for the processor.

Reserved

Non-Integer Bus Ratio (R/O)

Indicates non-integer bus ratio is enabled. Applies

processors based on Enhanced Intel Core

microarchitecture.

63:47

Reserved

199H

409

IA32_PERF_CTL

Unique

See Table 2-2.

19AH

410

IA32_CLOCK_MODULATION

Unique

Clock Modulation (R/W)

See Table 2-2.

IA32_CLOCK_MODULATION MSR was originally named

IA32_THERM_CONTROL MSR.

19BH

411

IA32_THERM_INTERRUPT

Unique

Thermal Interrupt Control (R/W)

See Table 2-2.

19CH

412

IA32_THERM_STATUS

Unique

Thermal Monitor Status (R/W)

See Table 2-2.

19DH

413

MSR_THERM2_CTL

Unique

Thermal Monitor 2 Control

15:0

Reserved

TM_SELECT (R/W)

Mode of automatic thermal monitor:

0 = Thermal Monitor 1 (thermally-initiated on-die

modulation of the stop-clock duty cycle).

1 = Thermal Monitor 2 (thermally-initiated frequency

transitions).

If bit 3 of the IA32_MISC_ENABLE register is cleared,

TM_SELECT has no effect. Neither TM1 nor TM2 are

enabled.

63:16

Reserved

1A0H

416

IA32_MISC_ENABLE

Enable Misc. Processor Features (R/W)

Allows a variety of processor functions to be enabled and

disabled.

Fast-Strings Enable

See Table 2-2.

2:1

Reserved

Unique

Automatic Thermal Control Circuit Enable (R/W)

See Table 2-2.

6:4

Reserved

Shared

Performance Monitoring Available (R)

See Table 2-2.

Vol. 4

2-73

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

Reserved

Hardware Prefetcher Disable (R/W)

When set, disables the hardware prefetcher operation on

streams of data. When clear (default), enables the

prefetch queue.

Disabling of the hardware prefetcher may impact

processor performance.

Shared

FERR# Multiplexing Enable (R/W)

1 = FERR# asserted by the processor to indicate a

pending break event within the processor.

0 = Indicates compatible FERR# signaling behavior.

This bit must be set to 1 to support XAPIC interrupt

model usage.

Shared

Branch Trace Storage Unavailable (R/O)

See Table 2-2.

Shared

Processor Event Based Sampling Unavailable (R/O)

See Table 2-2.

Shared

TM2 Enable (R/W)

When this bit is set (1) and the thermal sensor indicates

that the die temperature is at the pre-determined

threshold, the Thermal Monitor 2 mechanism is engaged.

TM2 will reduce the bus to core ratio and voltage

according to the value last written to MSR_THERM2_CTL

bits 15:0.

When this bit is clear (0, default), the processor does not

change the VID signals or the bus to core ratio when the

processor enters a thermally managed state.

The BIOS must enable this feature if the TM2 feature flag

(CPUID.1:ECX[8]) is set; if the TM2 feature flag is not set,

this feature is not supported and BIOS must not alter the

contents of the TM2 bit location.

The processor is operating out of specification if both this

bit and the TM1 bit are set to 0.

15:14

Reserved

Shared

Enhanced Intel SpeedStep Technology Enable (R/W)

See Table 2-2.

Shared

ENABLE MONITOR FSM (R/W)

See Table 2-2.

2-74 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

Shared

Adjacent Cache Line Prefetch Disable (R/W)

When set to 1, the processor fetches the cache line that

contains data currently required by the processor. When

set to 0, the processor fetches cache lines that comprise a

cache line pair (128 bytes).

Single processor platforms should not set this bit. Server

platforms should set or clear this bit based on platform

performance observed in validation and testing.

BIOS may contain a setup option that controls the setting

of this bit.

Shared

Enhanced Intel SpeedStep Technology Select Lock (R/WO)

When set, this bit causes the following bits to become

read-only:

• Enhanced Intel SpeedStep Technology Select Lock (this

bit).

• Enhanced Intel SpeedStep Technology Enable bit.

The bit must be set before an Enhanced Intel SpeedStep

Technology transition is requested. This bit is cleared on

reset.

Reserved

Shared

Limit CPUID Maxval (R/W)

See Table 2-2.

Shared

xTPR Message Disable (R/W)

See Table 2-2.

33:24

Reserved

Unique

XD Bit Disable (R/W)

When set to 1, the Execute Disable Bit feature (XD Bit) is

disabled and the XD Bit extended feature flag will be

clear (CPUID.80000001H: EDX[20]=0).

When set to a 0 (default), the Execute Disable Bit feature

(if available) allows the OS to enable PAE paging and take

advantage of data only pages.

BIOS must not alter the contents of this bit location if XD

bit is not supported. Writing this bit to 1 when the XD Bit

extended feature flag is set to 0 may generate a #GP

exception.

36:35

Reserved

Vol. 4

2-75

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

Unique

DCU Prefetcher Disable (R/W)

When set to 1, the DCU L1 data cache prefetcher is

disabled. The default value after reset is 0. BIOS may

write ‘1’ to disable this feature.

The DCU prefetcher is an L1 data cache prefetcher. When

the DCU prefetcher detects multiple loads from the same

line done within a time limit, the DCU prefetcher assumes

the next line will be required. The next line is prefetched

in to the L1 data cache from memory or L2.

Shared

IDA Disable (R/W)

When set to 1 on processors that support IDA, the Intel

Dynamic Acceleration feature (IDA) is disabled and the

IDA_Enable feature flag will be cleared (CPUID.06H:

EAX[1]=0).

When set to a 0 on processors that support IDA,

CPUID.06H: EAX[1] reports the processor’s support of IDA

is enabled.

Note: The power-on default value is used by BIOS to

detect hardware support of IDA. If the power-on default

value is 1, IDA is available in the processor. If the power-

on default value is 0, IDA is not available.

Unique

IP Prefetcher Disable (R/W)

When set to 1, the IP prefetcher is disabled. The default

value after reset is 0. BIOS may write ‘1’ to disable this

feature.

The IP prefetcher is an L1 data cache prefetcher. The IP

prefetcher looks for sequential load history to determine

whether to prefetch the next expected data into the L1

cache from memory or L2.

63:40

Reserved

1C9H

457

MSR_LASTBRANCH_TOS

Unique

Last Branch Record Stack TOS (R/W)

Contains an index (bits 0-3) that points to the MSR

containing the most recent branch record.

See MSR_LASTBRANCH_0_FROM_IP (at 40H).

1D9H

473

IA32_DEBUGCTL

Unique

Debug Control (R/W)

See Table 2-2.

1DDH

477

MSR_LER_FROM_LIP

Unique

Last Exception Record From Linear IP (R/W)

Contains a pointer to the last branch instruction that the

processor executed prior to the last exception that was

generated or the last interrupt that was handled.

1DEH

478

MSR_LER_TO_LIP

Unique

Last Exception Record To Linear IP (R/W)

This area contains a pointer to the target of the last

branch instruction that the processor executed prior to

the last exception that was generated or the last

interrupt that was handled.

2-76 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

200H

512

IA32_MTRR_PHYSBASE0

Unique

See Table 2-2.

201H

513

IA32_MTRR_PHYSMASK0

Unique

See Table 2-2.

202H

514

IA32_MTRR_PHYSBASE1

Unique

See Table 2-2.

203H

515

IA32_MTRR_PHYSMASK1

Unique

See Table 2-2.

204H

516

IA32_MTRR_PHYSBASE2

Unique

See Table 2-2.

205H

517

IA32_MTRR_PHYSMASK2

Unique

See Table 2-2.

206H

518

IA32_MTRR_PHYSBASE3

Unique

See Table 2-2.

207H

519

IA32_MTRR_PHYSMASK3

Unique

See Table 2-2.

208H

520

IA32_MTRR_PHYSBASE4

Unique

See Table 2-2.

209H

521

IA32_MTRR_PHYSMASK4

Unique

See Table 2-2.

20AH

522

IA32_MTRR_PHYSBASE5

Unique

See Table 2-2.

20BH

523

IA32_MTRR_PHYSMASK5

Unique

See Table 2-2.

20CH

524

IA32_MTRR_PHYSBASE6

Unique

See Table 2-2.

20DH

525

IA32_MTRR_PHYSMASK6

Unique

See Table 2-2.

20EH

526

IA32_MTRR_PHYSBASE7

Unique

See Table 2-2.

20FH

527

IA32_MTRR_PHYSMASK7

Unique

See Table 2-2.

250H

592

IA32_MTRR_FIX64K_00000

Unique

See Table 2-2.

258H

600

IA32_MTRR_FIX16K_80000

Unique

See Table 2-2.

259H

601

IA32_MTRR_FIX16K_A0000

Unique

See Table 2-2.

268H

616

IA32_MTRR_FIX4K_C0000

Unique

See Table 2-2.

269H

617

IA32_MTRR_FIX4K_C8000

Unique

See Table 2-2.

26AH

618

IA32_MTRR_FIX4K_D0000

Unique

See Table 2-2.

26BH

619

IA32_MTRR_FIX4K_D8000

Unique

See Table 2-2.

26CH

620

IA32_MTRR_FIX4K_E0000

Unique

See Table 2-2.

26DH

621

IA32_MTRR_FIX4K_E8000

Unique

See Table 2-2.

26EH

622

IA32_MTRR_FIX4K_F0000

Unique

See Table 2-2.

26FH

623

IA32_MTRR_FIX4K_F8000

Unique

See Table 2-2.

277H

631

IA32_PAT

Unique

See Table 2-2.

2FFH

767

IA32_MTRR_DEF_TYPE

Unique

Default Memory Types (R/W)

See Table 2-2.

309H

777

IA32_FIXED_CTR0

Unique

Fixed-Function Performance Counter Register 0 (R/W)

See Table 2-2.

30AH

778

IA32_FIXED_CTR1

Unique

Fixed-Function Performance Counter Register 1 (R/W)

See Table 2-2.

Vol. 4

2-77

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

30BH

779

IA32_FIXED_CTR2

Unique

Fixed-Function Performance Counter Register 2 (R/W)

See Table 2-2.

345H

837

IA32_PERF_CAPABILITIES

Unique

See Table 2-2. See Section 18.4.1, “IA32_DEBUGCTL

MSR.”

345H

837

MSR_PERF_CAPABILITIES

Unique

R/O. This applies to processors that do not support

architectural perfmon version 2.

5:0

LBR Format. See Table 2-2.

PEBS Record Format

PEBSSaveArchRegs. See Table 2-2.

63:8

Reserved

38DH

909

IA32_FIXED_CTR_CTRL

Unique

Fixed-Function-Counter Control Register (R/W)

See Table 2-2.

38EH

910

IA32_PERF_GLOBAL_STATUS

Unique

See Table 2-2. See Section 20.6.2.2, “Global Counter

Control Facilities.”

38EH

910

MSR_PERF_GLOBAL_STATUS

Unique

See Section 20.6.2.2, “Global Counter Control Facilities.”

38FH

911

IA32_PERF_GLOBAL_CTRL

Unique

See Table 2-2. See Section 20.6.2.2, “Global Counter

Control Facilities.”

38FH

911

MSR_PERF_GLOBAL_CTRL

Unique

See Section 20.6.2.2, “Global Counter Control Facilities.”

390H

912

IA32_PERF_GLOBAL_OVF_CTRL

Unique

See Table 2-2. See Section 20.6.2.2, “Global Counter

Control Facilities.”

390H

912

MSR_PERF_GLOBAL_OVF_CTRL

Unique

See Section 20.6.2.2, “Global Counter Control Facilities.”

3F1H

1009

IA32_PEBS_ENABLE

Unique

See Table 2-2. See Section 20.6.2.4, “Processor Event

Based Sampling (PEBS).”

(MSR_PEBS_ENABLE)

Enable PEBS on IA32_PMC0. (R/W)

400H

1024

IA32_MC0_CTL

Unique

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

401H

1025

IA32_MC0_STATUS

Unique

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

402H

1026

IA32_MC0_ADDR

Unique

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The IA32_MC0_ADDR register is either not implemented

or contains no address if the ADDRV flag in the

IA32_MC0_STATUS register is clear.

When not implemented in the processor, all reads and

writes to this MSR will cause a general-protection

exception.

404H

1028

IA32_MC1_CTL

Unique

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

405H

1029

IA32_MC1_STATUS

Unique

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

2-78 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

406H

1030

IA32_MC1_ADDR

Unique

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The IA32_MC1_ADDR register is either not implemented

or contains no address if the ADDRV flag in the

IA32_MC1_STATUS register is clear.

When not implemented in the processor, all reads and

writes to this MSR will cause a general-protection

exception.

408H

1032

IA32_MC2_CTL

Unique

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

409H

1033

IA32_MC2_STATUS

Unique

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

40AH

1034

IA32_MC2_ADDR

Unique

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The IA32_MC2_ADDR register is either not implemented

or contains no address if the ADDRV flag in the

IA32_MC2_STATUS register is clear.

When not implemented in the processor, all reads and

writes to this MSR will cause a general-protection

exception.

40CH

1036

IA32_MC4_CTL

Unique

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

40DH

1037

IA32_MC4_STATUS

Unique

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

40EH

1038

IA32_MC4_ADDR

Unique

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The MSR_MC4_ADDR register is either not implemented

or contains no address if the ADDRV flag in the

MSR_MC4_STATUS register is clear.

When not implemented in the processor, all reads and

writes to this MSR will cause a general-protection

exception.

410H

1040

IA32_MC3_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

411H

1041

IA32_MC3_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

412H

1042

IA32_MC3_ADDR

Unique

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The MSR_MC3_ADDR register is either not implemented

or contains no address if the ADDRV flag in the

MSR_MC3_STATUS register is clear.

When not implemented in the processor, all reads and

writes to this MSR will cause a general-protection

exception.

413H

1043

IA32_MC3_MISC

Unique

Machine Check Error Reporting Register: Contains

additional information describing the machine-check error

if the MISCV flag in the IA32_MCi_STATUS register is set.

414H

1044

IA32_MC5_CTL

Unique

Machine Check Error Reporting Register: Controls

signaling of #MC for errors produced by a particular

hardware unit (or group of hardware units).

Vol. 4

2-79

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

415H

1045

IA32_MC5_STATUS

Unique

Machine Check Error Reporting Register: Contains

information related to a machine-check error if its VAL

(valid) flag is set. Software is responsible for clearing

IA32_MCi_STATUS MSRs by explicitly writing 0s to them;

writing 1s to them causes a general-protection exception.

416H

1046

IA32_MC5_ADDR

Unique

Machine Check Error Reporting Register: Contains the

address of the code or data memory location that

produced the machine-check error if the ADDRV flag in

the IA32_MCi_STATUS register is set.

417H

1047

IA32_MC5_MISC

Unique

Machine Check Error Reporting Register: Contains

additional information describing the machine-check error

if the MISCV flag in the IA32_MCi_STATUS register is set.

419H

1045

IA32_MC6_STATUS

Unique

Applies to Intel Xeon processor 7400 series (processor

signature 06_1D) only. See Section 16.3.2.2,

“IA32_MCi_STATUS MSRS,” and Chapter 24.

480H

1152

IA32_VMX_BASIC

Unique

Reporting Register of Basic VMX Capabilities (R/O)

See Table 2-2.

See Appendix A.1, “Basic VMX Information.”

481H

1153

IA32_VMX_PINBASED_CTLS

Unique

Capability Reporting Register of Pin-Based VM-Execution

Controls (R/O)

See Table 2-2.

See Appendix A.3, “VM-Execution Controls.”

482H

1154

IA32_VMX_PROCBASED_CTLS

Unique

Capability Reporting Register of Primary Processor-Based

VM-Execution Controls (R/O)

See Appendix A.3, “VM-Execution Controls.”

483H

1155

IA32_VMX_EXIT_CTLS

Unique

Capability Reporting Register of VM-Exit Controls (R/O)

See Table 2-2.

See Appendix A.4, “VM-Exit Controls.”

484H

1156

IA32_VMX_ENTRY_CTLS

Unique

Capability Reporting Register of VM-Entry Controls (R/O)

See Table 2-2.

See Appendix A.5, “VM-Entry Controls.”

485H

1157

IA32_VMX_MISC

Unique

Reporting Register of Miscellaneous VMX Capabilities

(R/O)

See Table 2-2.

See Appendix A.6, “Miscellaneous Data.”

486H

1158

IA32_VMX_CR0_FIXED0

Unique

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)

See Table 2-2.

See Appendix A.7, “VMX-Fixed Bits in CR0.”

487H

1159

IA32_VMX_CR0_FIXED1

Unique

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)

See Table 2-2.

See Appendix A.7, “VMX-Fixed Bits in CR0.”

2-80 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

488H

1160

IA32_VMX_CR4_FIXED0

Unique

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)

See Table 2-2.

See Appendix A.8, “VMX-Fixed Bits in CR4.”

489H

1161

IA32_VMX_CR4_FIXED1

Unique

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)

See Table 2-2.

See Appendix A.8, “VMX-Fixed Bits in CR4.”

48AH

1162

IA32_VMX_VMCS_ENUM

Unique

Capability Reporting Register of VMCS Field Enumeration

(R/O)

See Table 2-2.

See Appendix A.9, “VMCS Enumeration.”

48BH

1163

IA32_VMX_PROCBASED_CTLS2

Unique

Capability Reporting Register of Secondary Processor-

Based VM-Execution Controls (R/O)

See Appendix A.3, “VM-Execution Controls.”

600H

1536

IA32_DS_AREA

Unique

DS Save Area (R/W)

See Table 2-2.

See Section 20.6.3.4, “Debug Store (DS) Mechanism.”

107CC

67532

MSR_EMON_L3_CTR_CTL0

Unique

GBUSQ Event Control/Counter Register (R/W)

Applies to Intel Xeon processor 7400 series (processor

signature 06_1D) only. See Section 18.2.2.

107CD

67533

MSR_EMON_L3_CTR_CTL1

Unique

GBUSQ Event Control/Counter Register (R/W)

Applies to Intel Xeon processor 7400 series (processor

signature 06_1D) only. See Section 18.2.2.

107CE

67534

MSR_EMON_L3_CTR_CTL2

Unique

GSNPQ Event Control/Counter Register (R/W)

Applies to Intel Xeon processor 7400 series (processor

signature 06_1D) only. See Section 18.2.2.

107CF

67535

MSR_EMON_L3_CTR_CTL3

Unique

GSNPQ Event Control/Counter Register (R/W)

Applies to Intel Xeon processor 7400 series (processor

signature 06_1D) only. See Section 18.2.2.

107D0

67536

MSR_EMON_L3_CTR_CTL4

Unique

FSB Event Control/Counter Register (R/W)

Applies to Intel Xeon processor 7400 series (processor

signature 06_1D) only. See Section 18.2.2.

107D1

67537

MSR_EMON_L3_CTR_CTL5

Unique

FSB Event Control/Counter Register (R/W)

Applies to Intel Xeon processor 7400 series (processor

signature 06_1D) only. See Section 18.2.2.

107D2

67538

MSR_EMON_L3_CTR_CTL6

Unique

FSB Event Control/Counter Register (R/W)

Applies to Intel Xeon processor 7400 series (processor

signature 06_1D) only. See Section 18.2.2.

107D3

67539

MSR_EMON_L3_CTR_CTL7

Unique

FSB Event Control/Counter Register (R/W)

Applies to Intel Xeon processor 7400 series (processor

signature 06_1D) only. See Section 18.2.2.

Vol. 4

2-81

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

107D8

67544

MSR_EMON_L3_GL_CTL

Unique

L3/FSB Common Control Register (R/W)

Applies to Intel Xeon processor 7400 series (processor

signature 06_1D) only. See Section 18.2.2.

C000_

IA32_EFER

Unique

Extended Feature Enables

0080H

See Table 2-2.

C000_

IA32_STAR

Unique

System Call Target Address (R/W)

0081H

See Table 2-2.

C000_

IA32_LSTAR

Unique

IA-32e Mode System Call Target Address (R/W)

0082H

See Table 2-2.

C000_

IA32_FMASK

Unique

System Call Flag Mask (R/W)

0084H

See Table 2-2.

C000_

IA32_FS_BASE

Unique

Map of BASE Address of FS (R/W)

0100H

See Table 2-2.

C000_

IA32_GS_BASE

Unique

Map of BASE Address of GS (R/W)

0101H

See Table 2-2.

C000_

IA32_KERNEL_GS_BASE

Unique

Swap Target of BASE Address of GS (R/W)

0102H

See Table 2-2.

2.3

MSRS IN THE 45 NM AND 32 NM INTEL ATOM® PROCESSOR FAMILY

Table 2-4 lists model-specific registers (MSRs) for 45 nm and 32 nm Intel Atom processors, architectural MSR

addresses are also included in Table 2-4. These processors have a CPUID Signature DisplayFamily_DisplayModel

value of 06_1CH, 06_26H, 06_27H, 06_35H, or 06_36H; see Table 2-1.

The column “Shared/Unique” applies to logical processors sharing the same core in processors based on the Intel

Atom microarchitecture. “Unique” means each logical processor has a separate MSR, or a bit field in an MSR

governs only a logical processor. “Shared” means the MSR or the bit field in an MSR address governs the operation

of both logical processors in the same core.

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family

Shared/

Address

Unique

Bit Description

Hex

Dec

IA32_P5_MC_ADDR

Shared

See Section 2.23, “MSRs in Pentium Processors.”

IA32_P5_MC_TYPE

Shared

See Section 2.23, “MSRs in Pentium Processors.”

IA32_MONITOR_FILTER_

Unique

See Section 9.10.5, “Monitor/Mwait Address Range

SIZE

Determination,” and Table 2-2.

10H

IA32_TIME_STAMP_

Unique

See Section 18.17, “Time-Stamp Counter,” and see

COUNTER

Table 2-2.

17H

IA32_PLATFORM_ID

Shared

Platform ID (R)

See Table 2-2.

2-82 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

17H

MSR_PLATFORM_ID

Shared

Model Specific Platform ID (R)

7:0

Reserved

12:8

Maximum Qualified Ratio (R)

The maximum allowed bus ratio.

63:13

Reserved

1BH

IA32_APIC_BASE

Unique

See Section 11.4.4, “Local APIC Status and Location,” and

Table 2-2.

2AH

MSR_EBL_CR_POWERON

Shared

Processor Hard Power-On Configuration (R/W)

Enables and disables processor features; (R) indicates

current processor configuration.

Reserved

Data Error Checking Enable (R/W)

1 = Enabled; 0 = Disabled

Always 0.

Response Error Checking Enable (R/W)

1 = Enabled; 0 = Disabled

Always 0.

AERR# Drive Enable (R/W)

1 = Enabled; 0 = Disabled

Always 0.

BERR# Enable for initiator bus requests (R/W)

1 = Enabled; 0 = Disabled

Always 0.

Reserved

BINIT# Driver Enable (R/W)

1 = Enabled; 0 = Disabled

Always 0.

Reserved

Execute BIST (R/O)

1 = Enabled; 0 = Disabled

AERR# Observation Enabled (R/O)

1 = Enabled; 0 = Disabled

Always 0.

Reserved

BINIT# Observation Enabled (R/O)

1 = Enabled; 0 = Disabled

Always 0.

Reserved

Vol. 4

2-83

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

1 MByte Power on Reset Vector (R/O)

1 = 1 MByte; 0 = 4 GBytes

Reserved

17:16

APIC Cluster ID (R/O)

Always 00B.

19: 18

Reserved

21: 20

Symmetric Arbitration ID (R/O)

Always 00B.

26:22

Integer Bus Frequency Ratio (R/O)

3AH

IA32_FEATURE_CONTROL

Unique

Control Features in Intel 64Processor (R/W)

See Table 2-2.

40H

MSR_LASTBRANCH_0_FROM_IP

Unique

Last Branch Record 0 From IP (R/W)

One of eight pairs of last branch record registers on the

last branch record stack. The From_IP part of the stack

contains pointers to the source instruction. See also:

• Last Branch Record Stack TOS at 1C9H.

• Section 18.5.

41H

MSR_LASTBRANCH_1_FROM_IP

Unique

Last Branch Record 1 From IP (R/W)

See description of MSR_LASTBRANCH_0_FROM_IP.

42H

MSR_LASTBRANCH_2_FROM_IP

Unique

Last Branch Record 2 From IP (R/W)

See description of MSR_LASTBRANCH_0_FROM_IP.

43H

MSR_LASTBRANCH_3_FROM_IP

Unique

Last Branch Record 3 From IP (R/W)

See description of MSR_LASTBRANCH_0_FROM_IP.

44H

MSR_LASTBRANCH_4_FROM_IP

Unique

Last Branch Record 4 From IP (R/W)

See description of MSR_LASTBRANCH_0_FROM_IP.

45H

MSR_LASTBRANCH_5_FROM_IP

Unique

Last Branch Record 5 From IP (R/W)

See description of MSR_LASTBRANCH_0_FROM_IP.

46H

MSR_LASTBRANCH_6_FROM_IP

Unique

Last Branch Record 6 From IP (R/W)

See description of MSR_LASTBRANCH_0_FROM_IP.

47H

MSR_LASTBRANCH_7_FROM_IP

Unique

Last Branch Record 7 From IP (R/W)

See description of MSR_LASTBRANCH_0_FROM_IP.

60H

MSR_LASTBRANCH_0_TO_IP

Unique

Last Branch Record 0 To IP (R/W)

One of eight pairs of last branch record registers on the

last branch record stack. The To_IP part of the stack

contains pointers to the destination instruction.

61H

MSR_LASTBRANCH_1_TO_IP

Unique

Last Branch Record 1 To IP (R/W)

See description of MSR_LASTBRANCH_0_TO_IP.

62H

MSR_LASTBRANCH_2_TO_IP

Unique

Last Branch Record 2 To IP (R/W)

See description of MSR_LASTBRANCH_0_TO_IP.

63H

MSR_LASTBRANCH_3_TO_IP

Unique

Last Branch Record 3 To IP (R/W)

See description of MSR_LASTBRANCH_0_TO_IP.

2-84 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

64H

100

MSR_LASTBRANCH_4_TO_IP

Unique

Last Branch Record 4 To IP (R/W)

See description of MSR_LASTBRANCH_0_TO_IP.

65H

101

MSR_LASTBRANCH_5_TO_IP

Unique

Last Branch Record 5 To IP (R/W)

See description of MSR_LASTBRANCH_0_TO_IP.

66H

102

MSR_LASTBRANCH_6_TO_IP

Unique

Last Branch Record 6 To IP (R/W)

See description of MSR_LASTBRANCH_0_TO_IP.

67H

103

MSR_LASTBRANCH_7_TO_IP

Unique

Last Branch Record 7 To IP (R/W)

See description of MSR_LASTBRANCH_0_TO_IP.

79H

121

IA32_BIOS_UPDT_TRIG

Shared

BIOS Update Trigger Register (W)

See Table 2-2.

8BH

139

IA32_BIOS_SIGN_ID

Unique

BIOS Update Signature ID (R/W)

See Table 2-2.

C1H

193

IA32_PMC0

Unique

Performance counter register

See Table 2-2.

C2H

194

IA32_PMC1

Unique

Performance Counter Register

See Table 2-2.

CDH

205

MSR_FSB_FREQ

Shared

Scaleable Bus Speed (R/O)

This field indicates the intended scalable bus clock speed

for processors based on Intel Atom microarchitecture.

2:0

•

111B: 083 MHz (FSB 333)

•

101B: 100 MHz (FSB 400)

•

001B: 133 MHz (FSB 533)

•

011B: 167 MHz (FSB 667)

133.33 MHz should be utilized if performing calculation

with System Bus Speed when encoding is 001B.

166.67 MHz should be utilized if performing calculation

with System Bus Speed when encoding is 011B.

63:3

Reserved

E7H

231

IA32_MPERF

Unique

Maximum Performance Frequency Clock Count (R/W)

See Table 2-2.

E8H

232

IA32_APERF

Unique

Actual Performance Frequency Clock Count (R/W)

See Table 2-2.

FEH

254

IA32_MTRRCAP

Shared

Memory Type Range Register (R)

See Table 2-2.

11EH

281

MSR_BBL_CR_CTL3

Shared

Control Register 3

Used to configure the L2 Cache.

L2 Hardware Enabled (R/O)

1 = Indicates the L2 is hardware-enabled.

0 = Indicates the L2 is hardware-disabled.

7:1

Reserved

Vol. 4

2-85

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

L2 Enabled (R/W)

1 = L2 cache has been initialized.

0 = Disabled (default).

Until this bit is set, the processor will not respond to the

WBINVD instruction or the assertion of the FLUSH# input.

22:9

Reserved

L2 Not Present (R/O)

0 = L2 Present

1 = L2 Not Present

63:24

Reserved

174H

372

IA32_SYSENTER_CS

Unique

See Table 2-2.

175H

373

IA32_SYSENTER_ESP

Unique

See Table 2-2.

176H

374

IA32_SYSENTER_EIP

Unique

See Table 2-2.

179H

377

IA32_MCG_CAP

Unique

See Table 2-2.

17AH

378

IA32_MCG_STATUS

Unique

Global Machine Check Status

RIPV

When set, bit indicates that the instruction addressed by

the instruction pointer pushed on the stack (when the

machine check was generated) can be used to restart the

program. If cleared, the program cannot be reliably

restarted.

EIPV

When set, bit indicates that the instruction addressed by

the instruction pointer pushed on the stack (when the

machine check was generated) is directly associated with

the error.

MCIP

When set, bit indicates that a machine check has been

generated. If a second machine check is detected while

this bit is still set, the processor enters a shutdown state.

Software should write this bit to 0 after processing a

machine check exception.

63:3

Reserved

186H

390

IA32_PERFEVTSEL0

Unique

See Table 2-2.

187H

391

IA32_PERFEVTSEL1

Unique

See Table 2-2.

198H

408

IA32_PERF_STATUS

Shared

See Table 2-2.

198H

408

MSR_PERF_STATUS

Shared

Performance Status

15:0

Current Performance State Value

39:16

Reserved

44:40

Maximum Bus Ratio (R/O)

Indicates maximum bus ratio configured for the processor.

63:45

Reserved

2-86 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

199H

409

IA32_PERF_CTL

Unique

See Table 2-2.

19AH

410

IA32_CLOCK_MODULATION

Unique

Clock Modulation (R/W)

See Table 2-2.

IA32_CLOCK_MODULATION MSR was originally named

IA32_THERM_CONTROL MSR.

19BH

411

IA32_THERM_INTERRUPT

Unique

Thermal Interrupt Control (R/W)

See Table 2-2.

19CH

412

IA32_THERM_STATUS

Unique

Thermal Monitor Status (R/W)

See Table 2-2.

19DH

413

MSR_THERM2_CTL

Shared

Thermal Monitor 2 Control

15:0

Reserved

TM_SELECT (R/W)

Mode of automatic thermal monitor:

0 = Thermal Monitor 1 (thermally-initiated on-die

modulation of the stop-clock duty cycle).

1 = Thermal Monitor 2 (thermally-initiated frequency

transitions).

If bit 3 of the IA32_MISC_ENABLE register is cleared,

TM_SELECT has no effect. Neither TM1 nor TM2 are

enabled.

63:17

Reserved

1A0H

416

IA32_MISC_ENABLE

Unique

Enable Misc. Processor Features (R/W)

Allows a variety of processor functions to be enabled and

disabled.

Fast-Strings Enable

See Table 2-2.

2:1

Reserved

Unique

Automatic Thermal Control Circuit Enable (R/W)

See Table 2-2. Default value is 0.

6:4

Reserved

Shared

Performance Monitoring Available (R)

See Table 2-2.

Reserved

Shared

FERR# Multiplexing Enable (R/W)

1 = FERR# asserted by the processor to indicate a

pending break event within the processor.

0 = Indicates compatible FERR# signaling behavior.

This bit must be set to 1 to support XAPIC interrupt model

usage.

Shared

Branch Trace Storage Unavailable (R/O)

See Table 2-2.

Vol. 4

2-87

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

Shared

Processor Event Based Sampling Unavailable (R/O)

See Table 2-2.

Shared

TM2 Enable (R/W)

When this bit is set (1) and the thermal sensor indicates

that the die temperature is at the pre-determined

threshold, the Thermal Monitor 2 mechanism is engaged.

TM2 will reduce the bus to core ratio and voltage according

to the value last written to MSR_THERM2_CTL bits 15:0.

When this bit is cleared (0, default), the processor does not

change the VID signals or the bus to core ratio when the

processor enters a thermally managed state.

The BIOS must enable this feature if the TM2 feature flag

(CPUID.1:ECX[8]) is set; if the TM2 feature flag is not set,

this feature is not supported and BIOS must not alter the

contents of the TM2 bit location.

The processor is operating out of specification if both this

bit and the TM1 bit are set to 0.

15:14

Reserved

Shared

Enhanced Intel SpeedStep Technology Enable (R/W)

See Table 2-2.

Shared

ENABLE MONITOR FSM (R/W)

See Table 2-2.

Reserved

Shared

Enhanced Intel SpeedStep Technology Select Lock (R/WO)

When set, this bit causes the following bits to become

read-only:

• Enhanced Intel SpeedStep Technology Select Lock (this

bit).

• Enhanced Intel SpeedStep Technology Enable bit.

The bit must be set before an Enhanced Intel SpeedStep

Technology transition is requested. This bit is cleared on

reset.

Reserved

Unique

Limit CPUID Maxval (R/W)

See Table 2-2.

Shared

xTPR Message Disable (R/W)

See Table 2-2.

33:24

Reserved

Unique

XD Bit Disable (R/W)

See Table 2-3.

63:35

Reserved

2-88 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

1C9H

457

MSR_LASTBRANCH_TOS

Unique

Last Branch Record Stack TOS (R/W)

Contains an index (bits 0-2) that points to the MSR

containing the most recent branch record.

See MSR_LASTBRANCH_0_FROM_IP (at 40H).

1D9H

473

IA32_DEBUGCTL

Unique

Debug Control (R/W)

See Table 2-2.

1DDH

477

MSR_LER_FROM_LIP

Unique

Last Exception Record From Linear IP (R)

Contains a pointer to the last branch instruction that the

processor executed prior to the last exception that was

generated or the last interrupt that was handled.

1DEH

478

MSR_LER_TO_LIP

Unique

Last Exception Record To Linear IP (R)

This area contains a pointer to the target of the last

branch instruction that the processor executed prior to

the last exception that was generated or the last interrupt

that was handled.

200H

512

IA32_MTRR_PHYSBASE0

Shared

See Table 2-2.

201H

513

IA32_MTRR_PHYSMASK0

Shared

See Table 2-2.

202H

514

IA32_MTRR_PHYSBASE1

Shared

See Table 2-2.

203H

515

IA32_MTRR_PHYSMASK1

Shared

See Table 2-2.

204H

516

IA32_MTRR_PHYSBASE2

Shared

See Table 2-2.

205H

517

IA32_MTRR_PHYSMASK2

Shared

See Table 2-2.

206H

518

IA32_MTRR_PHYSBASE3

Shared

See Table 2-2.

207H

519

IA32_MTRR_PHYSMASK3

Shared

See Table 2-2.

208H

520

IA32_MTRR_PHYSBASE4

Shared

See Table 2-2.

209H

521

IA32_MTRR_PHYSMASK4

Shared

See Table 2-2.

20AH

522

IA32_MTRR_PHYSBASE5

Shared

See Table 2-2.

20BH

523

IA32_MTRR_PHYSMASK5

Shared

See Table 2-2.

20CH

524

IA32_MTRR_PHYSBASE6

Shared

See Table 2-2.

20DH

525

IA32_MTRR_PHYSMASK6

Shared

See Table 2-2.

20EH

526

IA32_MTRR_PHYSBASE7

Shared

See Table 2-2.

20FH

527

IA32_MTRR_PHYSMASK7

Shared

See Table 2-2.

250H

592

IA32_MTRR_FIX64K_00000

Shared

See Table 2-2.

258H

600

IA32_MTRR_FIX16K_80000

Shared

See Table 2-2.

259H

601

IA32_MTRR_FIX16K_A0000

Shared

See Table 2-2.

268H

616

IA32_MTRR_FIX4K_C0000

Shared

See Table 2-2.

269H

617

IA32_MTRR_FIX4K_C8000

Shared

See Table 2-2.

26AH

618

IA32_MTRR_FIX4K_D0000

Shared

See Table 2-2.

26BH

619

IA32_MTRR_FIX4K_D8000

Shared

See Table 2-2.

26CH

620

IA32_MTRR_FIX4K_E0000

Shared

See Table 2-2.

Vol. 4

2-89

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

26DH

621

IA32_MTRR_FIX4K_E8000

Shared

See Table 2-2.

26EH

622

IA32_MTRR_FIX4K_F0000

Shared

See Table 2-2.

26FH

623

IA32_MTRR_FIX4K_F8000

Shared

See Table 2-2.

277H

631

IA32_PAT

Unique

See Table 2-2.

309H

777

IA32_FIXED_CTR0

Unique

Fixed-Function Performance Counter Register 0 (R/W)

See Table 2-2.

30AH

778

IA32_FIXED_CTR1

Unique

Fixed-Function Performance Counter Register 1 (R/W)

See Table 2-2.

30BH

779

IA32_FIXED_CTR2

Unique

Fixed-Function Performance Counter Register 2 (R/W)

See Table 2-2.

345H

837

IA32_PERF_CAPABILITIES

Shared

See Table 2-2. See Section 18.4.1, “IA32_DEBUGCTL MSR.”

38DH

909

IA32_FIXED_CTR_CTRL

Unique

Fixed-Function-Counter Control Register (R/W)

See Table 2-2.

38EH

910

IA32_PERF_GLOBAL_STATUS

Unique

See Table 2-2. See Section 20.6.2.2, “Global Counter

Control Facilities.”

38FH

911

IA32_PERF_GLOBAL_CTRL

Unique

See Table 2-2. See Section 20.6.2.2, “Global Counter

Control Facilities.”

390H

912

IA32_PERF_GLOBAL_OVF_CTRL

Unique

See Table 2-2. See Section 20.6.2.2, “Global Counter

Control Facilities.”

3F1H

1009

IA32_PEBS_ENABLE

Unique

See Table 2-2. See Section 20.6.2.4, “Processor Event

Based Sampling (PEBS).”

(MSR_PEBS_ENABLE)

Enable PEBS on IA32_PMC0 (R/W)

400H

1024

IA32_MC0_CTL

Shared

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

401H

1025

IA32_MC0_STATUS

Shared

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

402H

1026

IA32_MC0_ADDR

Shared

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The IA32_MC0_ADDR register is either not implemented

or contains no address if the ADDRV flag in the

IA32_MC0_STATUS register is clear.

When not implemented in the processor, all reads and

writes to this MSR will cause a general-protection

exception.

404H

1028

IA32_MC1_CTL

Shared

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

405H

1029

IA32_MC1_STATUS

Shared

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

408H

1032

IA32_MC2_CTL

Shared

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

409H

1033

IA32_MC2_STATUS

Shared

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

2-90 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

40AH

1034

IA32_MC2_ADDR

Shared

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The IA32_MC2_ADDR register is either not implemented

or contains no address if the ADDRV flag in the

IA32_MC2_STATUS register is clear.

When not implemented in the processor, all reads and

writes to this MSR will cause a general-protection

exception.

40CH

1036

IA32_MC3_CTL

Shared

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

40DH

1037

IA32_MC3_STATUS

Shared

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

40EH

1038

IA32_MC3_ADDR

Shared

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The MSR_MC3_ADDR register is either not implemented or

contains no address if the ADDRV flag in the

MSR_MC3_STATUS register is clear.

When not implemented in the processor, all reads and

writes to this MSR will cause a general-protection

exception.

410H

1040

IA32_MC4_CTL

Shared

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

411H

1041

IA32_MC4_STATUS

Shared

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

412H

1042

IA32_MC4_ADDR

Shared

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The MSR_MC4_ADDR register is either not implemented or

contains no address if the ADDRV flag in the

MSR_MC4_STATUS register is clear.

When not implemented in the processor, all reads and

writes to this MSR will cause a general-protection

exception.

480H

1152

IA32_VMX_BASIC

Unique

Reporting Register of Basic VMX Capabilities (R/O)

See Table 2-2.

See Appendix A.1, “Basic VMX Information.”

481H

1153

IA32_VMX_PINBASED_CTLS

Unique

Capability Reporting Register of Pin-Based VM-Execution

Controls (R/O)

See Table 2-2.

See Appendix A.3, “VM-Execution Controls.”

482H

1154

IA32_VMX_PROCBASED_CTLS

Unique

Capability Reporting Register of Primary Processor-Based

VM-Execution Controls (R/O)

See Appendix A.3, “VM-Execution Controls.”

483H

1155

IA32_VMX_EXIT_CTLS

Unique

Capability Reporting Register of VM-Exit Controls (R/O)

See Table 2-2.

See Appendix A.4, “VM-Exit Controls.”

484H

1156

IA32_VMX_ENTRY_CTLS

Unique

Capability Reporting Register of VM-Entry Controls (R/O)

See Table 2-2.

See Appendix A.5, “VM-Entry Controls.”

Vol. 4

2-91

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)

Shared/

Address

Unique

Bit Description

Hex

Dec

485H

1157

IA32_VMX_MISC

Unique

Reporting Register of Miscellaneous VMX Capabilities

(R/O)

See Table 2-2.

See Appendix A.6, “Miscellaneous Data.”

486H

1158

IA32_VMX_CR0_FIXED0

Unique

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)

See Table 2-2.

See Appendix A.7, “VMX-Fixed Bits in CR0.”

487H

1159

IA32_VMX_CR0_FIXED1

Unique

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)

See Table 2-2.

See Appendix A.7, “VMX-Fixed Bits in CR0.”

488H

1160

IA32_VMX_CR4_FIXED0

Unique

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)

See Table 2-2.

See Appendix A.8, “VMX-Fixed Bits in CR4.”

489H

1161

IA32_VMX_CR4_FIXED1

Unique

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)

See Table 2-2.

See Appendix A.8, “VMX-Fixed Bits in CR4.”

48AH

1162

IA32_VMX_VMCS_ENUM

Unique

Capability Reporting Register of VMCS Field Enumeration

(R/O)

See Table 2-2.

See Appendix A.9, “VMCS Enumeration.”

48BH

1163

IA32_VMX_PROCBASED_CTLS2

Unique

Capability Reporting Register of Secondary Processor-

Based VM-Execution Controls (R/O)

See Appendix A.3, “VM-Execution Controls.”

600H

1536

IA32_DS_AREA

Unique

DS Save Area (R/W)

See Table 2-2.

See Section 20.6.3.4, “Debug Store (DS) Mechanism.”

C000_

IA32_EFER

Unique

Extended Feature Enables

0080H

See Table 2-2.

C000_

IA32_STAR

Unique

System Call Target Address (R/W)

0081H

See Table 2-2.

C000_

IA32_LSTAR

Unique

IA-32e Mode System Call Target Address (R/W)

0082H

See Table 2-2.

C000_

IA32_FMASK

Unique

System Call Flag Mask (R/W)

0084H

See Table 2-2.

C000_

IA32_FS_BASE

Unique

Map of BASE Address of FS (R/W)

0100H

See Table 2-2.

C000_

IA32_GS_BASE

Unique

Map of BASE Address of GS (R/W)

0101H

See Table 2-2.

C000_

IA32_KERNEL_GS_BASE

Unique

Swap Target of BASE Address of GS (R/W)

0102H

See Table 2-2.

2-92 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-5 lists model-specific registers (MSRs) that are specific to Intel Atom^® processor with a CPUID Signature

DisplayFamily_DisplayModel value of 06_27H.

Table 2-5. MSRs Supported by Intel Atom® Processors with a CPUID Signature DisplayFamily_DisplayModel

Value of 06_27H

Address

Scope

Bit Description

Hex

Dec

3F8H

1016

MSR_PKG_C2_RESIDENCY

Package

Package C2 Residency

Note: C-state values are processor specific C-state code

names, unrelated to MWAIT extension C-state parameters

or ACPI C-States.

63:0

Package

Package C2 Residency Counter (R/O)

Time that this package is in processor-specific C2 states

since last reset. Counts at 1 Mhz frequency.

3F9H

1017

MSR_PKG_C4_RESIDENCY

Package

Package C4 Residency

Note: C-state values are processor specific C-state code

names, unrelated to MWAIT extension C-state parameters

or ACPI C-States.

63:0

Package

Package C4 Residency Counter. (R/O)

Time that this package is in processor-specific C4 states

since last reset. Counts at 1 Mhz frequency.

3FAH

1018

MSR_PKG_C6_RESIDENCY

Package

Package C6 Residency

Note: C-state values are processor specific C-state code

names, unrelated to MWAIT extension C-state parameters

or ACPI C-States.

63:0

Package

Package C6 Residency Counter. (R/O)

Time that this package is in processor-specific C6 states

since last reset. Counts at 1 Mhz frequency.

2.4

MSRS IN INTEL PROCESSORS BASED ON SILVERMONT

MICROARCHITECTURE

Table 2-6 lists model-specific registers (MSRs) common to Intel processors based on the Silvermont microarchitec-

ture. These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_37H, 06_4AH, 06_4DH,

06_5AH, or 06_5DH; see Table 2-1. The MSRs listed in Table 2-6 are also common to processors based on the

Airmont microarchitecture and newer microarchitectures for next generation Intel Atom processors.

Table 2-7 lists MSRs common to processors based on the Silvermont and Airmont microarchitectures, but not

newer microarchitectures.

Table 2-8, Table 2-9, and Table 2-10 lists MSRs that are model-specific across processors based on the Silvermont

microarchitecture.

In the Silvermont microarchitecture, the scope column indicates the following: “Core” means each processor core

has a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit field

is shared by a subset of the processor cores in the physical package. The number of processor cores in this subset

is model specific and may differ between different processors. For all processors based on Silvermont microarchi-

tecture, the L2 cache is also shared between cores in a module and thus CPUID leaf 04H enumeration can be used

to figure out which processors are in the same module. “Package” means all processor cores in the physical

package share the same MSR or bit interface.

Vol. 4

2-93

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom®

Processors

Address

Scope

Bit Description

Hex

Dec

IA32_P5_MC_ADDR

Module

See Section 2.23, “MSRs in Pentium Processors.”

IA32_P5_MC_TYPE

Module

See Section 2.23, “MSRs in Pentium Processors.”

IA32_MONITOR_FILTER_SIZE

Core

See Section 9.10.5, “Monitor/Mwait Address Range

Determination,” and Table 2-2.

10H

IA32_TIME_STAMP_COUNTER

Core

See Section 18.17, “Time-Stamp Counter,” and

Table 2-2.

1BH

IA32_APIC_BASE

Core

See Section 11.4.4, “Local APIC Status and Location,”

and Table 2-2.

2AH

MSR_EBL_CR_POWERON

Module

Processor Hard Power-On Configuration (R/W)

Writes ignored.

63:0

Reserved

34H

MSR_SMI_COUNT

Core

SMI Counter (R/O)

31:0

SMI Count (R/O)

Running count of SMI events since last RESET.

63:32

Reserved

79H

121

IA32_BIOS_UPDT_TRIG

Core

BIOS Update Trigger Register (W)

See Table 2-2.

8BH

139

IA32_BIOS_SIGN_ID

Core

BIOS Update Signature ID (R/W)

See Table 2-2.

C1H

193

IA32_PMC0

Core

Performance counter register

See Table 2-2.

C2H

194

IA32_PMC1

Core

Performance Counter Register

See Table 2-2.

E4H

228

MSR_PMG_IO_CAPTURE_BASE

Module

Power Management IO Redirection in C-state (R/W)

See http://biosbits.org.

15:0

LVL_2 Base Address (R/W)

Specifies the base address visible to software for IO

redirection. If IO MWAIT Redirection is enabled, reads to

this address will be consumed by the power

management logic and decoded to MWAIT instructions.

When IO port address redirection is enabled, this is the

IO port address reported to the OS/software.

2-94 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom®

Processors (Contd.)

Address

Scope

Bit Description

Hex

Dec

18:16

C-state Range (R/W)

Specifies the encoding value of the maximum C-State

code name to be included when IO read to MWAIT

redirection is enabled by

MSR_PKG_CST_CONFIG_CONTROL[bit10]:

100b - C4 is the max C-State to include

110b - C6 is the max C-State to include

111b - C7 is the max C-State to include

63:19

Reserved

E7H

231

IA32_MPERF

Core

Maximum Performance Frequency Clock Count (R/W)

See Table 2-2.

E8H

232

IA32_APERF

Core

Actual Performance Frequency Clock Count (R/W)

See Table 2-2.

FEH

254

IA32_MTRRCAP

Core

Memory Type Range Register (R)

See Table 2-2.

13CH

316

MSR_FEATURE_CONFIG

Core

AES Configuration (RW-L)

Privileged post-BIOS agent must provide a #GP handler

to handle unsuccessful read of this MSR.

1:0

AES Configuration (RW-L)

Upon a successful read of this MSR, the configuration of

AES instruction sets availability is as follows:

11b: AES instructions are not available until next

RESET.

Otherwise, AES instructions are available.

Note: AES instruction set is not available if read is

unsuccessful. If the configuration is not 01b, AES

instructions can be mis-configured if a privileged agent

unintentionally writes 11b.

63:2

Reserved

174H

372

IA32_SYSENTER_CS

Core

See Table 2-2.

175H

373

IA32_SYSENTER_ESP

Core

See Table 2-2.

176H

374

IA32_SYSENTER_EIP

Core

See Table 2-2.

179H

377

IA32_MCG_CAP

Core

See Table 2-2.

17AH

378

IA32_MCG_STATUS

Core

Global Machine Check Status

RIPV

When set, bit indicates that the instruction addressed

by the instruction pointer pushed on the stack (when

the machine check was generated) can be used to

restart the program. If cleared, the program cannot be

reliably restarted.

Vol. 4

2-95

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom®

Processors (Contd.)

Address

Scope

Bit Description

Hex

Dec

EIPV

When set, bit indicates that the instruction addressed

by the instruction pointer pushed on the stack (when

the machine check was generated) is directly

associated with the error.

MCIP

When set, bit indicates that a machine check has been

generated. If a second machine check is detected while

this bit is still set, the processor enters a shutdown

state. Software should write this bit to 0 after

processing a machine check exception.

63:3

Reserved

186H

390

IA32_PERFEVTSEL0

Core

See Table 2-2.

7:0

Event Select

15:8

UMask

USR

Edge

INT

Reserved

INV

31:24

CMASK

63:32

Reserved

187H

391

IA32_PERFEVTSEL1

Core

See Table 2-2.

198H

408

IA32_PERF_STATUS

Module

See Table 2-2.

199H

409

IA32_PERF_CTL

Core

See Table 2-2.

19AH

410

IA32_CLOCK_MODULATION

Core

Clock Modulation (R/W)

See Table 2-2.

IA32_CLOCK_MODULATION MSR was originally named

IA32_THERM_CONTROL MSR.

19BH

411

IA32_THERM_INTERRUPT

Core

Thermal Interrupt Control (R/W)

See Table 2-2.

19CH

412

IA32_THERM_STATUS

Core

Thermal Monitor Status (R/W)

See Table 2-2.

1A2H

418

MSR_TEMPERATURE_TARGET

Package

Temperature Target

15:0

Reserved

2-96 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom®

Processors (Contd.)

Address

Scope

Bit Description

Hex

Dec

23:16

Temperature Target (R)

The default thermal throttling or PROCHOT# activation

temperature in degrees C. The effective temperature

for thermal throttling or PROCHOT# activation is

“Temperature Target” + “Target Offset”.

29:24

Target Offset (R/W)

Specifies an offset in degrees C to adjust the throttling

and PROCHOT# activation temperature from the

default target specified in TEMPERATURE_TARGET

(bits 23:16).

63:30

Reserved

1A6H

422

MSR_OFFCORE_RSP_0

Module

Offcore Response Event Select Register (R/W)

1A7H

423

MSR_OFFCORE_RSP_1

Module

Offcore Response Event Select Register (R/W)

1B0H

432

IA32_ENERGY_PERF_BIAS

Core

See Table 2-2.

1D9H

473

IA32_DEBUGCTL

Core

Debug Control (R/W)

See Table 2-2.

1DDH

477

MSR_LER_FROM_LIP

Core

Last Exception Record From Linear IP (R/W)

Contains a pointer to the last branch instruction that

the processor executed prior to the last exception that

was generated or the last interrupt that was handled.

1DEH

478

MSR_LER_TO_LIP

Core

Last Exception Record To Linear IP (R/W)

This area contains a pointer to the target of the last

branch instruction that the processor executed prior to

the last exception that was generated or the last

interrupt that was handled.

1F2H

498

IA32_SMRR_PHYSBASE

Core

See Table 2-2.

1F3H

499

IA32_SMRR_PHYSMASK

Core

See Table 2-2.

200H

512

IA32_MTRR_PHYSBASE0

Core

See Table 2-2.

201H

513

IA32_MTRR_PHYSMASK0

Core

See Table 2-2.

202H

514

IA32_MTRR_PHYSBASE1

Core

See Table 2-2.

203H

515

IA32_MTRR_PHYSMASK1

Core

See Table 2-2.

204H

516

IA32_MTRR_PHYSBASE2

Core

See Table 2-2.

205H

517

IA32_MTRR_PHYSMASK2

Core

See Table 2-2.

206H

518

IA32_MTRR_PHYSBASE3

Core

See Table 2-2.

207H

519

IA32_MTRR_PHYSMASK3

Core

See Table 2-2.

208H

520

IA32_MTRR_PHYSBASE4

Core

See Table 2-2.

209H

521

IA32_MTRR_PHYSMASK4

Core

See Table 2-2.

20AH

522

IA32_MTRR_PHYSBASE5

Core

See Table 2-2.

20BH

523

IA32_MTRR_PHYSMASK5

Core

See Table 2-2.

20CH

524

IA32_MTRR_PHYSBASE6

Core

See Table 2-2.

Vol. 4

2-97

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom®

Processors (Contd.)

Address

Scope

Bit Description

Hex

Dec

20DH

525

IA32_MTRR_PHYSMASK6

Core

See Table 2-2.

20EH

526

IA32_MTRR_PHYSBASE7

Core

See Table 2-2.

20FH

527

IA32_MTRR_PHYSMASK7

Core

See Table 2-2.

250H

592

IA32_MTRR_FIX64K_00000

Core

See Table 2-2.

258H

600

IA32_MTRR_FIX16K_80000

Core

See Table 2-2.

259H

601

IA32_MTRR_FIX16K_A0000

Core

See Table 2-2.

268H

616

IA32_MTRR_FIX4K_C0000

Core

See Table 2-2.

269H

617

IA32_MTRR_FIX4K_C8000

Core

See Table 2-2.

26AH

618

IA32_MTRR_FIX4K_D0000

Core

See Table 2-2.

26BH

619

IA32_MTRR_FIX4K_D8000

Core

See Table 2-2.

26CH

620

IA32_MTRR_FIX4K_E0000

Core

See Table 2-2.

26DH

621

IA32_MTRR_FIX4K_E8000

Core

See Table 2-2.

26EH

622

IA32_MTRR_FIX4K_F0000

Core

See Table 2-2.

26FH

623

IA32_MTRR_FIX4K_F8000

Core

See Table 2-2.

277H

631

IA32_PAT

Core

See Table 2-2.

2FFH

767

IA32_MTRR_DEF_TYPE

Core

Default Memory Types (R/W)

See Table 2-2.

309H

777

IA32_FIXED_CTR0

Core

Fixed-Function Performance Counter Register 0 (R/W)

See Table 2-2.

30AH

778

IA32_FIXED_CTR1

Core

Fixed-Function Performance Counter Register 1 (R/W)

See Table 2-2.

30BH

779

IA32_FIXED_CTR2

Core

Fixed-Function Performance Counter Register 2 (R/W)

See Table 2-2.

345H

837

IA32_PERF_CAPABILITIES

Core

See Table 2-2. See Section 18.4.1, “IA32_DEBUGCTL

MSR.”

38DH

909

IA32_FIXED_CTR_CTRL

Core

Fixed-Function-Counter Control Register (R/W)

See Table 2-2.

38FH

911

IA32_PERF_GLOBAL_CTRL

Core

See Table 2-2. See Section 20.6.2.2, “Global Counter

Control Facilities.”

3FDH

1021

MSR_CORE_C6_RESIDENCY

Core

Note: C-state values are processor specific C-state code

names, unrelated to MWAIT extension C-state

parameters or ACPI C-States.

63:0

CORE C6 Residency Counter (R/O)

Value since last reset that this core is in processor-

specific C6 states. Counts at the TSC Frequency.

400H

1024

IA32_MC0_CTL

Module

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

401H

1025

IA32_MC0_STATUS

Module

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

2-98 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom®

Processors (Contd.)

Address

Scope

Bit Description

Hex

Dec

402H

1026

IA32_MC0_ADDR

Module

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The IA32_MC0_ADDR register is either not

implemented or contains no address if the ADDRV flag

in the IA32_MC0_STATUS register is clear.

When not implemented in the processor, all reads and

writes to this MSR will cause a general-protection

exception.

404H

1028

IA32_MC1_CTL

Module

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

405H

1029

IA32_MC1_STATUS

Module

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

408H

1032

IA32_MC2_CTL

Module

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

409H

1033

IA32_MC2_STATUS

Module

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

40AH

1034

IA32_MC2_ADDR

Module

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The IA32_MC2_ADDR register is either not

implemented or contains no address if the ADDRV flag

in the IA32_MC2_STATUS register is clear.

When not implemented in the processor, all reads and

writes to this MSR will cause a general-protection

exception.

40CH

1036

IA32_MC3_CTL

Core

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

40DH

1037

IA32_MC3_STATUS

Core

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

40EH

1038

IA32_MC3_ADDR

Core

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The MSR_MC3_ADDR register is either not

implemented or contains no address if the ADDRV flag

in the MSR_MC3_STATUS register is clear.

When not implemented in the processor, all reads and

writes to this MSR will cause a general-protection

exception.

410H

1040

IA32_MC4_CTL

Core

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

411H

1041

IA32_MC4_STATUS

Core

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

412H

1042

IA32_MC4_ADDR

Core

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The MSR_MC4_ADDR register is either not

implemented or contains no address if the ADDRV flag

in the MSR_MC4_STATUS register is clear.

When not implemented in the processor, all reads and

writes to this MSR will cause a general-protection

exception.

414H

1044

IA32_MC5_CTL

Package

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

415H

1045

IA32_MC5_STATUS

Package

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

Vol. 4

2-99

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom®

Processors (Contd.)

Address

Scope

Bit Description

Hex

Dec

416H

1046

IA32_MC5_ADDR

Package

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

The MSR_MC4_ADDR register is either not

implemented or contains no address if the ADDRV flag

in the MSR_MC4_STATUS register is clear.

When not implemented in the processor, all reads and

writes to this MSR will cause a general-protection

exception.

480H

1152

IA32_VMX_BASIC

Core

Reporting Register of Basic VMX Capabilities (R/O)

See Table 2-2.

See Appendix A.1, “Basic VMX Information.”

481H

1153

IA32_VMX_PINBASED_CTLS

Core

Capability Reporting Register of Pin-Based

VM-Execution Controls (R/O)

See Table 2-2.

See Appendix A.3, “VM-Execution Controls.”

482H

1154

IA32_VMX_PROCBASED_CTLS

Core

Capability Reporting Register of Primary Processor-

Based VM-Execution Controls (R/O)

See Appendix A.3, “VM-Execution Controls.”

483H

1155

IA32_VMX_EXIT_CTLS

Core

Capability Reporting Register of VM-Exit Controls (R/O)

See Table 2-2.

See Appendix A.4, “VM-Exit Controls.”

484H

1156

IA32_VMX_ENTRY_CTLS

Core

Capability Reporting Register of VM-Entry Controls

(R/O)

See Table 2-2.

See Appendix A.5, “VM-Entry Controls.”

485H

1157

IA32_VMX_MISC

Core

Reporting Register of Miscellaneous VMX Capabilities

(R/O)

See Table 2-2.

See Appendix A.6, “Miscellaneous Data.”

486H

1158

IA32_VMX_CR0_FIXED0

Core

Capability Reporting Register of CR0 Bits Fixed to 0

(R/O)

See Table 2-2.

See Appendix A.7, “VMX-Fixed Bits in CR0.”

487H

1159

IA32_VMX_CR0_FIXED1

Core

Capability Reporting Register of CR0 Bits Fixed to 1

(R/O)

See Table 2-2.

See Appendix A.7, “VMX-Fixed Bits in CR0.”

488H

1160

IA32_VMX_CR4_FIXED0

Core

Capability Reporting Register of CR4 Bits Fixed to 0

(R/O)

See Table 2-2.

See Appendix A.8, “VMX-Fixed Bits in CR4.”

2-100 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom®

Processors (Contd.)

Address

Scope

Bit Description

Hex

Dec

489H

1161

IA32_VMX_CR4_FIXED1

Core

Capability Reporting Register of CR4 Bits Fixed to 1

(R/O)

See Table 2-2.

See Appendix A.8, “VMX-Fixed Bits in CR4.”

48AH

1162

IA32_VMX_VMCS_ENUM

Core

Capability Reporting Register of VMCS Field

Enumeration (R/O)

See Table 2-2.

See Appendix A.9, “VMCS Enumeration.”

48BH

1163

IA32_VMX_PROCBASED_CTLS2

Core

Capability Reporting Register of Secondary Processor-

Based VM-Execution Controls (R/O)

See Appendix A.3, “VM-Execution Controls.”

48CH

1164

IA32_VMX_EPT_VPID_ENUM

Core

Capability Reporting Register of EPT and VPID (R/O)

See Table 2-2

48DH

1165

IA32_VMX_TRUE_PINBASED_CTLS

Core

Capability Reporting Register of Pin-Based

VM-Execution Flex Controls (R/O)

See Table 2-2

48EH

1166

IA32_VMX_TRUE_PROCBASED_CTLS

Core

Capability Reporting Register of Primary Processor-

based VM-Execution Flex Controls (R/O)

See Table 2-2

48FH

1167

IA32_VMX_TRUE_EXIT_CTLS

Core

Capability Reporting Register of VM-Exit Flex Controls

(R/O)

See Table 2-2

490H

1168

IA32_VMX_TRUE_ENTRY_CTLS

Core

Capability Reporting Register of VM-Entry Flex Controls

(R/O)

See Table 2-2

491H

1169

IA32_VMX_FMFUNC

Core

Capability Reporting Register of VM-Function Controls

(R/O)

See Table 2-2

4C1H

1217

IA32_A_PMC0

Core

See Table 2-2.

4C2H

1218

IA32_A_PMC1

Core

See Table 2-2.

600H

1536

IA32_DS_AREA

Core

DS Save Area (R/W)

See Table 2-2.

See Section 20.6.3.4, “Debug Store (DS) Mechanism.”

660H

1632

MSR_CORE_C1_RESIDENCY

Core

Note: C-state values are processor specific C-state code

names, unrelated to MWAIT extension C-state

parameters or ACPI C-States.

63:0

CORE C1 Residency Counter. (R/O)

Value since last reset that this core is in processor-

specific C1 states. Counts at the TSC frequency.

6E0H

1760

IA32_TSC_DEADLINE

Core

TSC Target of Local APIC’s TSC Deadline Mode (R/W)

See Table 2-2.

Vol. 4

2-101

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-6. MSRs Common to the Silvermont Microarchitecture and Newer Microarchitectures for Intel Atom®

Processors (Contd.)

Address

Scope

Bit Description

Hex

Dec

C000_

IA32_EFER

Core

Extended Feature Enables

0080H

See Table 2-2.

C000_

IA32_STAR

Core

System Call Target Address (R/W)

0081H

See Table 2-2.

C000_

IA32_LSTAR

Core

IA-32e Mode System Call Target Address (R/W)

0082H

See Table 2-2.

C000_

IA32_FMASK

Core

System Call Flag Mask (R/W)

0084H

See Table 2-2.

C000_

IA32_FS_BASE

Core

Map of BASE Address of FS (R/W)

0100H

See Table 2-2.

C000_

IA32_GS_BASE

Core

Map of BASE Address of GS (R/W)

0101H

See Table 2-2.

C000_

IA32_KERNEL_GS_BASE

Core

Swap Target of BASE Address of GS (R/W)

0102H

See Table 2-2.

C000_

IA32_TSC_AUX

Core

AUXILIARY TSC Signature (R/W)

0103H

See Table 2-2.

Table 2-7 lists model-specific registers (MSRs) that are common to Intel Atom^® processors based on the Silver-

mont and Airmont microarchitectures but not newer microarchitectures.

Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures

Address

Scope

Bit Description

Hex

Dec

17H

MSR_PLATFORM_ID

Module

Model Specific Platform ID (R)

7:0

Reserved

13:8

Maximum Qualified Ratio (R)

The maximum allowed bus ratio.

49:13

Reserved

52:50

See Table 2-2.

63:33

Reserved

3AH

IA32_FEATURE_CONTROL

Core

Control Features in Intel 64Processor (R/W)

See Table 2-2.

Lock (R/WL)

Reserved

Enable VMX outside SMX operation (R/WL)

2-102 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures

Address

Scope

Bit Description

Hex

Dec

40H

MSR_LASTBRANCH_0_FROM_IP

Core

Last Branch Record 0 From IP (R/W)

One of eight pairs of last branch record registers on the

last branch record stack. The From_IP part of the stack

contains pointers to the source instruction. See also:

• Last Branch Record Stack TOS at 1C9H.

• Section 18.5 and record format in Section 18.4.8.1.

41H

MSR_LASTBRANCH_1_FROM_IP

Core

Last Branch Record 1 From IP (R/W)

See description of MSR_LASTBRANCH_0_FROM_IP.

42H

MSR_LASTBRANCH_2_FROM_IP

Core

Last Branch Record 2 From IP (R/W)

See description of MSR_LASTBRANCH_0_FROM_IP.

43H

MSR_LASTBRANCH_3_FROM_IP

Core

Last Branch Record 3 From IP (R/W)

See description of MSR_LASTBRANCH_0_FROM_IP.

44H

MSR_LASTBRANCH_4_FROM_IP

Core

Last Branch Record 4 From IP (R/W)

See description of MSR_LASTBRANCH_0_FROM_IP.

45H

MSR_LASTBRANCH_5_FROM_IP

Core

Last Branch Record 5 From IP (R/W)

See description of MSR_LASTBRANCH_0_FROM_IP.

46H

MSR_LASTBRANCH_6_FROM_IP

Core

Last Branch Record 6 From IP (R/W)

See description of MSR_LASTBRANCH_0_FROM_IP.

47H

MSR_LASTBRANCH_7_FROM_IP

Core

Last Branch Record 7 From IP (R/W)

See description of MSR_LASTBRANCH_0_FROM_IP.

60H

MSR_LASTBRANCH_0_TO_IP

Core

Last Branch Record 0 To IP (R/W)

One of eight pairs of last branch record registers on the

last branch record stack. The To_IP part of the stack

contains pointers to the destination instruction.

61H

MSR_LASTBRANCH_1_TO_IP

Core

Last Branch Record 1 To IP (R/W)

See description of MSR_LASTBRANCH_0_TO_IP.

62H

MSR_LASTBRANCH_2_TO_IP

Core

Last Branch Record 2 To IP (R/W)

See description of MSR_LASTBRANCH_0_TO_IP.

63H

MSR_LASTBRANCH_3_TO_IP

Core

Last Branch Record 3 To IP (R/W)

See description of MSR_LASTBRANCH_0_TO_IP.

64H

100

MSR_LASTBRANCH_4_TO_IP

Core

Last Branch Record 4 To IP (R/W)

See description of MSR_LASTBRANCH_0_TO_IP.

65H

101

MSR_LASTBRANCH_5_TO_IP

Core

Last Branch Record 5 To IP (R/W)

See description of MSR_LASTBRANCH_0_TO_IP.

66H

102

MSR_LASTBRANCH_6_TO_IP

Core

Last Branch Record 6 To IP (R/W)

See description of MSR_LASTBRANCH_0_TO_IP.

67H

103

MSR_LASTBRANCH_7_TO_IP

Core

Last Branch Record 7 To IP (R/W)

See description of MSR_LASTBRANCH_0_TO_IP.

CEH

206

MSR_PLATFORM_INFO

Package

Platform Information: Contains power management and

other model specific features enumeration. See

http://biosbits.org.

Vol. 4

2-103

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures

Address

Scope

Bit Description

Hex

Dec

7:0

Reserved

15:8

Package

Maximum Non-Turbo Ratio (R/O)

This is the ratio of the maximum frequency that does not

require turbo. Frequency = ratio * Scalable Bus

Frequency.

63:16

Reserved

E2H

226

MSR_PKG_CST_CONFIG_CONTROL

Module

C-State Configuration Control (R/W)

Note: C-state values are processor specific C-state code

names, unrelated to MWAIT extension C-state

parameters or ACPI C-States.

See http://biosbits.org.

2:0

Package C-State Limit (R/W)

Specifies the lowest processor-specific C-state code

name (consuming the least power) for the package. The

default is set as factory-configured package C-state limit.

The following C-state code name encodings are

supported:

000b: C0 (no package C-sate support)

001b: C1 (Behavior is the same as 000b)

100b: C4

110b: C6

111b: C7 (Silvermont only).

9:3

Reserved

I/O MWAIT Redirection Enable (R/W)

When set, will map IO_read instructions sent to IO

MWAIT instructions.

14:11

Reserved

CFG Lock (R/WO)

When set, locks bits 15:0 of this register until next reset.

63:16

Reserved

11EH

281

MSR_BBL_CR_CTL3

Module

Control Register 3

Used to configure the L2 Cache.

L2 Hardware Enabled (R/O)

1 = If the L2 is hardware-enabled.

0 = Indicates if the L2 is hardware-disabled.

7:1

Reserved

L2 Enabled (R/W)

1 = L2 cache has been initialized.

0 = Disabled (default).

Until this bit is set the processor will not respond to the

WBINVD instruction or the assertion of the FLUSH#

input.

2-104 Vol. 4

Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 128