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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 106

INSTRUCTION SET REFERENCE, V

VRSQRT14SS—Compute Approximate Reciprocal of Square Root of Scalar Float32 Value

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F38.W0 4F /r

A

V/V

AVX512F

Computes the approximate reciprocal square root of the

VRSQRT14SS xmm1 {k1}{z},

scalar single-precision floating-point value in xmm3/m32

xmm2, xmm3/m32

and stores the result in the low doubleword element of

xmm1 using writemask k1. Bits[127:32] of xmm2 is copied

to xmm1[127:32].

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Computes of the approximate reciprocal of the square root of the scalar single-precision floating-point value in the

low doubleword element of the source operand (the second operand) and stores the result in the low doubleword

element of the destination operand (the first operand) according to the writemask. The maximum relative error for

this approximation is less than 2^-14. The source operand can be an XMM register or a 32-bit memory location. The

destination operand is an XMM register.

Bits (127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits

(MAXVL-1:128) of the destination register are zeroed.

The VRSQRT14SS instruction is not affected by the rounding control bits in the MXCSR register. When a source

value is a 0.0, an ∞ with the sign of the source value is returned. When the source operand is an ∞, zero with the

sign of the source value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR.

Otherwise it is treated correctly and performs the approximation with the specified masked response. When a

source value is a negative value (other than 0.0) a floating-point indefinite is returned. When a source value is an

SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned.

MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.

A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-

cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRSQRT14SS (EVEX version)

IF k1[0] or *no writemask*

THEN DEST[31:0] := APPROXIMATE(1.0/ SQRT(SRC2[31:0]))

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[31:0] remains unchanged*

ELSE

; zeroing-masking

THEN DEST[31:0] := 0

FI;

FI;

DEST[127:32] := SRC1[127:32]

DEST[MAXVL-1:128] := 0

VRSQRT14SS—Compute Approximate Reciprocal of Square Root of Scalar Float32 Value

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INSTRUCTION SET REFERENCE, V

Table 5-27. VRSQRT14SS Special Cases

Input value

Result value

Comments

Any denormal

Normal

Cannot generate overflow

X = 2^-2n

2ⁿ

X < 0

QNaN_Indefinite

Including -INF

X = -0

-INF

X = +0

+INF

X = +INF

+0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT14SS __m128 _mm_rsqrt14_ss( __m128 a, __m128 b);

VRSQRT14SS __m128 _mm_mask_rsqrt14_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);

VRSQRT14SS __m128 _mm_maskz_rsqrt14_ss( __mmask8 k, __m128 a, __m128 b);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-51, “Type E5 Class Exception Conditions.”

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Vol. 2C

VRSQRT14SS—Compute Approximate Reciprocal of Square Root of Scalar Float32 Value

INSTRUCTION SET REFERENCE, V

VRSQRTPH—Compute Reciprocals of Square Roots of Packed FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.128.66.MAP6.W0 4E /r

A

V/V

AVX512-FP16

Compute the approximate reciprocals of the

VRSQRTPH xmm1{k1}{z}, xmm2/

AVX512VL

square roots of packed FP16 values in xmm2/

m128/m16bcst

m128/m16bcst and store the result in xmm1

subject to writemask k1.

EVEX.256.66.MAP6.W0 4E /r

A

V/V

AVX512-FP16

Compute the approximate reciprocals of the

VRSQRTPH ymm1{k1}{z}, ymm2/

AVX512VL

square roots of packed FP16 values in ymm2/

m256/m16bcst

m256/m16bcst and store the result in ymm1

subject to writemask k1.

EVEX.512.66.MAP6.W0 4E /r

A

V/V

AVX512-FP16

Compute the approximate reciprocals of the

VRSQRTPH zmm1{k1}{z}, zmm2/

square roots of packed FP16 values in zmm2/

m512/m16bcst

m512/m16bcst and store the result in zmm1

subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

This instruction performs a SIMD computation of the approximate reciprocals square-root of 8/16/32 packed FP16

floating-point values in the source operand (the second operand) and stores the packed FP16 floating-point results

in the destination operand.

The maximum relative error for this approximation is less than 2⁻¹¹ + 2⁻¹⁴. For special cases, see Table 5-28.

The destination elements are updated according to the writemask.

Table 5-28. VRSQRTPH/VRSQRTSH Special Cases

Input value

Reset Value

Comments

Any denormal

Normal

Cannot generate overflow

X = 2⁻²ⁿ

2n

X < 0

QNaN_Indefinite

Including −∞

X = −0

−∞

X = +0

+∞

X = +∞

+0

VRSQRTPH—Compute Reciprocals of Square Roots of Packed FP16 Values

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5-679

INSTRUCTION SET REFERENCE, V

VRSQRTSH—Compute Approximate Reciprocal of Square Root of Scalar FP16 Value

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.LLIG.66.MAP6.W0 4F /r

A

V/V

AVX512-FP16

Compute the approximate reciprocal square root

VRSQRTSH xmm1{k1}{z}, xmm2,

of the FP16 value in xmm3/m16 and store the

xmm3/m16

result in the low word element of xmm1 subject

to writemask k1. Bits 127:16 of xmm2 are

copied to xmm1[127:16].

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction performs the computation of the approximate reciprocal square-root of the low FP16 value in the

second source operand (the third operand) and stores the result in the low word element of the destination operand

(the first operand) according to the writemask k1.

The maximum relative error for this approximation is less than 2⁻¹¹ + 2⁻¹⁴.

Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits

MAXVL−1:128 of the destination operand are zeroed.

For special cases, see Table 5-28.

Operation

VRSQRTSH dest{k1}, src1, src2

VL = 128, 256 or 512

KL := VL/16

IF k1[0] or *no writemask*:

DEST.fp16[0] := APPROXIMATE(1.0 / SQRT(src2.fp16[0]))

ELSE IF *zeroing*:

DEST.fp16[0] := 0

//else DEST.fp16[0] remains unchanged

DEST[127:16] := src1[127:16]

DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRTSH __m128h _mm_mask_rsqrt_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);

VRSQRTSH __m128h _mm_maskz_rsqrt_sh (__mmask8 k, __m128h a, __m128h b);

VRSQRTSH __m128h _mm_rsqrt_sh (__m128h a, __m128h b);

SIMD Floating-Point Exceptions

None.

Other Exceptions

EVEX-encoded instruction, see Table 2-58, “Type E10 Class Exception Conditions.”

VRSQRTSH—Compute Approximate Reciprocal of Square Root of Scalar FP16 Value

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INSTRUCTION SET REFERENCE, V

VSCALEFPD—Scale Packed Float64 Values With Float64 Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.128.66.0F38.W1 2C /r

A

V/V

AVX512VL

Scale the packed double precision floating-point values in

VSCALEFPD xmm1 {k1}{z}, xmm2,

AVX512F

xmm2 using values from xmm3/m128/m64bcst. Under

xmm3/m128/m64bcst

writemask k1.

EVEX.256.66.0F38.W1 2C /r

A

V/V

AVX512VL

Scale the packed double precision floating-point values in

VSCALEFPD ymm1 {k1}{z}, ymm2,

AVX512F

ymm2 using values from ymm3/m256/m64bcst. Under

ymm3/m256/m64bcst

writemask k1.

EVEX.512.66.0F38.W1 2C /r

A

V/V

AVX512F

Scale the packed double precision floating-point values in

VSCALEFPD zmm1 {k1}{z}, zmm2,

zmm2 using values from zmm3/m512/m64bcst. Under

zmm3/m512/m64bcst{er}

writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a floating-point scale of the packed double precision floating-point values in the first source operand by

multiplying them by 2 to the power of the double precision floating-point values in second source operand.

The equation of this operation is given by:

zmm1 := zmm2*2^floor(zmm3).

Floor(zmm3) means maximum integer value ≤ zmm3.

If the result cannot be represented in double precision, then the proper overflow response (for positive scaling

operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow

responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in

MXCSR (exception mask bits, FTZ bit), and on the SAE bit.

The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, a

512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The

destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.

Handling of special-case input values are listed in Table 5-29 and Table 5-30.

Table 5-29. VSCALEFPD/SD/PS/SS Special Cases

Src2

Set IE

±NaN

+Inf

-Inf

0/Denorm/Norm

Src1

±QNaN

QNaN(Src1)

+INF

+0

QNaN(Src1)

IF either source is SNAN

±SNaN

QNaN(Src1)

QNaN(Src1)

QNaN(Src1)

QNaN(Src1)

YES

±Inf

QNaN(Src2)

Src1

QNaN_Indefinite

Src1

IF Src2 is SNAN or -INF

±0

QNaN(Src2)

QNaN_Indefinite

Src1

Src1

IF Src2 is SNAN or +INF

Denorm/Norm

QNaN(Src2)

±INF (Src1 sign)

±0 (Src1 sign)

Compute Result

IF Src2 is SNAN

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VSCALEFPD—Scale Packed Float64 Values With Float64 Values

INSTRUCTION SET REFERENCE, V

Table 5-30. Additional VSCALEFPD/SD Special Cases

Special Case

Returned value

Faults

|result| < 2^-1074

±0 or ±Min-Denormal (Src1 sign)

Underflow

|result| ≥ 2¹⁰²⁴

±INF (Src1 sign) or ±Max-normal (Src1 sign)

Overflow

Operation

SCALE(SRC1, SRC2)

{

TMP_SRC2 := SRC2

TMP_SRC1 := SRC1

IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0

IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0

/* SRC2 is a 64 bits floating-point value */

DEST[63:0] := TMP_SRC1[63:0] * POW(2, Floor(TMP_SRC2[63:0]))

}

VSCALEFPD (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

IF (VL = 512) AND (EVEX.b = 1) AND (SRC2 *is register*)

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN DEST[i+63:i] := SCALE(SRC1[i+63:i], SRC2[63:0]);

ELSE DEST[i+63:i] := SCALE(SRC1[i+63:i], SRC2[i+63:i]);

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VSCALEFPD—Scale Packed Float64 Values With Float64 Values

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INSTRUCTION SET REFERENCE, V

VSCALEFPH—Scale Packed FP16 Values with FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.128.66.MAP6.W0 2C /r

A

V/V

AVX512-FP16

Scale the packed FP16 values in xmm2 using

VSCALEFPH xmm1{k1}{z}, xmm2,

AVX512VL

values from xmm3/m128/m16bcst, and store

xmm3/m128/m16bcst

the result in xmm1 subject to writemask k1.

EVEX.256.66.MAP6.W0 2C /r

A

V/V

AVX512-FP16

Scale the packed FP16 values in ymm2 using

VSCALEFPH ymm1{k1}{z}, ymm2,

AVX512VL

values from ymm3/m256/m16bcst, and store the

ymm3/m256/m16bcst

result in ymm1 subject to writemask k1.

EVEX.512.66.MAP6.W0 2C /r

A

V/V

AVX512-FP16

Scale the packed FP16 values in zmm2 using

VSCALEFPH zmm1{k1}{z}, zmm2,

values from zmm3/m512/m16bcst, and store the

zmm3/m512/m16bcst {er}

result in zmm1 subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction performs a floating-point scale of the packed FP16 values in the first source operand by multiplying

it by 2 to the power of the FP16 values in second source operand. The destination elements are updated according

to the writemask.

The equation of this operation is given by:

zmm1 := zmm2 * 2^floor(zmm3).

Floor(zmm3) means maximum integer value ≤ zmm3.

If the result cannot be represented in FP16, then the proper overflow response (for positive scaling operand), or

the proper underflow response (for negative scaling operand), is issued. The overflow and underflow responses are

dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in MXCSR (exception

mask bits), and on the SAE bit.

Handling of special-case input values are listed in Table 5-31 and Table 5-32.

Table 5-31. VSCALEFPH/VSCALEFSH Special Cases

Src2

Src1

Set IE

±NaN

+INF

−INF

0/Denorm/Norm

±QNaN

QNaN(Src1)

+INF

+0

QNaN(Src1)

IF either source is SNaN

±SNaN

QNaN(Src1)

QNaN(Src1)

QNaN(Src1)

QNaN(Src1)

YES

±INF

QNaN(Src2)

Src1

QNaN_Indefinite

Src1

IF Src2 is SNaN or −INF

±0

QNaN(Src2)

QNaN_Indefinite

Src1

Src1

IF Src2 is SNaN or +INF

Denorm/Norm

QNaN(Src2)

±INF (Src1 sign)

±0 (Src1 sign)

Compute Result

IF Src2 is SNaN

Table 5-32. Additional VSCALEFPH/VSCALEFSH Special Cases

Special Case

Returned Value

Faults

|result| < 2^-24

±0 or ±Min-Denormal (Src1 sign)

Underflow

|result| ≥ 2¹⁶

±INF (Src1 sign) or ±Max-Denormal (Src1 sign)

Overflow

VSCALEFPH—Scale Packed FP16 Values with FP16 Values

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INSTRUCTION SET REFERENCE, V

VSCALEFPS—Scale Packed Float32 Values With Float32 Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.128.66.0F38.W0 2C /r

A

V/V

AVX512VL

Scale the packed single-precision floating-point values in

VSCALEFPS xmm1 {k1}{z}, xmm2,

AVX512F

xmm2 using values from xmm3/m128/m32bcst. Under

xmm3/m128/m32bcst

writemask k1.

EVEX.256.66.0F38.W0 2C /r

A

V/V

AVX512VL

Scale the packed single-precision values in ymm2 using

VSCALEFPS ymm1 {k1}{z}, ymm2,

AVX512F

floating-point values from ymm3/m256/m32bcst. Under

ymm3/m256/m32bcst

writemask k1.

EVEX.512.66.0F38.W0 2C /r

A

V/V

AVX512F

Scale the packed single-precision floating-point values in

VSCALEFPS zmm1 {k1}{z}, zmm2,

zmm2 using floating-point values from

zmm3/m512/m32bcst{er}

zmm3/m512/m32bcst. Under writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a floating-point scale of the packed single-precision floating-point values in the first source operand by

multiplying them by 2 to the power of the float32 values in second source operand.

The equation of this operation is given by:

zmm1 := zmm2*2^floor(zmm3).

Floor(zmm3) means maximum integer value ≤ zmm3.

If the result cannot be represented in single-precision, then the proper overflow response (for positive scaling

operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow

responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in

MXCSR (exception mask bits, FTZ bit), and on the SAE bit.

EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM

register, a 512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location. The destina-

tion operand is a ZMM register conditionally updated with writemask k1.

EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM

register, a 256-bit memory location, or a 256-bit vector broadcasted from a 32-bit memory location. The destina-

tion operand is a YMM register, conditionally updated using writemask k1.

EVEX.128 encoded version: The first source operand is an XMM register. The second source operand is a XMM

register, a 128-bit memory location, or a 128-bit vector broadcasted from a 32-bit memory location. The destina-

tion operand is a XMM register, conditionally updated using writemask k1.

Handling of special-case input values are listed in Table 5-29 and Table 5-33.

Table 5-33. Additional VSCALEFPS/SS Special Cases

Special Case

Returned value

Faults

|result| < 2^-149

±0 or ±Min-Denormal (Src1 sign)

Underflow

|result| ≥ 2¹²⁸

±INF (Src1 sign) or ±Max-normal (Src1 sign)

Overflow

VSCALEFPS—Scale Packed Float32 Values With Float32 Values

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INSTRUCTION SET REFERENCE, V

VSCALEFSD—Scale Scalar Float64 Values With Float64 Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F38.W1 2D /r

A

V/V

AVX512F

Scale the scalar double precision floating-point values in

VSCALEFSD xmm1 {k1}{z}, xmm2,

xmm2 using the value from xmm3/m64. Under writemask

xmm3/m64{er}

k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a floating-point scale of the scalar double precision floating-point value in the first source operand by

multiplying it by 2 to the power of the double precision floating-point value in second source operand.

The equation of this operation is given by:

xmm1 := xmm2*2^floor(xmm3).

Floor(xmm3) means maximum integer value ≤ xmm3.

If the result cannot be represented in double precision, then the proper overflow response (for positive scaling

operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow

responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in

MXCSR (exception mask bits, FTZ bit), and on the SAE bit.

EVEX encoded version: The first source operand is an XMM register. The second source operand is an XMM register

or a memory location. The destination operand is an XMM register conditionally updated with writemask k1.

Handling of special-case input values are listed in Table 5-29 and Table 5-30.

Operation

SCALE(SRC1, SRC2)

{

; Check for denormal operands

TMP_SRC2 := SRC2

TMP_SRC1 := SRC1

IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0

IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0

/* SRC2 is a 64 bits floating-point value */

DEST[63:0] := TMP_SRC1[63:0] * POW(2, Floor(TMP_SRC2[63:0]))

}

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Vol. 2C

VSCALEFSD—Scale Scalar Float64 Values With Float64 Values

INSTRUCTION SET REFERENCE, V

VSCALEFSH—Scale Scalar FP16 Values with FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.LLIG.66.MAP6.W0 2D /r

A

V/V

AVX512-FP16

Scale the FP16 values in xmm2 using the value

VSCALEFSH xmm1{k1}{z}, xmm2,

from xmm3/m16 and store the result in xmm1

xmm3/m16 {er}

subject to writemask k1. Bits 127:16 from xmm2

are copied to xmm1[127:16].

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction performs a floating-point scale of the low FP16 element in the first source operand by multiplying it

by 2 to the power of the low FP16 element in second source operand, storing the result in the low element of the

destination operand.

Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits

MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according

to the writemask.

The equation of this operation is given by:

xmm1 := xmm2 * 2^floor(xmm3).

Floor(xmm3) means maximum integer value ≤ xmm3.

If the result cannot be represented in FP16, then the proper overflow response (for positive scaling operand), or the

proper underflow response (for negative scaling operand), is issued. The overflow and underflow responses are

dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in MXCSR (exception

mask bits, FTZ bit), and on the SAE bit.

Handling of special-case input values are listed in Table 5-31 and Table 5-32.

Operation

VSCALEFSH dest{k1}, src1, src2

IF (EVEX.b = 1) and no memory operand:

SET_RM(EVEX.RC)

ELSE

SET_RM(MXCSR.RC)

IF k1[0] or *no writemask*:

dest.fp16[0] := scale_fp16(src1.fp16[0], src2.fp16[0]) // see VSCALEFPH

ELSE IF *zeroing*:

dest.fp16[0] := 0

//else DEST.fp16[0] remains unchanged

DEST[127:16] := src1[127:16]

DEST[MAXVL-1:128] := 0

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Vol. 2C

VSCALEFSH—Scale Scalar FP16 Values with FP16 Values

INSTRUCTION SET REFERENCE, V

VSCALEFSS—Scale Scalar Float32 Value With Float32 Value

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F38.W0 2D /r

A

V/V

AVX512F

Scale the scalar single-precision floating-point value in

VSCALEFSS xmm1 {k1}{z}, xmm2,

xmm2 using floating-point value from xmm3/m32. Under

xmm3/m32{er}

writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a floating-point scale of the scalar single-precision floating-point value in the first source operand by

multiplying it by 2 to the power of the float32 value in second source operand.

The equation of this operation is given by:

xmm1 := xmm2*2^floor(xmm3).

Floor(xmm3) means maximum integer value ≤ xmm3.

If the result cannot be represented in single-precision, then the proper overflow response (for positive scaling

operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow

responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in

MXCSR (exception mask bits, FTZ bit), and on the SAE bit.

EVEX encoded version: The first source operand is an XMM register. The second source operand is an XMM register

or a memory location. The destination operand is an XMM register conditionally updated with writemask k1.

Handling of special-case input values are listed in Table 5-29 and Table 5-33.

5-694

Vol. 2C

VSCALEFSS—Scale Scalar Float32 Value With Float32 Value

INSTRUCTION SET REFERENCE, V

VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Packed Single, Packed

Double with Signed Dword and Qword Indices

Opcode/

Op/E

64/32

CPUID

Description

Instruction

n

bit Mode

Feature

Support

Flag

EVEX.128.66.0F38.W0 A2 /vsib

A

V/V

AVX512VL

Using signed dword indices, scatter single-precision

VSCATTERDPS vm32x {k1}, xmm1

AVX512F

floating-point values to memory using writemask k1.

EVEX.256.66.0F38.W0 A2 /vsib

A

V/V

AVX512VL

Using signed dword indices, scatter single-precision

VSCATTERDPS vm32y {k1}, ymm1

AVX512F

floating-point values to memory using writemask k1.

EVEX.512.66.0F38.W0 A2 /vsib

A

V/V

AVX512F

Using signed dword indices, scatter single-precision

VSCATTERDPS vm32z {k1}, zmm1

floating-point values to memory using writemask k1.

EVEX.128.66.0F38.W1 A2 /vsib

A

V/V

AVX512VL

Using signed dword indices, scatter double precision

VSCATTERDPD vm32x {k1}, xmm1

AVX512F

floating-point values to memory using writemask k1.

EVEX.256.66.0F38.W1 A2 /vsib

A

V/V

AVX512VL

Using signed dword indices, scatter double precision

VSCATTERDPD vm32x {k1}, ymm1

AVX512F

floating-point values to memory using writemask k1.

EVEX.512.66.0F38.W1 A2 /vsib

A

V/V

AVX512F

Using signed dword indices, scatter double precision

VSCATTERDPD vm32y {k1}, zmm1

floating-point values to memory using writemask k1.

EVEX.128.66.0F38.W0 A3 /vsib

A

V/V

AVX512VL

Using signed qword indices, scatter single-precision

VSCATTERQPS vm64x {k1}, xmm1

AVX512F

floating-point values to memory using writemask k1.

EVEX.256.66.0F38.W0 A3 /vsib

A

V/V

AVX512VL

Using signed qword indices, scatter single-precision

VSCATTERQPS vm64y {k1}, xmm1

AVX512F

floating-point values to memory using writemask k1.

EVEX.512.66.0F38.W0 A3 /vsib

A

V/V

AVX512F

Using signed qword indices, scatter single-precision

VSCATTERQPS vm64z {k1}, ymm1

floating-point values to memory using writemask k1.

EVEX.128.66.0F38.W1 A3 /vsib

A

V/V

AVX512VL

Using signed qword indices, scatter double precision

VSCATTERQPD vm64x {k1}, xmm1

AVX512F

floating-point values to memory using writemask k1.

EVEX.256.66.0F38.W1 A3 /vsib

A

V/V

AVX512VL

Using signed qword indices, scatter double precision

VSCATTERQPD vm64y {k1}, ymm1

AVX512F

floating-point values to memory using writemask k1.

EVEX.512.66.0F38.W1 A3 /vsib

A

V/V

AVX512F

Using signed qword indices, scatter double precision

VSCATTERQPD vm64z {k1}, zmm1

floating-point values to memory using writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

BaseReg (R): VSIB:base,

A

Tuple1 Scalar

ModRM:reg (r)

N/A

N/A

VectorReg(R): VSIB:index

Description

Stores up to 16 elements (or 8 elements) in doubleword/quadword vector zmm1 to the memory locations pointed

by base address BASE_ADDR and index vector VINDEX, with scale SCALE. The elements are specified via the VSIB

(i.e., the index register is a vector register, holding packed indices). Elements will only be stored if their corre-

sponding mask bit is one. The entire mask register will be set to zero by this instruction unless it triggers an excep-

tion.

This instruction can be suspended by an exception if at least one element is already scattered (i.e., if the exception

is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination

register and the mask register (k1) are partially updated. If any traps or interrupts are pending from already scat-

tered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction

breakpoint is not re-triggered when the instruction is continued.

Note that:

• Only writes to overlapping vector indices are guaranteed to be ordered with respect to each other (from LSB to

MSB of the source registers). Note that this also include partially overlapping vector indices. Writes that are not

overlapped may happen in any order. Memory ordering with other instructions follows the Intel-64 memory

ordering model. Note that this does not account for non-overlapping indices that map into the same physical

address locations.

VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Packed Single, Packed Double with Signed Dword and Qword

5-696

Vol. 2C

INSTRUCTION SET REFERENCE, V

VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-Bit

Granularity

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.256.66.0F3A.W0 23 /r ib

A

V/V

AVX512VL

Shuffle 128-bit packed single-precision floating-point

VSHUFF32X4 ymm1{k1}{z}, ymm2,

AVX512F

values selected by imm8 from ymm2 and

ymm3/m256/m32bcst, imm8

ymm3/m256/m32bcst and place results in ymm1

subject to writemask k1.

EVEX.512.66.0F3A.W0 23 /r ib

A

V/V

AVX512F

Shuffle 128-bit packed single-precision floating-point

VSHUFF32x4 zmm1{k1}{z}, zmm2,

values selected by imm8 from zmm2 and

zmm3/m512/m32bcst, imm8

zmm3/m512/m32bcst and place results in zmm1

subject to writemask k1.

EVEX.256.66.0F3A.W1 23 /r ib

A

V/V

AVX512VL

Shuffle 128-bit packed double precision floating-point

VSHUFF64X2 ymm1{k1}{z}, ymm2,

AVX512F

values selected by imm8 from ymm2 and

ymm3/m256/m64bcst, imm8

ymm3/m256/m64bcst and place results in ymm1

subject to writemask k1.

EVEX.512.66.0F3A.W1 23 /r ib

A

V/V

AVX512F

Shuffle 128-bit packed double precision floating-point

VSHUFF64x2 zmm1{k1}{z}, zmm2,

values selected by imm8 from zmm2 and

zmm3/m512/m64bcst, imm8

zmm3/m512/m64bcst and place results in zmm1

subject to writemask k1.

EVEX.256.66.0F3A.W0 43 /r ib

A

V/V

AVX512VL

Shuffle 128-bit packed double-word values selected by

VSHUFI32X4 ymm1{k1}{z}, ymm2,

AVX512F

imm8 from ymm2 and ymm3/m256/m32bcst and place

ymm3/m256/m32bcst, imm8

results in ymm1 subject to writemask k1.

EVEX.512.66.0F3A.W0 43 /r ib

A

V/V

AVX512F

Shuffle 128-bit packed double-word values selected by

VSHUFI32x4 zmm1{k1}{z}, zmm2,

imm8 from zmm2 and zmm3/m512/m32bcst and place

zmm3/m512/m32bcst, imm8

results in zmm1 subject to writemask k1.

EVEX.256.66.0F3A.W1 43 /r ib

A

V/V

AVX512VL

Shuffle 128-bit packed quad-word values selected by

VSHUFI64X2 ymm1{k1}{z}, ymm2,

AVX512F

imm8 from ymm2 and ymm3/m256/m64bcst and place

ymm3/m256/m64bcst, imm8

results in ymm1 subject to writemask k1.

EVEX.512.66.0F3A.W1 43 /r ib

A

V/V

AVX512F

Shuffle 128-bit packed quad-word values selected by

VSHUFI64x2 zmm1{k1}{z}, zmm2,

imm8 from zmm2 and zmm3/m512/m64bcst and place

zmm3/m512/m64bcst, imm8

results in zmm1 subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

256-bit Version: Moves one of the two 128-bit packed single-precision floating-point values from the first source

operand (second operand) into the low 128-bit of the destination operand (first operand); moves one of the two

packed 128-bit floating-point values from the second source operand (third operand) into the high 128-bit of the

destination operand. The selector operand (third operand) determines which values are moved to the destination

operand.

512-bit Version: Moves two of the four 128-bit packed single-precision floating-point values from the first source

operand (second operand) into the low 256-bit of each double qword of the destination operand (first operand);

moves two of the four packed 128-bit floating-point values from the second source operand (third operand) into

the high 256-bit of the destination operand. The selector operand (third operand) determines which values are

moved to the destination operand.

The first source operand is a vector register. The second source operand can be a ZMM register, a 512-bit memory

location or a 512-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a vector

register.

The writemask updates the destination operand with the granularity of 32/64-bit data elements.

5-700

Vol. 2C

VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-Bit Granularity

INSTRUCTION SET REFERENCE, V

VSQRTPH—Compute Square Root of Packed FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.128.NP.MAP5.W0 51 /r

A

V/V

AVX512-FP16

Compute square roots of the packed FP16 values

VSQRTPH xmm1{k1}{z}, xmm2/m128/

AVX512VL

in xmm2/m128/m16bcst, and store the result in

m16bcst

xmm1 subject to writemask k1.

EVEX.256.NP.MAP5.W0 51 /r

A

V/V

AVX512-FP16

Compute square roots of the packed FP16 values

VSQRTPH ymm1{k1}{z}, ymm2/m256/

AVX512VL

in ymm2/m256/m16bcst, and store the result in

m16bcst

ymm1 subject to writemask k1.

EVEX.512.NP.MAP5.W0 51 /r

A

V/V

AVX512-FP16

Compute square roots of the packed FP16 values

VSQRTPH zmm1{k1}{z}, zmm2/m512/

in zmm2/m512/m16bcst, and store the result in

m16bcst {er}

zmm1 subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

This instruction performs a packed FP16 square-root computation on the values from source operand and stores

the packed FP16 result in the destination operand. The destination elements are updated according to the

writemask.

Operation

VSQRTPH dest{k1}, src

VL = 128, 256 or 512

KL := VL/16

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

IF SRC is memory and (EVEX.b = 1):

tsrc := src.fp16[0]

ELSE:

tsrc := src.fp16[i]

DEST.fp16[i] := SQRT(tsrc)

ELSE IF *zeroing*:

DEST.fp16[i] := 0

//else DEST.fp16[i] remains unchanged

DEST[MAXVL-1:VL] := 0

VSQRTPH—Compute Square Root of Packed FP16 Values

Vol. 2C

5-705

INSTRUCTION SET REFERENCE, V

VSQRTSH—Compute Square Root of Scalar FP16 Value

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.LLIG.F3.MAP5.W0 51 /r

A

V/V

AVX512-FP16

Compute square root of the low FP16 value in

VSQRTSH xmm1{k1}{z}, xmm2,

xmm3/m16 and store the result in xmm1 subject

xmm3/m16 {er}

to writemask k1. Bits 127:16 from xmm2 are

copied to xmm1[127:16].

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction performs a scalar FP16 square-root computation on the source operand and stores the FP16 result

in the destination operand. Bits 127:16 of the destination operand are copied from the corresponding bits of the

first source operand. Bits MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the desti-

nation is updated according to the writemask.

Operation

VSQRTSH dest{k1}, src1, src2

IF k1[0] or *no writemask*:

DEST.fp16[0] := SQRT(src2.fp16[0])

ELSE IF *zeroing*:

DEST.fp16[0] := 0

//else DEST.fp16[0] remains unchanged

DEST[127:16] := src1[127:16]

DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VSQRTSH __m128h _mm_mask_sqrt_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, const int rounding);

VSQRTSH __m128h _mm_maskz_sqrt_round_sh (__mmask8 k, __m128h a, __m128h b, const int rounding);

VSQRTSH __m128h _mm_sqrt_round_sh (__m128h a, __m128h b, const int rounding);

VSQRTSH __m128h _mm_mask_sqrt_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);

VSQRTSH __m128h _mm_maskz_sqrt_sh (__mmask8 k, __m128h a, __m128h b);

VSQRTSH __m128h _mm_sqrt_sh (__m128h a, __m128h b);

SIMD Floating-Point Exceptions

Invalid, Precision, Denormal

Other Exceptions

EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”

VSQRTSH—Compute Square Root of Scalar FP16 Value

Vol. 2C

5-707

INSTRUCTION SET REFERENCE, V

VSUBPH—Subtract Packed FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.128.NP.MAP5.W0 5C /r

A

V/V

AVX512-FP16

Subtract packed FP16 values from xmm3/m128/

VSUBPH xmm1{k1}{z}, xmm2, xmm3/

AVX512VL

m16bcst to xmm2, and store the result in xmm1

m128/m16bcst

subject to writemask k1.

EVEX.256.NP.MAP5.W0 5C /r

A

V/V

AVX512-FP16

Subtract packed FP16 values from ymm3/m256/

VSUBPH ymm1{k1}{z}, ymm2, ymm3/

AVX512VL

m16bcst to ymm2, and store the result in ymm1

m256/m16bcst

subject to writemask k1.

EVEX.512.NP.MAP5.W0 5C /r

A

V/V

AVX512-FP16

Subtract packed FP16 values from zmm3/m512/

VSUBPH zmm1{k1}{z}, zmm2, zmm3/

m16bcst to zmm2, and store the result in zmm1

m512/m16bcst {er}

subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction subtracts packed FP16 values from second source operand from the corresponding elements in the

first source operand, storing the packed FP16 result in the destination operand. The destination elements are

updated according to the writemask.

Operation

VSUBPH (EVEX encoded versions) when src2 operand is a register

VL = 128, 256 or 512

KL := VL/16

IF (VL = 512) AND (EVEX.b = 1):

SET_RM(EVEX.RC)

ELSE

SET_RM(MXCSR.RC)

FOR j := 0 TO KL-1:

IF k1[j] OR *no writemask*:

DEST.fp16[j] := SRC1.fp16[j] - SRC2.fp16[j]

ELSE IF *zeroing*:

DEST.fp16[j] := 0

// else dest.fp16[j] remains unchanged

DEST[MAXVL-1:VL] := 0

5-708

Vol. 2C

VSUBPH—Subtract Packed FP16 Values

INSTRUCTION SET REFERENCE, V

VSUBSH—Subtract Scalar FP16 Value

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.LLIG.F3.MAP5.W0 5C /r

A

V/V

AVX512-FP16

Subtract the low FP16 value in xmm3/m16 from

VSUBSH xmm1{k1}{z}, xmm2,

xmm2 and store the result in xmm1 subject to

xmm3/m16 {er}

writemask k1. Bits 127:16 from xmm2 are

copied to xmm1[127:16].

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction subtracts the low FP16 value from the second source operand from the corresponding value in the

first source operand, storing the FP16 result in the destination operand. Bits 127:16 of the destination operand are

copied from the corresponding bits of the first source operand. Bits MAXVL-1:128 of the destination operand are

zeroed. The low FP16 element of the destination is updated according to the writemask.

Operation

VSUBSH (EVEX encoded versions)

IF EVEX.b = 1 and SRC2 is a register:

SET_RM(EVEX.RC)

ELSE

SET_RM(MXCSR.RC)

IF k1[0] OR *no writemask*:

DEST.fp16[0] := SRC1.fp16[0] - SRC2.fp16[0]

ELSE IF *zeroing*:

DEST.fp16[0] := 0

// else dest.fp16[0] remains unchanged

DEST[127:16] := SRC1[127:16]

DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VSUBSH __m128h _mm_mask_sub_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int rounding);

VSUBSH __m128h _mm_maskz_sub_round_sh (__mmask8 k, __m128h a, __m128h b, int rounding);

VSUBSH __m128h _mm_sub_round_sh (__m128h a, __m128h b, int rounding);

VSUBSH __m128h _mm_mask_sub_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);

VSUBSH __m128h _mm_maskz_sub_sh (__mmask8 k, __m128h a, __m128h b);

VSUBSH __m128h _mm_sub_sh (__m128h a, __m128h b);

SIMD Floating-Point Exceptions

Invalid, Underflow, Overflow, Precision, Denormal

Other Exceptions

EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”

5-710

Vol. 2C

VSUBSH—Subtract Scalar FP16 Value

INSTRUCTION SET REFERENCE, V

VTESTPD/VTESTPS—Packed Bit Test

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature

Support

Flag

VEX.128.66.0F38.W0 0E /r

RM

V/V

AVX

Set ZF and CF depending on sign bit AND and

VTESTPS xmm1, xmm2/m128

ANDN of packed single-precision floating-point

sources.

VEX.256.66.0F38.W0 0E /r

RM

V/V

AVX

Set ZF and CF depending on sign bit AND and

VTESTPS ymm1, ymm2/m256

ANDN of packed single-precision floating-point

sources.

VEX.128.66.0F38.W0 0F /r

RM

V/V

AVX

Set ZF and CF depending on sign bit AND and

VTESTPD xmm1, xmm2/m128

ANDN of packed double precision floating-point

sources.

VEX.256.66.0F38.W0 0F /r

RM

V/V

AVX

Set ZF and CF depending on sign bit AND and

VTESTPD ymm1, ymm2/m256

ANDN of packed double precision floating-point

sources.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (r)

ModRM:r/m (r)

N/A

N/A

Description

VTESTPS performs a bitwise comparison of all the sign bits of the packed single-precision elements in the first

source operation and corresponding sign bits in the second source operand. If the AND of the source sign bits with

the dest sign bits produces all zeros, the ZF is set else the ZF is clear. If the AND of the source sign bits with the

inverted dest sign bits produces all zeros the CF is set else the CF is clear. An attempt to execute VTESTPS with

VEX.W=1 will cause #UD.

VTESTPD performs a bitwise comparison of all the sign bits of the double precision elements in the first source

operation and corresponding sign bits in the second source operand. If the AND of the source sign bits with the dest

sign bits produces all zeros, the ZF is set else the ZF is clear. If the AND the source sign bits with the inverted dest

sign bits produces all zeros the CF is set else the CF is clear. An attempt to execute VTESTPS with VEX.W=1 will

cause #UD.

The first source register is specified by the ModR/M reg field.

128-bit version: The first source register is an XMM register. The second source register can be an XMM register or

a 128-bit memory location. The destination register is not modified.

VEX.256 encoded version: The first source register is a YMM register. The second source register can be a YMM

register or a 256-bit memory location. The destination register is not modified.

Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

VTESTPD/VTESTPS—Packed Bit Test

Vol. 2C

5-711

INSTRUCTION SET REFERENCE, V

VUCOMISH—Unordered Compare Scalar FP16 Values and Set EFLAGS

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.LLIG.NP.MAP5.W0 2E /r

A

V/V

AVX512-FP16

Compare low FP16 values in xmm1 and xmm2/

VUCOMISH xmm1, xmm2/m16 {sae}

m16 and set the EFLAGS flags accordingly.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Scalar

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

This instruction compares the FP16 values in the low word of operand 1 (first operand) and operand 2 (second

operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered, greater than,

less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result is returned

if either source operand is a NaN (QNaN or SNaN).

Operand 1 is an XMM register; operand 2 can be an XMM register or a 16-bit memory location.

The VUCOMISH instruction differs from the VCOMISH instruction in that it signals a SIMD floating-point invalid oper-

ation exception (#I) only if a source operand is an SNaN. The COMISS instruction signals an invalid numeric excep-

tion when a source operand is either a QNaN or SNaN.

The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated. EVEX.vvvv are

reserved and must be 1111b, otherwise instructions will #UD.

Operation

VUCOMISH

RESULT := UnorderedCompare(SRC1.fp16[0],SRC2.fp16[0])

if RESULT is UNORDERED:

ZF, PF, CF := 1, 1, 1

else if RESULT is GREATER_THAN:

ZF, PF, CF := 0, 0, 0

else if RESULT is LESS_THAN:

ZF, PF, CF := 0, 0, 1

else: // RESULT is EQUALS

ZF, PF, CF := 1, 0, 0

OF, AF, SF := 0, 0, 0

Intel C/C++ Compiler Intrinsic Equivalent

VUCOMISH int _mm_ucomieq_sh (__m128h a, __m128h b);

VUCOMISH int _mm_ucomige_sh (__m128h a, __m128h b);

VUCOMISH int _mm_ucomigt_sh (__m128h a, __m128h b);

VUCOMISH int _mm_ucomile_sh (__m128h a, __m128h b);

VUCOMISH int _mm_ucomilt_sh (__m128h a, __m128h b);

VUCOMISH int _mm_ucomineq_sh (__m128h a, __m128h b);

SIMD Floating-Point Exceptions

Invalid, Denormal

Other Exceptions

EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”

5-714

Vol. 2C

VUCOMISH—Unordered Compare Scalar FP16 Values and Set EFLAGS

INSTRUCTION SET REFERENCE, V

VZEROALL—Zero XMM, YMM, and ZMM Registers

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature

Support

Flag

VEX.256.0F.WIG 77

ZO

V/V

AVX

Zero some of the XMM, YMM, and ZMM

registers.

VZEROALL

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

Description

In 64-bit mode, the instruction zeroes XMM0-XMM15, YMM0-YMM15, and ZMM0-ZMM15. Outside 64-bit mode, it

zeroes only XMM0-XMM7, YMM0-YMM7, and ZMM0-ZMM7. VZEROALL does not modify ZMM16-ZMM31.

Note: VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD. In Compatibility and legacy 32-bit

mode only the lower 8 registers are modified.

Operation

simd_reg_file[][] is a two dimensional array representing the SIMD register file containing all the overlapping xmm, ymm, and zmm

registers present in that implementation. The major dimension is the register number: 0 for xmm0, ymm0, and zmm0; 1 for xmm1,

ymm1, and zmm1; etc. The minor dimension size is the width of the implemented SIMD state measured in bits. On a machine

supporting Intel AVX-512, the width is 512.

VZEROALL (VEX.256 encoded version)

IF (64-bit mode)

limit :=15

ELSE

limit := 7

FOR i in 0 .. limit:

simd_reg_file[i][MAXVL-1:0] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VZEROALL:

_mm256_zeroall()

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-25, “Type 8 Class Exception Conditions.”

VZEROALL—Zero XMM, YMM, and ZMM Registers

Vol. 2C

5-715

INSTRUCTION SET REFERENCE, V

VZEROUPPER—Zero Upper Bits of YMM and ZMM Registers

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature

Support

Flag

VEX.128.0F.WIG 77

ZO

V/V

AVX

Zero bits in positions 128 and higher of some

YMM and ZMM registers.

VZEROUPPER

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

Description

In 64-bit mode, the instruction zeroes the bits in positions 128 and higher in YMM0-YMM15 and ZMM0-ZMM15.

Outside 64-bit mode, it zeroes those bits only in YMM0-YMM7 and ZMM0-ZMM7. VZEROUPPER does not modify the

lower 128 bits of these registers and it does not modify ZMM16-ZMM31.

This instruction is recommended when transitioning between AVX and legacy SSE code; it will eliminate perfor-

mance penalties caused by false dependencies.

Note: VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD. In Compatibility and legacy 32-bit

mode only the lower 8 registers are modified.

Operation

simd_reg_file[][] is a two dimensional array representing the SIMD register file containing all the overlapping xmm, ymm, and zmm

registers present in that implementation. The major dimension is the register number: 0 for xmm0, ymm0, and zmm0; 1 for xmm1,

ymm1, and zmm1; etc. The minor dimension size is the width of the implemented SIMD state measured in bits.

VZEROUPPER

IF (64-bit mode)

limit :=15

ELSE

limit := 7

FOR i in 0 .. limit:

simd_reg_file[i][MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VZEROUPPER:

_mm256_zeroupper()

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-25, “Type 8 Class Exception Conditions.”

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VZEROUPPER—Zero Upper Bits of YMM and ZMM Registers

CHAPTER 6

INSTRUCTION SET REFERENCE, W-Z

6.1

INSTRUCTIONS (W-Z)

Chapter 6 continues an alphabetical discussion of Intel^® 64 and IA-32 instructions (W-Z). See also: Chapter 3,

“Instruction Set Reference, A-L,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume

2A; Chapter 4, “Instruction Set Reference, M-U‚” in the Intel® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 2B; and Chapter 5, “Instruction Set Reference, V‚” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2D.

Vol. 2D

6-1

INSTRUCTION SET REFERENCE, W-Z

WAIT/FWAIT—Wait

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

9B

WAIT

ZO

Valid

Valid

Check pending unmasked floating-point

exceptions.

9B

FWAIT

ZO

Valid

Valid

Check pending unmasked floating-point

exceptions.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

Description

Causes the processor to check for and handle pending, unmasked, floating-point exceptions before proceeding.

(FWAIT is an alternate mnemonic for WAIT.)

This instruction is useful for synchronizing exceptions in critical sections of code. Coding a WAIT instruction after a

floating-point instruction ensures that any unmasked floating-point exceptions the instruction may raise are

handled before the processor can modify the instruction’s results. See the section titled “Floating-Point Exception

Synchronization” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1,

for more information on using the WAIT/FWAIT instruction.

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

CheckForPendingUnmaskedFloatingPointExceptions;

FPU Flags Affected

The C0, C1, C2, and C3 flags are undefined.

Floating-Point Exceptions

None.

Protected Mode Exceptions

#NM

If CR0.MP[bit 1] = 1 and CR0.TS[bit 3] = 1.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as in protected mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

Same exceptions as in protected mode.

6-2

Vol. 2D

WAIT/FWAIT—Wait

INSTRUCTION SET REFERENCE, W-Z

WBINVD—Write Back and Invalidate Cache

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

0F 09

WBINVD

ZO

Valid

Valid

Write back and flush Internal caches; initiate

writing-back and flushing of external caches.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

Description

Writes back all modified cache lines in the processor’s internal cache to main memory and invalidates (flushes) the

internal caches. The instruction then issues a special-function bus cycle that directs external caches to also write

back modified data and another bus cycle to indicate that the external caches should be invalidated.

After executing this instruction, the processor does not wait for the external caches to complete their write-back

and flushing operations before proceeding with instruction execution. It is the responsibility of hardware to respond

to the cache write-back and flush signals. The amount of time or cycles for WBINVD to complete will vary due to

size and other factors of different cache hierarchies. As a consequence, the use of the WBINVD instruction can have

an impact on logical processor interrupt/event response time. Additional information of WBINVD behavior in a

cache hierarchy with hierarchical sharing topology can be found in Chapter 2 of the Intel® 64 and IA-32 Architec-

tures Software Developer’s Manual, Volume 3A.

The WBINVD instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a

program or procedure must be 0 to execute this instruction. This instruction is also a serializing instruction (see

“Serializing Instructions” in Chapter 9 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 3A).

In situations where cache coherency with main memory is not a concern, software can use the INVD instruction.

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

IA-32 Architecture Compatibility

The WBINVD instruction is implementation dependent, and its function may be implemented differently on future

Intel 64 and IA-32 processors. The instruction is not supported on IA-32 processors earlier than the Intel486

processor.

Operation

WriteBack(InternalCaches);

Flush(InternalCaches);

SignalWriteBack(ExternalCaches);

SignalFlush(ExternalCaches);

Continue; (* Continue execution *)

Intel C/C++ Compiler Intrinsic Equivalent

WBINVD void _wbinvd(void);

Flags Affected

None.

Protected Mode Exceptions

#GP(0)

If the current privilege level is not 0.

#UD

If the LOCK prefix is used.

WBINVD—Write Back and Invalidate Cache

Vol. 2D

6-3

INSTRUCTION SET REFERENCE, W-Z

WBNOINVD—Write Back and Do Not Invalidate Cache

Opcode /

Op/

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature

Support

Flag

F3 0F 09

ZO

V/V

WBNOINVD

Write back and do not flush internal caches;

initiate writing-back without flushing of external

WBNOINVD

caches.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

N/A

Description

The WBNOINVD instruction writes back all modified cache lines in the processor’s internal cache to main memory

but does not invalidate (flush) the internal caches.

After executing this instruction, the processor does not wait for the external caches to complete their write-back

operation before proceeding with instruction execution. It is the responsibility of hardware to respond to the cache

write-back signal. The amount of time or cycles for WBNOINVD to complete will vary due to size and other factors

of different cache hierarchies. As a consequence, the use of the WBNOINVD instruction can have an impact on

logical processor interrupt/event response time.

The WBNOINVD instruction is a privileged instruction. When the processor is running in protected mode, the CPL of

a program or procedure must be 0 to execute this instruction. This instruction is also a serializing instruction (see

“Serializing Instructions” in Chapter 9 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,

Volume 3A).

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

WriteBack(InternalCaches);

Continue; (* Continue execution *)

Intel C/C++ Compiler Intrinsic Equivalent

WBNOINVD void _wbnoinvd(void);

Flags Affected

None.

Protected Mode Exceptions

#GP(0)

If the current privilege level is not 0.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

#UD

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#GP(0)

WBNOINVD cannot be executed at the virtual-8086 mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

WBNOINVD—Write Back and Do Not Invalidate Cache

Vol. 2D

6-5

INSTRUCTION SET REFERENCE, W-Z

WRFSBASE/WRGSBASE—Write FS/GS Segment Base

Opcode/

Op/

64/32-

CPUID Fea-

Description

Instruction

En

bit

ture Flag

Mode

F3 0F AE /2

M

V/I

FSGSBASE

Load the FS base address with the 32-bit value in the

WRFSBASE r32

source register.

F3 REX.W 0F AE /2

M

V/I

FSGSBASE

Load the FS base address with the 64-bit value in the

WRFSBASE r64

source register.

F3 0F AE /3

M

V/I

FSGSBASE

Load the GS base address with the 32-bit value in the

WRGSBASE r32

source register.

F3 REX.W 0F AE /3

M

V/I

FSGSBASE

Load the GS base address with the 64-bit value in the

WRGSBASE r64

source register.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

M

ModRM:r/m (r)

N/A

N/A

N/A

Description

Loads the FS or GS segment base address with the general-purpose register indicated by the modR/M:r/m field.

The source operand may be either a 32-bit or a 64-bit general-purpose register. The REX.W prefix indicates the

operand size is 64 bits. If no REX.W prefix is used, the operand size is 32 bits; the upper 32 bits of the source

register are ignored and upper 32 bits of the base address (for FS or GS) are cleared.

This instruction is supported only in 64-bit mode.

Operation

FS/GS segment base address := SRC;

Flags Affected

None

C/C++ Compiler Intrinsic Equivalent

WRFSBASE:

void _writefsbase_u32( unsigned int );

WRFSBASE:

_writefsbase_u64( unsigned __int64 );

WRGSBASE:

void _writegsbase_u32( unsigned int );

WRGSBASE:

_writegsbase_u64( unsigned __int64 );

Protected Mode Exceptions

#UD

The WRFSBASE and WRGSBASE instructions are not recognized in protected mode.

Real-Address Mode Exceptions

#UD

The WRFSBASE and WRGSBASE instructions are not recognized in real-address mode.

Virtual-8086 Mode Exceptions

#UD

The WRFSBASE and WRGSBASE instructions are not recognized in virtual-8086 mode.

Compatibility Mode Exceptions

#UD

The WRFSBASE and WRGSBASE instructions are not recognized in compatibility mode.

WRFSBASE/WRGSBASE—Write FS/GS Segment Base

Vol. 2D

6-7

INSTRUCTION SET REFERENCE, W-Z

WRMSR—Write to Model Specific Register

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

0F 30

WRMSR

ZO

Valid

Valid

Write the value in EDX:EAX to MSR specified

by ECX.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

Description

Writes the contents of registers EDX:EAX into the 64-bit model specific register (MSR) specified in the ECX register.

(On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The contents of

the EDX register are copied to high-order 32 bits of the selected MSR and the contents of the EAX register are

copied to low-order 32 bits of the MSR. (On processors that support the Intel 64 architecture, the high-order 32

bits of each of RAX and RDX are ignored.) Undefined or reserved bits in an MSR should be set to values previously

read.

This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection

exception #GP(0) is generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a

general protection exception. The processor will also generate a general protection exception if software attempts

to write to bits in a reserved MSR.

When the WRMSR instruction is used to write to an MTRR, the TLBs are invalidated. This includes global entries

(see “Translation Lookaside Buffers (TLBs)” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Devel-

oper’s Manual, Volume 3A).

MSRs control functions for testability, execution tracing, performance-monitoring and machine check errors.

Chapter 2, “Model-Specific Registers (MSRs),” of the Intel® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 4, lists all MSRs that can be written with this instruction and their addresses. Note that each

processor family has its own set of MSRs.

The WRMSR instruction is a serializing instruction (see “Serializing Instructions” in Chapter 9 of the Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A). Note that WRMSR to the IA32_TSC_DEADLINE

MSR (MSR index 6E0H) and the X2APIC MSRs (MSR indices 802H to 83FH) are not serializing.

The CPUID instruction should be used to determine whether MSRs are supported (CPUID.01H:EDX[5] = 1) before

using this instruction.

IA-32 Architecture Compatibility

The MSRs and the ability to read them with the WRMSR instruction were introduced into the IA-32 architecture with

the Pentium processor. Execution of this instruction by an IA-32 processor earlier than the Pentium processor

results in an invalid opcode exception #UD.

Operation

MSR[ECX] := EDX:EAX;

Flags Affected

None.

WRMSR—Write to Model Specific Register

Vol. 2D

6-9

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