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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 105

INSTRUCTION SET REFERENCE, V

VRANGESS—Range Restriction Calculation From a Pair of Scalar Float32 Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F3A.W0 51 /r

A

V/V

AVX512DQ

Calculate a RANGE operation output value from 2 single-

VRANGESS xmm1 {k1}{z},

precision floating-point values in xmm2 and xmm3/m32,

xmm2, xmm3/m32{sae}, imm8

store the output to xmm1 under writemask. Imm8 specifies

the comparison and sign of the range operation.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction calculates a range operation output from two input single-precision floating-point values in the low

dword element of the first source operand (the second operand) and second source operand (the third operand).

The range output is written to the low dword element of the destination operand (the first operand) under the

writemask k1.

Bits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a

two-bit control field within imm8[3:0]:

• Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min

absolute value of the input value pair. Each comparison of two input values produces an intermediate result that

combines with the sign selection control (imm8[3:2]) to determine the final range operation output.

• Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input

value, from the comparison result, set or clear.

The encodings of imm8[1:0] and imm8[3:2] are shown in Figure 5-27.

Bits 128:31 of the destination operand are copied from the respective elements of the first source operand.

When one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details

with one of more input value is NAN is listed in Table 5-13. If the comparison raises an IE, the sign select control

(imm8[3:2]) has no effect to the range operation output; this is indicated also in Table 5-13.

When both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare

operation is slightly different from the conceptually similar floating-point MIN/MAX operation that are found in the

instructions VMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS

for magnitude-0, opposite-signed input cases are listed in Table 5-14.

Additionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS compar-

ison operation with result listed in Table 5-15.

5-628

Vol. 2C

VRANGESS—Range Restriction Calculation From a Pair of Scalar Float32 Values

INSTRUCTION SET REFERENCE, V

VRCP14PD—Compute Approximate Reciprocals of Packed Float64 Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.128.66.0F38.W1 4C /r

A

V/V

AVX512VL

Computes the approximate reciprocals of the packed double

VRCP14PD xmm1 {k1}{z},

AVX512F

precision floating-point values in xmm2/m128/m64bcst and

xmm2/m128/m64bcst

stores the results in xmm1. Under writemask.

EVEX.256.66.0F38.W1 4C /r

A

V/V

AVX512VL

Computes the approximate reciprocals of the packed double

VRCP14PD ymm1 {k1}{z},

AVX512F

precision floating-point values in ymm2/m256/m64bcst and

ymm2/m256/m64bcst

stores the results in ymm1. Under writemask.

EVEX.512.66.0F38.W1 4C /r

A

V/V

AVX512F

Computes the approximate reciprocals of the packed double

VRCP14PD zmm1 {k1}{z},

precision floating-point values in zmm2/m512/m64bcst and

zmm2/m512/m64bcst

stores the results in zmm1. Under writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

This instruction performs a SIMD computation of the approximate reciprocals of eight/four/two packed double

precision floating-point values in the source operand (the second operand) and stores the packed double precision

floating-point results in the destination operand. The maximum relative error for this approximation is less than 2^-

¹⁴.

The source operand can be a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-

bit memory location. The destination operand is a ZMM register conditionally updated according to the writemask.

The VRCP14PD instruction is not affected by the rounding control bits in the MXCSR register. When a source value

is a 0.0, an ∞ with the sign of the source value is returned. A denormal source value will be treated as zero only in

case of DAZ bit set in MXCSR. Otherwise it is treated correctly (i.e., not as a 0.0). Underflow results are flushed to

zero only in case of FTZ bit set in MXCSR. Otherwise it will be treated correctly (i.e., correct underflow result is

written) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN

or the source QNaN is returned.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.

Table 5-16. VRCP14PD/VRCP14SD Special Cases

Input value

Result value

Comments

0 ≤ X ≤ 2^-1024

INF

Very small denormal

-2^-1024 ≤ X ≤ -0

-INF

Very small denormal

X > 2¹⁰²²

Underflow

Up to 18 bits of fractions are returned*

X < -2¹⁰²²

-Underflow

Up to 18 bits of fractions are returned*

X = 2^-n

2ⁿ

X = -2^-n

-2ⁿ

* in this case the mantissa is shifted right by one or two bits

A numerically exact implementation of VRCP14xx can be found at https://software.intel.com/en-us/articles/refer-

ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

VRCP14PD—Compute Approximate Reciprocals of Packed Float64 Values

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5-631

INSTRUCTION SET REFERENCE, V

VRCP14SD—Compute Approximate Reciprocal of Scalar Float64 Value

Opcode/

Op

64/32

CPUID

Description

Instruction

/ En

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F38.W1 4D /r

A

V/V

AVX512F

Computes the approximate reciprocal of the scalar double

VRCP14SD xmm1 {k1}{z}, xmm2,

precision floating-point value in xmm3/m64 and stores the

xmm3/m64

result in xmm1 using writemask k1. Also, upper double

precision floating-point value (bits[127:64]) from xmm2 is

copied to xmm1[127:64].

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction performs a SIMD computation of the approximate reciprocal of the low double precision floating-

point value in the second source operand (the third operand) stores the result in the low quadword element of the

destination operand (the first operand) according to the writemask k1. Bits (127:64) of the XMM register destina-

tion are copied from corresponding bits in the first source operand (the second operand). The maximum relative

error for this approximation is less than 2^-14. The source operand can be an XMM register or a 64-bit memory loca-

tion. The destination operand is an XMM register.

The VRCP14SD instruction is not affected by the rounding control bits in the MXCSR register. When a source value

is a 0.0, an ∞ with the sign of the source value is returned. A denormal source value will be treated as zero only in

case of DAZ bit set in MXCSR. Otherwise it is treated correctly (i.e., not as a 0.0). Underflow results are flushed to

zero only in case of FTZ bit set in MXCSR. Otherwise it will be treated correctly (i.e., correct underflow result is

written) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN

or the source QNaN is returned. See Table 5-16 for special-case input values.

MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.

A numerically exact implementation of VRCP14xx can be found at:

https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-

vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRCP14SD (EVEX version)

IF k1[0] OR *no writemask*

THEN DEST[63:0] := APPROXIMATE(1.0/SRC2[63:0]);

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[63:0] remains unchanged*

ELSE

; zeroing-masking

DEST[63:0] := 0

FI;

FI;

DEST[127:64] := SRC1[127:64]

DEST[MAXVL-1:128] := 0

VRCP14SD—Compute Approximate Reciprocal of Scalar Float64 Value

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5-633

INSTRUCTION SET REFERENCE, V

VRCP14PS—Compute Approximate Reciprocals of Packed Float32 Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.128.66.0F38.W0 4C /r

A

V/V

AVX512VL

Computes the approximate reciprocals of the packed single-

VRCP14PS xmm1 {k1}{z},

AVX512F

precision floating-point values in xmm2/m128/m32bcst and

xmm2/m128/m32bcst

stores the results in xmm1. Under writemask.

EVEX.256.66.0F38.W0 4C /r

A

V/V

AVX512VL

Computes the approximate reciprocals of the packed single-

VRCP14PS ymm1 {k1}{z},

AVX512F

precision floating-point values in ymm2/m256/m32bcst and

ymm2/m256/m32bcst

stores the results in ymm1. Under writemask.

EVEX.512.66.0F38.W0 4C /r

A

V/V

AVX512F

Computes the approximate reciprocals of the packed single-

VRCP14PS zmm1 {k1}{z},

precision floating-point values in zmm2/m512/m32bcst and

zmm2/m512/m32bcst

stores the results in zmm1. Under writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

This instruction performs a SIMD computation of the approximate reciprocals of the packed single-precision

floating-point values in the source operand (the second operand) and stores the packed single-precision floating-

point results in the destination operand (the first operand). The maximum relative error for this approximation is

less than 2^-14.

The source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32-

bit memory location. The destination operand is a ZMM register conditionally updated according to the writemask.

The VRCP14PS instruction is not affected by the rounding control bits in the MXCSR register. When a source value

is a 0.0, an ∞ with the sign of the source value is returned. A denormal source value will be treated as zero only in

case of DAZ bit set in MXCSR. Otherwise it is treated correctly (i.e., not as a 0.0). Underflow results are flushed to

zero only in case of FTZ bit set in MXCSR. Otherwise it will be treated correctly (i.e., correct underflow result is

written) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN

or the source QNaN is returned.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.

Table 5-17. VRCP14PS/VRCP14SS Special Cases

Input value

Result value

Comments

0 ≤ X ≤ 2^-128

INF

Very small denormal

-2^-128 ≤ X ≤ -0

-INF

Very small denormal

X > 2¹²⁶

Underflow

Up to 18 bits of fractions are returned¹

X < -2¹²⁶

-Underflow

Up to 18 bits of fractions are returned¹

X = 2^-n

2ⁿ

X = -2^-n

-2ⁿ

NOTES:

1. In this case, the mantissa is shifted right by one or two bits.

A numerically exact implementation of VRCP14xx can be found at:

https://software.intel.com/en-us/articles/reference-implementations-for-IA-approximation-instructions-vrcp14-

vrsqrt14-vrcp28-vrsqrt28-vexp2.

VRCP14PS—Compute Approximate Reciprocals of Packed Float32 Values

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INSTRUCTION SET REFERENCE, V

VRCP14SS—Compute Approximate Reciprocal of Scalar Float32 Value

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F38.W0 4D /r

A

V/V

AVX512F

Computes the approximate reciprocal of the scalar single-

VRCP14SS xmm1 {k1}{z}, xmm2,

precision floating-point value in xmm3/m32 and stores the

xmm3/m32

results in xmm1 using writemask k1. Also, upper double

precision floating-point value (bits[127:32]) from xmm2 is

copied to xmm1[127:32].

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction performs a SIMD computation of the approximate reciprocal of the low single-precision floating-

point value in the second source operand (the third operand) and stores the result in the low quadword element of

the destination operand (the first operand) according to the writemask k1. Bits (127:32) of the XMM register desti-

nation are copied from corresponding bits in the first source operand (the second operand). The maximum relative

error for this approximation is less than 2^-14. The source operand can be an XMM register or a 32-bit memory loca-

tion. The destination operand is an XMM register.

The VRCP14SS instruction is not affected by the rounding control bits in the MXCSR register. When a source value

is a 0.0, an ∞ with the sign of the source value is returned. A denormal source value will be treated as zero only in

case of DAZ bit set in MXCSR. Otherwise it is treated correctly (i.e., not as a 0.0). Underflow results are flushed to

zero only in case of FTZ bit set in MXCSR. Otherwise it will be treated correctly (i.e., correct underflow result is

written) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN

or the source QNaN is returned. See Table 5-17 for special-case input values.

MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.

A numerically exact implementation of VRCP14xx can be found at https://software.intel.com/en-us/articles/refer-

ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRCP14SS (EVEX version)

IF k1[0] OR *no writemask*

THEN DEST[31:0] := APPROXIMATE(1.0/SRC2[31:0]);

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[31:0] remains unchanged*

ELSE

; zeroing-masking

DEST[31:0] := 0

FI;

FI;

DEST[127:32] := SRC1[127:32]

DEST[MAXVL-1:128] := 0

VRCP14SS—Compute Approximate Reciprocal of Scalar Float32 Value

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INSTRUCTION SET REFERENCE, V

VRCPPH—Compute Reciprocals of Packed FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.128.66.MAP6.W0 4C /r

A

V/V

AVX512-FP16

Compute the approximate reciprocals of packed

VRCPPH xmm1{k1}{z}, xmm2/m128/

AVX512VL

FP16 values in xmm2/m128/m16bcst and store

m16bcst

the result in xmm1 subject to writemask k1.

EVEX.256.66.MAP6.W0 4C /r

A

V/V

AVX512-FP16

Compute the approximate reciprocals of packed

VRCPPH ymm1{k1}{z}, ymm2/m256/

AVX512VL

FP16 values in ymm2/m256/m16bcst and store

m16bcst

the result in ymm1 subject to writemask k1.

EVEX.512.66.MAP6.W0 4C /r

A

V/V

AVX512-FP16

Compute the approximate reciprocals of packed

VRCPPH zmm1{k1}{z}, zmm2/m512/

FP16 values in zmm2/m512/m16bcst and store

m16bcst

the result in zmm1 subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

This instruction performs a SIMD computation of the approximate reciprocals of 8/16/32 packed FP16 values in the

source operand (the second operand) and stores the packed FP16 results in the destination operand. The maximum

relative error for this approximation is less than 2⁻¹¹ + 2⁻¹⁴.

For special cases, see Table 5-18.

Table 5-18. VRCPPH/VRCPSH Special Cases

Input Value

Result Value

Comments

0 ≤ X ≤ 2^-16

INF

Very small denormal

−2^-16 ≤ X ≤ -0

−INF

Very small denormal

X > +∞

+0

X < −∞

−0

X = 2^-n

2ⁿ

X = −2^-n

−2ⁿ

Operation

VRCPPH dest{k1}, src

VL = 128, 256 or 512

KL := VL/16

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

IF SRC is memory and (EVEX.b = 1):

tsrc := src.fp16[0]

ELSE:

tsrc := src.fp16[i]

DEST.fp16[i] := APPROXIMATE(1.0 / tsrc)

ELSE IF *zeroing*:

DEST.fp16[i] := 0

//else DEST.fp16[i] remains unchanged

DEST[MAXVL-1:VL] := 0

VRCPPH—Compute Reciprocals of Packed FP16 Values

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INSTRUCTION SET REFERENCE, V

VRCPSH—Compute Reciprocal of Scalar FP16 Value

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.LLIG.66.MAP6.W0 4D /r

A

V/V

AVX512-FP16

Compute the approximate reciprocal of the low

VRCPSH xmm1{k1}{z}, xmm2, xmm3/

FP16 value in xmm3/m16 and store the result in

m16

xmm1 subject to writemask k1. Bits 127:16 from

xmm2 are copied to xmm1[127:16].

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction performs a SIMD computation of the approximate reciprocal of the low FP16 value in the second

source operand (the third operand) and stores the result in the low word element of the destination operand (the

first operand) according to the writemask k1. Bits 127:16 of the XMM register destination are copied from corre-

sponding bits in the first source operand (the second operand). The maximum relative error for this approximation

is less than 2⁻¹¹ + 2⁻¹⁴.

Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits

MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according

to the writemask.

For special cases, see Table 5-18.

Operation

VRCPSH dest{k1}, src1, src2

IF k1[0] or *no writemask*:

DEST.fp16[0] := APPROXIMATE(1.0 / src2.fp16[0])

ELSE IF *zeroing*:

DEST.fp16[0] := 0

//else DEST.fp16[0] remains unchanged

DEST[127:16] := src1[127:16]

DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VRCPSH __m128h _mm_mask_rcp_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);

VRCPSH __m128h _mm_maskz_rcp_sh (__mmask8 k, __m128h a, __m128h b);

VRCPSH __m128h _mm_rcp_sh (__m128h a, __m128h b);

SIMD Floating-Point Exceptions

None.

Other Exceptions

EVEX-encoded instruction, see Table 2-58, “Type E10 Class Exception Conditions.”

VRCPSH—Compute Reciprocal of Scalar FP16 Value

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INSTRUCTION SET REFERENCE, V

VREDUCEPD—Perform Reduction Transformation on Packed Float64 Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.128.66.0F3A.W1 56 /r ib

A

V/V

AVX512VL

Perform reduction transformation on packed double precision

VREDUCEPD xmm1 {k1}{z},

AVX512DQ

floating-point values in xmm2/m128/m32bcst by subtracting

xmm2/m128/m64bcst, imm8

a number of fraction bits specified by the imm8 field. Stores

the result in xmm1 register under writemask k1.

EVEX.256.66.0F3A.W1 56 /r ib

A

V/V

AVX512VL

Perform reduction transformation on packed double precision

VREDUCEPD ymm1 {k1}{z},

AVX512DQ

floating-point values in ymm2/m256/m32bcst by subtracting

ymm2/m256/m64bcst, imm8

a number of fraction bits specified by the imm8 field. Stores

the result in ymm1 register under writemask k1.

EVEX.512.66.0F3A.W1 56 /r ib

A

V/V

AVX512DQ

Perform reduction transformation on double precision

VREDUCEPD zmm1 {k1}{z},

floating-point values in zmm2/m512/m32bcst by subtracting

zmm2/m512/m64bcst{sae},

a number of fraction bits specified by the imm8 field. Stores

imm8

the result in zmm1 register under writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

imm8

N/A

Description

Perform reduction transformation of the packed binary encoded double precision floating-point values in the source

operand (the second operand) and store the reduced results in binary floating-point format to the destination

operand (the first operand) under the writemask k1.

The reduction transformation subtracts the integer part and the leading M fractional bits from the binary floating-

point source value, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduc-

tion transformation can be expressed as:

dest = src - (ROUND(2^M*src))*2^-M;

where “Round()” treats “src”, “2^M”, and their product as binary floating-point numbers with normalized signifi-

cand and biased exponents.

The magnitude of the reduced result can be expressed by considering src= 2^p*man2,

where ‘man2’ is the normalized significand and ‘p’ is the unbiased exponent

Then if RC = RNE: 0<=|Reduced Result|<=2^p-M-1

Then if RC ≠ RNE: 0<=|Reduced Result|<2^p-M

This instruction might end up with a precision exception set. However, in case of SPE set (i.e., Suppress Precision

Exception, which is imm8[3]=1), no precision exception is reported.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

7

6

5

4

3

2

1

0

imm8

Fixed point length

SPE

RS

Round Control Override

Suppress Precision Exception: Imm8[3]

Imm8[1:0] = 00b : Round nearest even

Imm8[3] = 0b : Use MXCSR exception mask

Round Select: Imm8[2]

Imm8[7:4] : Number of fixed points to subtract

Imm8[1:0] = 01b : Round down

Imm8[3] = 1b : Suppress

Imm8[2] = 0b : Use Imm8[1:0]

Imm8[1:0] = 10b : Round up

Imm8[2] = 1b : Use MXCSR

Imm8[1:0] = 11b : Truncate

Figure 5-28. Imm8 Controls for VREDUCEPD/SD/PS/SS

5-642

Vol. 2C

VREDUCEPD—Perform Reduction Transformation on Packed Float64 Values

INSTRUCTION SET REFERENCE, V

Handling of special case of input values are listed in Table 5-19.

Table 5-19. VREDUCEPD/SD/PS/SS Special Cases

Round Mode

Returned value

|Src1| < 2^-M-1

RNE

Src1

RPI, Src1 > 0

Round (Src1-2^-M) *

RPI, Src1 ≤ 0

Src1

RNI, Src1 ≥ 0

Src1

|Src1| < 2^-M

RNI, Src1 < 0

Round (Src1+2^-M) *

NOT RNI

+0.0

Src1 = ±0, or

Dest = ±0 (Src1!=INF)

RNI

-0.0

Src1 = ±INF

any

+0.0

Src1= ±NAN

n/a

QNaN(Src1)

* Round control = (imm8.MS1)? MXCSR.RC: imm8.RC

Operation

ReduceArgumentDP(SRC[63:0], imm8[7:0])

{

// Check for NaN

IF (SRC [63:0] = NAN) THEN

RETURN (Convert SRC[63:0] to QNaN); FI;

M := imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted

RC := imm8[1:0];// Round Control for ROUND() operation

RC source := imm[2];

SPE := imm[3];// Suppress Precision Exception

TMP[63:0] := 2^-M *{ROUND(2^M*SRC[63:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2^M as standard binary FP values

TMP[63:0] := SRC[63:0] - TMP[63:0]; // subtraction under the same RC,SPE controls

RETURN TMP[63:0]; // binary encoded FP with biased exponent and normalized significand

}

VREDUCEPD

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b == 1) AND (SRC *is memory*)

THEN DEST[i+63:i] := ReduceArgumentDP(SRC[63:0], imm8[7:0]);

ELSE DEST[i+63:i] := ReduceArgumentDP(SRC[i+63:i], imm8[7:0]);

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] = 0

FI;

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

VREDUCEPD—Perform Reduction Transformation on Packed Float64 Values

Vol. 2C

5-643

INSTRUCTION SET REFERENCE, V

VREDUCEPH—Perform Reduction Transformation on Packed FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.128.NP.0F3A.W0 56 /r /ib

A

V/V

AVX512-FP16

Perform reduction transformation on packed

VREDUCEPH xmm1{k1}{z}, xmm2/

AVX512VL

FP16 values in xmm2/m128/m16bcst by

m128/m16bcst, imm8

subtracting a number of fraction bits specified by

the imm8 field. Store the result in xmm1 subject

to writemask k1.

EVEX.256.NP.0F3A.W0 56 /r /ib

A

V/V

AVX512-FP16

Perform reduction transformation on packed

VREDUCEPH ymm1{k1}{z}, ymm2/

AVX512VL

FP16 values in ymm2/m256/m16bcst by

m256/m16bcst, imm8

subtracting a number of fraction bits specified by

the imm8 field. Store the result in ymm1 subject

to writemask k1.

EVEX.512.NP.0F3A.W0 56 /r /ib

A

V/V

AVX512-FP16

Perform reduction transformation on packed

VREDUCEPH zmm1{k1}{z}, zmm2/

FP16 values in zmm2/m512/m16bcst by

m512/m16bcst {sae}, imm8

subtracting a number of fraction bits specified by

the imm8 field. Store the result in zmm1 subject

to writemask k1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

imm8 (r)

N/A

Description

This instruction performs a reduction transformation of the packed binary encoded FP16 values in the source

operand (the second operand) and store the reduced results in binary FP format to the destination operand (the

first operand) under the writemask k1.

The reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source

value, where M is a unsigned integer specified by imm8[7:4]. Specifically, the reduction transformation can be

expressed as:

dest = src − (ROUND(2^M * src)) * 2^−M

where ROUND() treats src, 2^M, and their product as binary FP numbers with normalized significand and biased

exponents.

The magnitude of the reduced result can be expressed by considering src = 2^p * man2, where ‘man2’ is the normal-

ized significand and ‘p’ is the unbiased exponent.

Then if RC=RNE: 0 ≤ |ReducedResult| ≤ 2^−M−1.

Then if RC ≠ RNE: 0 ≤ |ReducedResult| < 2^−M.

This instruction might end up with a precision exception set. However, in case of SPE set (i.e., Suppress Precision

Exception, which is imm8[3]=1), no precision exception is reported.

This instruction may generate tiny non-zero result. If it does so, it does not report underflow exception, even if

underflow exceptions are unmasked (UM flag in MXCSR register is 0).

For special cases, see Table 5-20.

VREDUCEPH—Perform Reduction Transformation on Packed FP16 Values

Vol. 2C

5-645

INSTRUCTION SET REFERENCE, V

Table 5-20. VREDUCEPH/VREDUCESH Special Cases

Input value

Round Mode

Returned Value

|Src1| < 2−M−1

RNE

Src1

RU, Src1 > 0

Round(Src1 − 2−M)¹

RU, Src1 ≤ 0

Src1

|Src1| < 2^−M

RD, Src1 ≥ 0

Src1

RD, Src1 < 0

Round(Src1 + 2−M)

NOT RD

+0.0

Src1 = ±0 or

Dest = ±0 (Src1 ≠ ∞)

RD

−0.0

Src1 = ±∞

Any

+0.0

Src1 = ±NAN

Any

QNaN (Src1)

NOTES:

1. The Round(.) function uses rounding controls specified by (imm8[2]? MXCSR.RC: imm8[1:0]).

Operation

def reduce_fp16(src, imm8):

nan := (src.exp = 0x1F) and (src.fraction != 0)

if nan:

return QNAN(src)

m := imm8[7:4]

rc := imm8[1:0]

rc_source := imm8[2]

spe := imm[3] // suppress precision exception

tmp := 2^(-m) * ROUND(2^m * src, spe, rc_source, rc)

tmp := src - tmp // using same RC, SPE controls

return tmp

VREDUCEPH dest{k1}, src, imm8

VL = 128, 256 or 512

KL := VL/16

FOR i := 0 to KL-1:

IF k1[i] or *no writemask*:

IF SRC is memory and (EVEX.b = 1):

tsrc := src.fp16[0]

ELSE:

tsrc := src.fp16[i]

DEST.fp16[i] := reduce_fp16(tsrc, imm8)

ELSE IF *zeroing*:

DEST.fp16[i] := 0

//else DEST.fp16[i] remains unchanged

DEST[MAXVL-1:VL] := 0

5-646

Vol. 2C

VREDUCEPH—Perform Reduction Transformation on Packed FP16 Values

INSTRUCTION SET REFERENCE, V

VREDUCESD—Perform a Reduction Transformation on a Scalar Float64 Value

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

En

Mode

Feature

Support

Flag

EVEX.LLIG.66.0F3A.W1 57

A

V/V

AVX512D

Perform a reduction transformation on a scalar double precision

VREDUCESD xmm1 {k1}{z},

Q

floating-point value in xmm3/m64 by subtracting a number of

xmm2, xmm3/m64{sae},

fraction bits specified by the imm8 field. Also, upper double

imm8/r

precision floating-point value (bits[127:64]) from xmm2 are

copied to xmm1[127:64]. Stores the result in xmm1 register.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Perform a reduction transformation of the binary encoded double precision floating-point value in the low qword

element of the second source operand (the third operand) and store the reduced result in binary floating-point

format to the low qword element of the destination operand (the first operand) under the writemask k1. Bits

127:64 of the destination operand are copied from respective qword elements of the first source operand (the

second operand).

The reduction transformation subtracts the integer part and the leading M fractional bits from the binary floating-

point source value, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduc-

tion transformation can be expressed as:

dest = src - (ROUND(2^M*src))*2^-M;

where “Round()” treats “src”, “2^M”, and their product as binary floating-point numbers with normalized signifi-

cand and biased exponents.

The magnitude of the reduced result can be expressed by considering src= 2^p*man2,

where ‘man2’ is the normalized significand and ‘p’ is the unbiased exponent

Then if RC = RNE: 0<=|Reduced Result|<=2^p-M-1

Then if RC ≠ RNE: 0<=|Reduced Result|<2^p-M

This instruction might end up with a precision exception set. However, in case of SPE set (i.e., Suppress Precision

Exception, which is imm8[3]=1), no precision exception is reported.

The operation is write masked.

Handling of special case of input values are listed in Table 5-19.

Operation

ReduceArgumentDP(SRC[63:0], imm8[7:0])

{

// Check for NaN

IF (SRC [63:0] = NAN) THEN

RETURN (Convert SRC[63:0] to QNaN); FI;

M := imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted

RC := imm8[1:0];// Round Control for ROUND() operation

RC source := imm[2];

SPE := imm[3];// Suppress Precision Exception

TMP[63:0] := 2^-M *{ROUND(2^M*SRC[63:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2^M as standard binary FP values

TMP[63:0] := SRC[63:0] - TMP[63:0]; // subtraction under the same RC,SPE controls

RETURN TMP[63:0]; // binary encoded FP with biased exponent and normalized significand

}

5-648

Vol. 2C

VREDUCESD—Perform a Reduction Transformation on a Scalar Float64 Value

INSTRUCTION SET REFERENCE, V

VREDUCESH—Perform Reduction Transformation on Scalar FP16 Value

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.LLIG.NP.0F3A.W0 57 /r /ib

A

V/V

AVX512-FP16

Perform a reduction transformation on the low

VREDUCESH xmm1{k1}{z}, xmm2,

binary encoded FP16 value in xmm3/m16 by

xmm3/m16 {sae}, imm8

subtracting a number of fraction bits specified by

the imm8 field. Store the result in xmm1 subject

to writemask k1. Bits 127:16 from xmm2 are

copied to xmm1[127:16].

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8 (r)

Description

This instruction performs a reduction transformation of the low binary encoded FP16 value in the source operand

(the second operand) and store the reduced result in binary FP format to the low element of the destination

operand (the first operand) under the writemask k1. For further details see the description of VREDUCEPH.

Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits

MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according

to the writemask.

This instruction might end up with a precision exception set. However, in case of SPE set (i.e., Suppress Precision

Exception, which is imm8[3]=1), no precision exception is reported.

This instruction may generate tiny non-zero result. If it does so, it does not report underflow exception, even if

underflow exceptions are unmasked (UM flag in MXCSR register is 0).

For special cases, see Table 5-20.

Operation

VREDUCESH dest{k1}, src, imm8

IF k1[0] or *no writemask*:

dest.fp16[0] := reduce_fp16(src2.fp16[0], imm8)

// see VREDUCEPH

ELSE IF *zeroing*:

dest.fp16[0] := 0

//else dest.fp16[0] remains unchanged

DEST[127:16] := src1[127:16]

DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VREDUCESH __m128h _mm_mask_reduce_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int imm8, const int sae);

VREDUCESH __m128h _mm_maskz_reduce_round_sh (__mmask8 k, __m128h a, __m128h b, int imm8, const int sae);

VREDUCESH __m128h _mm_reduce_round_sh (__m128h a, __m128h b, int imm8, const int sae);

VREDUCESH __m128h _mm_mask_reduce_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, int imm8);

VREDUCESH __m128h _mm_maskz_reduce_sh (__mmask8 k, __m128h a, __m128h b, int imm8);

VREDUCESH __m128h _mm_reduce_sh (__m128h a, __m128h b, int imm8);

SIMD Floating-Point Exceptions

Invalid, Precision

5-650

Vol. 2C

VREDUCESH—Perform Reduction Transformation on Scalar FP16 Value

INSTRUCTION SET REFERENCE, V

VREDUCEPS—Perform Reduction Transformation on Packed Float32 Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.128.66.0F3A.W0 56 /r ib

A

V/V

AVX512VL

Perform reduction transformation on packed single-precision

VREDUCEPS xmm1 {k1}{z},

AVX512DQ

floating-point values in xmm2/m128/m32bcst by subtracting

xmm2/m128/m32bcst, imm8

a number of fraction bits specified by the imm8 field. Stores

the result in xmm1 register under writemask k1.

EVEX.256.66.0F3A.W0 56 /r ib

A

V/V

AVX512VL

Perform reduction transformation on packed single-precision

VREDUCEPS ymm1 {k1}{z},

AVX512DQ

floating-point values in ymm2/m256/m32bcst by subtracting

ymm2/m256/m32bcst, imm8

a number of fraction bits specified by the imm8 field. Stores

the result in ymm1 register under writemask k1.

EVEX.512.66.0F3A.W0 56 /r ib

A

V/V

AVX512DQ

Perform reduction transformation on packed single-precision

VREDUCEPS zmm1 {k1}{z},

floating-point values in zmm2/m512/m32bcst by subtracting

zmm2/m512/m32bcst{sae},

a number of fraction bits specified by the imm8 field. Stores

imm8

the result in zmm1 register under writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

imm8

N/A

Description

Perform reduction transformation of the packed binary encoded single-precision floating-point values in the source

operand (the second operand) and store the reduced results in binary floating-point format to the destination

operand (the first operand) under the writemask k1.

The reduction transformation subtracts the integer part and the leading M fractional bits from the binary floating-

point source value, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduc-

tion transformation can be expressed as:

dest = src - (ROUND(2^M*src))*2^-M;

where “Round()” treats “src”, “2^M”, and their product as binary floating-point numbers with normalized signifi-

cand and biased exponents.

The magnitude of the reduced result can be expressed by considering src= 2^p*man2,

where ‘man2’ is the normalized significand and ‘p’ is the unbiased exponent

Then if RC = RNE: 0<=|Reduced Result|<=2^p-M-1

Then if RC ≠ RNE: 0<=|Reduced Result|<2^p-M

This instruction might end up with a precision exception set. However, in case of SPE set (i.e., Suppress Precision

Exception, which is imm8[3]=1), no precision exception is reported.

EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Handling of special case of input values are listed in Table 5-19.

5-652

Vol. 2C

VREDUCEPS—Perform Reduction Transformation on Packed Float32 Values

INSTRUCTION SET REFERENCE, V

VREDUCESS—Perform a Reduction Transformation on a Scalar Float32 Value

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F3A.W0 57 /r

A

V/V

AVX512DQ

Perform a reduction transformation on a scalar single-precision

/ib

floating-point value in xmm3/m32 by subtracting a number of

VREDUCESS xmm1 {k1}{z},

fraction bits specified by the imm8 field. Also, upper single-

xmm2, xmm3/m32{sae},

precision floating-point values (bits[127:32]) from xmm2 are

imm8

copied to xmm1[127:32]. Stores the result in xmm1 register.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Perform a reduction transformation of the binary encoded single-precision floating-point value in the low dword

element of the second source operand (the third operand) and store the reduced result in binary floating-point

format to the low dword element of the destination operand (the first operand) under the writemask k1. Bits

127:32 of the destination operand are copied from respective dword elements of the first source operand (the

second operand).

The reduction transformation subtracts the integer part and the leading M fractional bits from the binary floating-

point source value, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduc-

tion transformation can be expressed as:

dest = src - (ROUND(2^M*src))*2^-M;

where “Round()” treats “src”, “2^M”, and their product as binary floating-point numbers with normalized signifi-

cand and biased exponents.

The magnitude of the reduced result can be expressed by considering src= 2^p*man2,

where ‘man2’ is the normalized significand and ‘p’ is the unbiased exponent

Then if RC = RNE: 0<=|Reduced Result|<=2^p-M-1

Then if RC ≠ RNE: 0<=|Reduced Result|<2^p-M

This instruction might end up with a precision exception set. However, in case of SPE set (i.e., Suppress Precision

Exception, which is imm8[3]=1), no precision exception is reported.

Handling of special case of input values are listed in Table 5-19.

Operation

ReduceArgumentSP(SRC[31:0], imm8[7:0])

{

// Check for NaN

IF (SRC [31:0] = NAN) THEN

RETURN (Convert SRC[31:0] to QNaN); FI

M := imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted

RC := imm8[1:0];// Round Control for ROUND() operation

RC source := imm[2];

SPE := imm[3];// Suppress Precision Exception

TMP[31:0] := 2^-M *{ROUND(2^M*SRC[31:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2^M as standard binary FP values

TMP[31:0] := SRC[31:0] - TMP[31:0]; // subtraction under the same RC,SPE controls

RETURN TMP[31:0]; // binary encoded FP with biased exponent and normalized significand

}

5-654

Vol. 2C

VREDUCESS—Perform a Reduction Transformation on a Scalar Float32 Value

INSTRUCTION SET REFERENCE, V

VRNDSCALEPD—Round Packed Float64 Values to Include a Given Number of Fraction Bits

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.128.66.0F3A.W1 09 /r ib

A

V/V

AVX512VL

Rounds packed double precision floating-point values in

VRNDSCALEPD xmm1 {k1}{z},

AVX512F

xmm2/m128/m64bcst to a number of fraction bits

xmm2/m128/m64bcst, imm8

specified by the imm8 field. Stores the result in xmm1

register. Under writemask.

EVEX.256.66.0F3A.W1 09 /r ib

A

V/V

AVX512VL

Rounds packed double precision floating-point values in

VRNDSCALEPD ymm1 {k1}{z},

AVX512F

ymm2/m256/m64bcst to a number of fraction bits

ymm2/m256/m64bcst, imm8

specified by the imm8 field. Stores the result in ymm1

register. Under writemask.

EVEX.512.66.0F3A.W1 09 /r ib

A

V/V

AVX512F

Rounds packed double precision floating-point values in

VRNDSCALEPD zmm1 {k1}{z},

zmm2/m512/m64bcst to a number of fraction bits

zmm2/m512/m64bcst{sae}, imm8

specified by the imm8 field. Stores the result in zmm1

register using writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

imm8

N/A

Description

Round the double precision floating-point values in the source operand by the rounding mode specified in the

immediate operand (see Figure 5-29) and places the result in the destination operand.

The destination operand (the first operand) is a ZMM/YMM/XMM register conditionally updated according to the

writemask. The source operand (the second operand) can be a ZMM/YMM/XMM register, a 512/256/128-bit

memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location.

The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by

imm8[7:4] (to be included in the result) and returns the result as a double precision floating-point value.

It should be noticed that no overflow is induced while executing this instruction (although the source is scaled by

the imm8[7:4] value).

The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and

shown in the “Immediate Control Description” figure below. Bit 3 of the immediate byte controls the processor

behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky

rounding-mode value (immediate control table below lists the encoded values for rounding-mode field).

The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an

SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before

rounding.

The sign of the result of this instruction is preserved, including the sign of zero.

The formula of the operation on each data element for VRNDSCALEPD is

ROUND(x) = 2^-M*Round_to_INT(x*2^M, round_ctrl),

round_ctrl = imm[3:0];

M=imm[7:4];

The operation of x*2^M is computed as if the exponent range is unlimited (i.e., no overflow ever occurs).

5-656

Vol. 2C

VRNDSCALEPD—Round Packed Float64 Values to Include a Given Number of Fraction Bits

INSTRUCTION SET REFERENCE, V

VRNDSCALEPD is a more general form of the VEX-encoded VROUNDPD instruction. In VROUNDPD, the formula of

the operation on each element is

ROUND(x) = Round_to_INT(x, round_ctrl),

round_ctrl = imm[3:0];

Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

7

6

5

4

3

2

1

0

imm8

Fixed point length

SPE

RS

Round Control Override

Suppress Precision Exception: Imm8[3]

Imm8[1:0] = 00b : Round nearest even

Imm8[3] = 0b : Use MXCSR exception mask

Round Select: Imm8[2]

Imm8[7:4] : Number of fixed points to preserve

Imm8[1:0] = 01b : Round down

Imm8[3] = 1b : Suppress

Imm8[2] = 0b : Use Imm8[1:0]

Imm8[1:0] = 10b : Round up

Imm8[2] = 1b : Use MXCSR

Imm8[1:0] = 11b : Truncate

Figure 5-29. Imm8 Controls for VRNDSCALEPD/SD/PS/SS

Handling of special case of input values are listed in Table 5-21.

Table 5-21. VRNDSCALEPD/SD/PS/SS Special Cases

Returned value

Src1=±inf

Src1

Src1=±NAN

Src1 converted to QNAN

Src1=±0

Src1

Operation

RoundToIntegerDP(SRC[63:0], imm8[7:0]) {

if (imm8[2] = 1)

rounding_direction := MXCSR:RC

; get round control from MXCSR

else

rounding_direction := imm8[1:0]

; get round control from imm8[1:0]

FI

M := imm8[7:4]

; get the scaling factor

case (rounding_direction)

00: TMP[63:0] := round_to_nearest_even_integer(2^M*SRC[63:0])

01: TMP[63:0] := round_to_equal_or_smaller_integer(2^M*SRC[63:0])

10: TMP[63:0] := round_to_equal_or_larger_integer(2^M*SRC[63:0])

11: TMP[63:0] := round_to_nearest_smallest_magnitude_integer(2^M*SRC[63:0])

ESAC

Dest[63:0] := 2^-M* TMP[63:0]

; scale down back to 2^-M

if (imm8[3] = 0) Then

; check SPE

if (SRC[63:0] != Dest[63:0]) Then

; check precision lost

set_precision()

; set #PE

FI;

FI;

VRNDSCALEPD—Round Packed Float64 Values to Include a Given Number of Fraction Bits

Vol. 2C

5-657

INSTRUCTION SET REFERENCE, V

VRNDSCALEPH—Round Packed FP16 Values to Include a Given Number of Fraction Bits

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.128.NP.0F3A.W0 08 /r /ib

A

V/V

AVX512-FP16

Round packed FP16 values in xmm2/m128/

VRNDSCALEPH xmm1{k1}{z}, xmm2/

AVX512VL

m16bcst to a number of fraction bits specified by

m128/m16bcst, imm8

the imm8 field. Store the result in xmm1 subject

to writemask k1.

EVEX.256.NP.0F3A.W0 08 /r /ib

A

V/V

AVX512-FP16

Round packed FP16 values in ymm2/m256/

VRNDSCALEPH ymm1{k1}{z}, ymm2/

AVX512VL

m16bcst to a number of fraction bits specified by

m256/m16bcst, imm8

the imm8 field. Store the result in ymm1 subject

to writemask k1.

EVEX.512.NP.0F3A.W0 08 /r /ib

A

V/V

AVX512-FP16

Round packed FP16 values in zmm2/m512/

VRNDSCALEPH zmm1{k1}{z}, zmm2/

m16bcst to a number of fraction bits specified by

m512/m16bcst {sae}, imm8

the imm8 field. Store the result in zmm1 subject

to writemask k1.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

imm8 (r)

N/A

Description

This instruction rounds the FP16 values in the source operand by the rounding mode specified in the immediate

operand (see Table 5-22) and places the result in the destination operand. The destination operand is conditionally

updated according to the writemask.

The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by

imm8[7:4] (to be included in the result), and returns the result as an FP16 value.

Note that no overflow is induced while executing this instruction (although the source is scaled by the imm8[7:4]

value).

The immediate operand also specifies control fields for the rounding operation. Three bit fields are defined and

shown in Table 5-22, “Imm8 Controls for VRNDSCALEPH/VRNDSCALESH.” Bit 3 of the immediate byte controls the

processor behavior for a precision exception, bit 2 selects the source of rounding mode control, and bits 1:0 specify

a non-sticky rounding-mode value.

The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an

SNaN then it will be converted to a QNaN.

The sign of the result of this instruction is preserved, including the sign of zero. Special cases are described in Table

5-23.

The formula of the operation on each data element for VRNDSCALEPH is

ROUND(x) = 2^−M *Round_to_INT(x * 2^M, round_ctrl),

round_ctrl = imm[3:0];

M=imm[7:4];

The operation of x * 2^M is computed as if the exponent range is unlimited (i.e., no overflow ever occurs).

If this instruction encoding’s SPE bit (bit 3) in the immediate operand is 1, VRNDSCALEPH can set MXCSR.UE

without MXCSR.PE.

EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

VRNDSCALEPH—Round Packed FP16 Values to Include a Given Number of Fraction Bits

Vol. 2C

5-659

INSTRUCTION SET REFERENCE, V

Table 5-22. Imm8 Controls for VRNDSCALEPH/VRNDSCALESH

Imm8 Bits

Description

imm8[7:4]

Number of fixed points to preserve.

imm8[3]

Suppress Precision Exception (SPE)

0b00: Implies use of MXCSR exception mask.

0b01: Implies suppress.

imm8[2]

Round Select (RS)

0b00: Implies use of imm8[1:0].

0b01: Implies use of MXCSR.

imm8[1:0]

Round Control Override:

0b00: Round nearest even.

0b01: Round down.

0b10: Round up.

0b11: Truncate.

Table 5-23. VRNDSCALEPH/VRNDSCALESH Special Cases

Input Value

Returned Value

Src1 = ±∞

Src1

Src1 = ±NaN

Src1 converted to QNaN

Src1 = ±0

Src1

Operation

def round_fp16_to_integer(src, imm8):

if imm8[2] = 1:

rounding_direction := MXCSR.RC

else:

rounding_direction := imm8[1:0]

m := imm8[7:4] // scaling factor

tsrc1 := 2^m * src

if rounding_direction = 0b00:

tmp := round_to_nearest_even_integer(trc1)

else if rounding_direction = 0b01:

tmp := round_to_equal_or_smaller_integer(trc1)

else if rounding_direction = 0b10:

tmp := round_to_equal_or_larger_integer(trc1)

else if rounding_direction = 0b11:

tmp := round_to_smallest_magnitude_integer(trc1)

dst := 2^(-m) * tmp

if imm8[3]==0: // check SPE

if src != dst:

MXCSR.PE := 1

return dst

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Vol. 2C

VRNDSCALEPH—Round Packed FP16 Values to Include a Given Number of Fraction Bits

INSTRUCTION SET REFERENCE, V

VRNDSCALEPS—Round Packed Float32 Values to Include a Given Number of Fraction Bits

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.128.66.0F3A.W0 08 /r ib

A

V/V

AVX512VL

Rounds packed single-precision floating-point values in

VRNDSCALEPS xmm1 {k1}{z},

AVX512F

xmm2/m128/m32bcst to a number of fraction bits

xmm2/m128/m32bcst, imm8

specified by the imm8 field. Stores the result in xmm1

register. Under writemask.

EVEX.256.66.0F3A.W0 08 /r ib

A

V/V

AVX512VL

Rounds packed single-precision floating-point values in

VRNDSCALEPS ymm1 {k1}{z},

AVX512F

ymm2/m256/m32bcst to a number of fraction bits

ymm2/m256/m32bcst, imm8

specified by the imm8 field. Stores the result in ymm1

register. Under writemask.

EVEX.512.66.0F3A.W0 08 /r ib

A

V/V

AVX512F

Rounds packed single-precision floating-point values in

VRNDSCALEPS zmm1 {k1}{z},

zmm2/m512/m32bcst to a number of fraction bits

zmm2/m512/m32bcst{sae}, imm8

specified by the imm8 field. Stores the result in zmm1

register using writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

imm8

N/A

Description

Round the single-precision floating-point values in the source operand by the rounding mode specified in the imme-

diate operand (see Figure 5-29) and places the result in the destination operand.

The destination operand (the first operand) is a ZMM register conditionally updated according to the writemask.

The source operand (the second operand) can be a ZMM register, a 512-bit memory location, or a 512-bit vector

broadcasted from a 32-bit memory location.

The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by

imm8[7:4] (to be included in the result) and returns the result as a single-precision floating-point value.

It should be noticed that no overflow is induced while executing this instruction (although the source is scaled by

the imm8[7:4] value).

The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and

shown in the “Immediate Control Description” figure below. Bit 3 of the immediate byte controls the processor

behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky

rounding-mode value (immediate control table below lists the encoded values for rounding-mode field).

The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an

SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before

rounding.

The sign of the result of this instruction is preserved, including the sign of zero.

The formula of the operation on each data element for VRNDSCALEPS is

ROUND(x) = 2^-M*Round_to_INT(x*2^M, round_ctrl),

round_ctrl = imm[3:0];

M=imm[7:4];

The operation of x*2^M is computed as if the exponent range is unlimited (i.e., no overflow ever occurs).

VRNDSCALEPS is a more general form of the VEX-encoded VROUNDPS instruction. In VROUNDPS, the formula of

the operation on each element is

ROUND(x) = Round_to_INT(x, round_ctrl),

round_ctrl = imm[3:0];

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Vol. 2C

VRNDSCALEPS—Round Packed Float32 Values to Include a Given Number of Fraction Bits

INSTRUCTION SET REFERENCE, V

VRNDSCALESD—Round Scalar Float64 Value to Include a Given Number of Fraction Bits

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F3A.W1 0B /r ib

A

V/V

AVX512F

Rounds scalar double precision floating-point value in

VRNDSCALESD xmm1 {k1}{z}, xmm2,

xmm3/m64 to a number of fraction bits specified by the

xmm3/m64{sae}, imm8

imm8 field. Stores the result in xmm1 register.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

Rounds a double precision floating-point value in the low quadword (see Figure 5-29) element of the second source

operand (the third operand) by the rounding mode specified in the immediate operand and places the result in the

corresponding element of the destination operand (the first operand) according to the writemask. The quadword

element at bits 127:64 of the destination is copied from the first source operand (the second operand).

The destination and first source operands are XMM registers, the 2nd source operand can be an XMM register or

memory location. Bits MAXVL-1:128 of the destination register are cleared.

The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by

imm8[7:4] (to be included in the result) and returns the result as a double precision floating-point value.

It should be noticed that no overflow is induced while executing this instruction (although the source is scaled by

the imm8[7:4] value).

The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and

shown in the “Immediate Control Description” figure below. Bit 3 of the immediate byte controls the processor

behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky

rounding-mode value (immediate control table below lists the encoded values for rounding-mode field).

The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an

SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before

rounding.

The sign of the result of this instruction is preserved, including the sign of zero.

The formula of the operation for VRNDSCALESD is

ROUND(x) = 2^-M*Round_to_INT(x*2^M, round_ctrl),

round_ctrl = imm[3:0];

M=imm[7:4];

The operation of x*2^M is computed as if the exponent range is unlimited (i.e., no overflow ever occurs).

VRNDSCALESD is a more general form of the VEX-encoded VROUNDSD instruction. In VROUNDSD, the formula of

the operation is

ROUND(x) = Round_to_INT(x, round_ctrl),

round_ctrl = imm[3:0];

EVEX encoded version: The source operand is a XMM register or a 64-bit memory location. The destination operand

is a XMM register.

Handling of special case of input values are listed in Table 5-21.

VRNDSCALESD—Round Scalar Float64 Value to Include a Given Number of Fraction Bits

Vol. 2C

5-665

INSTRUCTION SET REFERENCE, V

VRNDSCALESH—Round Scalar FP16 Value to Include a Given Number of Fraction Bits

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

En

bit Mode

Flag

Support

EVEX.LLIG.NP.0F3A.W0 0A /r /ib

A

V/V

AVX512-FP16

Round the low FP16 value in xmm3/m16 to a

VRNDSCALESH xmm1{k1}{z}, xmm2,

number of fraction bits specified by the imm8

xmm3/m16 {sae}, imm8

field. Store the result in xmm1 subject to

writemask k1. Bits 127:16 from xmm2 are

copied to xmm1[127:16].

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

A

Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8 (r)

Description

This instruction rounds the low FP16 value in the second source operand by the rounding mode specified in the

immediate operand (see Table 5-22) and places the result in the destination operand.

Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits

MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according

to the writemask.

The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by

imm8[7:4] (to be included in the result), and returns the result as a FP16 value.

Note that no overflow is induced while executing this instruction (although the source is scaled by the imm8[7:4]

value).

The immediate operand also specifies control fields for the rounding operation. Three bit fields are defined and

shown in Table 5-22, “Imm8 Controls for VRNDSCALEPH/VRNDSCALESH.” Bit 3 of the immediate byte controls the

processor behavior for a precision exception, bit 2 selects the source of rounding mode control, and bits 1:0 specify

a non-sticky rounding-mode value.

The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an

SNaN then it will be converted to a QNaN.

The sign of the result of this instruction is preserved, including the sign of zero. Special cases are described in Table

5-23.

If this instruction encoding’s SPE bit (bit 3) in the immediate operand is 1, VRNDSCALESH can set MXCSR.UE

without MXCSR.PE.

The formula of the operation on each data element for VRNDSCALESH is:

ROUND(x) = 2^−M *Round_to_INT(x * 2^M, round_ctrl),

round_ctrl = imm[3:0];

M=imm[7:4];

The operation of x * 2^M is computed as if the exponent range is unlimited (i.e., no overflow ever occurs).

Operation

VRNDSCALESH dest{k1}, src1, src2, imm8

IF k1[0] or *no writemask*:

DEST.fp16[0] := round_fp16_to_integer(src2.fp16[0], imm8) // see VRNDSCALEPH

ELSE IF *zeroing*:

DEST.fp16[0] := 0

//else DEST.fp16[0] remains unchanged

DEST[127:16] = src1[127:16]

DEST[MAXVL-1:128] := 0

VRNDSCALESH—Round Scalar FP16 Value to Include a Given Number of Fraction Bits

Vol. 2C

5-667

INSTRUCTION SET REFERENCE, V

VRNDSCALESS—Round Scalar Float32 Value to Include a Given Number of Fraction Bits

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F3A.W0 0A /r ib

A

V/V

AVX512F

Rounds scalar single-precision floating-point value in

VRNDSCALESS xmm1 {k1}{z}, xmm2,

xmm3/m32 to a number of fraction bits specified by the

xmm3/m32{sae}, imm8

imm8 field. Stores the result in xmm1 register under

writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Rounds the single-precision floating-point value in the low doubleword element of the second source operand (the

third operand) by the rounding mode specified in the immediate operand (see Figure 5-29) and places the result in

the corresponding element of the destination operand (the first operand) according to the writemask. The double-

word elements at bits 127:32 of the destination are copied from the first source operand (the second operand).

The destination and first source operands are XMM registers, the 2nd source operand can be an XMM register or

memory location. Bits MAXVL-1:128 of the destination register are cleared.

The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by

imm8[7:4] (to be included in the result) and returns the result as a single-precision floating-point value.

It should be noticed that no overflow is induced while executing this instruction (although the source is scaled by

the imm8[7:4] value).

The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and

shown in the “Immediate Control Description” figure below. Bit 3 of the immediate byte controls the processor

behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky

rounding-mode value (immediate control tables below lists the encoded values for rounding-mode field).

The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an

SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before

rounding.

The sign of the result of this instruction is preserved, including the sign of zero.

The formula of the operation for VRNDSCALESS is

ROUND(x) = 2^-M*Round_to_INT(x*2^M, round_ctrl),

round_ctrl = imm[3:0];

M=imm[7:4];

The operation of x*2^M is computed as if the exponent range is unlimited (i.e., no overflow ever occurs).

VRNDSCALESS is a more general form of the VEX-encoded VROUNDSS instruction. In VROUNDSS, the formula of

the operation on each element is

ROUND(x) = Round_to_INT(x, round_ctrl),

round_ctrl = imm[3:0];

EVEX encoded version: The source operand is a XMM register or a 32-bit memory location. The destination operand

is a XMM register.

Handling of special case of input values are listed in Table 5-21.

VRNDSCALESS—Round Scalar Float32 Value to Include a Given Number of Fraction Bits

Vol. 2C

5-669

INSTRUCTION SET REFERENCE, V

VRSQRT14PD—Compute Approximate Reciprocals of Square Roots of Packed Float64 Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.128.66.0F38.W1 4E /r

A

V/V

AVX512VL

Computes the approximate reciprocal square roots of the

VRSQRT14PD xmm1 {k1}{z},

AVX512F

packed double precision floating-point values in

xmm2/m128/m64bcst

xmm2/m128/m64bcst and stores the results in xmm1.

Under writemask.

EVEX.256.66.0F38.W1 4E /r

A

V/V

AVX512VL

Computes the approximate reciprocal square roots of the

VRSQRT14PD ymm1 {k1}{z},

AVX512F

packed double precision floating-point values in

ymm2/m256/m64bcst

ymm2/m256/m64bcst and stores the results in ymm1.

Under writemask.

EVEX.512.66.0F38.W1 4E /r

A

V/V

AVX512F

Computes the approximate reciprocal square roots of the

VRSQRT14PD zmm1 {k1}{z},

packed double precision floating-point values in

zmm2/m512/m64bcst

zmm2/m512/m64bcst and stores the results in zmm1

under writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

This instruction performs a SIMD computation of the approximate reciprocals of the square roots of the eight

packed double precision floating-point values in the source operand (the second operand) and stores the packed

double precision floating-point results in the destination operand (the first operand) according to the writemask.

The maximum relative error for this approximation is less than 2^-14.

EVEX.512 encoded version: The source operand can be a ZMM register, a 512-bit memory location, or a 512-bit

vector broadcasted from a 64-bit memory location. The destination operand is a ZMM register, conditionally

updated using writemask k1.

EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector

broadcasted from a 64-bit memory location. The destination operand is a YMM register, conditionally updated using

writemask k1.

EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector

broadcasted from a 64-bit memory location. The destination operand is a XMM register, conditionally updated using

writemask k1.

The VRSQRT14PD instruction is not affected by the rounding control bits in the MXCSR register. When a source

value is a 0.0, an ∞ with the sign of the source value is returned. When the source operand is an +∞ then +ZERO

value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated

correctly and performs the approximation with the specified masked response. When a source value is a negative

value (other than 0.0) a floating-point QNaN_indefinite is returned. When a source value is an SNaN or QNaN, the

SNaN is converted to a QNaN or the source QNaN is returned.

MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.

Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-

cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

VRSQRT14PD—Compute Approximate Reciprocals of Square Roots of Packed Float64 Values

Vol. 2C

5-671

INSTRUCTION SET REFERENCE, V

Operation

VRSQRT14PD (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN DEST[i+63:i] := APPROXIMATE(1.0/ SQRT(SRC[63:0]));

ELSE DEST[i+63:i] := APPROXIMATE(1.0/ SQRT(SRC[i+63:i]));

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

Table 5-24. VRSQRT14PD Special Cases

Input value

Result value

Comments

Any denormal

Normal

Cannot generate overflow

X = 2^-2n

2ⁿ

X < 0

QNaN_Indefinite

Including -INF

X = -0

-INF

X = +0

+INF

X = +INF

+0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT14PD __m512d _mm512_rsqrt14_pd( __m512d a);

VRSQRT14PD __m512d _mm512_mask_rsqrt14_pd(__m512d s, __mmask8 k, __m512d a);

VRSQRT14PD __m512d _mm512_maskz_rsqrt14_pd( __mmask8 k, __m512d a);

VRSQRT14PD __m256d _mm256_rsqrt14_pd( __m256d a);

VRSQRT14PD __m256d _mm512_mask_rsqrt14_pd(__m256d s, __mmask8 k, __m256d a);

VRSQRT14PD __m256d _mm512_maskz_rsqrt14_pd( __mmask8 k, __m256d a);

VRSQRT14PD __m128d _mm_rsqrt14_pd( __m128d a);

VRSQRT14PD __m128d _mm_mask_rsqrt14_pd(__m128d s, __mmask8 k, __m128d a);

VRSQRT14PD __m128d _mm_maskz_rsqrt14_pd( __mmask8 k, __m128d a);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-49, “Type E4 Class Exception Conditions.”

5-672

Vol. 2C

VRSQRT14PD—Compute Approximate Reciprocals of Square Roots of Packed Float64 Values

INSTRUCTION SET REFERENCE, V

VRSQRT14SD—Compute Approximate Reciprocal of Square Root of Scalar Float64 Value

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F38.W1 4F /r

A

V/V

AVX512F

Computes the approximate reciprocal square root of the

VRSQRT14SD xmm1 {k1}{z},

scalar double precision floating-point value in xmm3/m64

xmm2, xmm3/m64

and stores the result in the low quadword element of xmm1

using writemask k1. Bits[127:64] of xmm2 is copied to

xmm1[127:64].

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Computes the approximate reciprocal of the square roots of the scalar double precision floating-point value in the

low quadword element of the source operand (the second operand) and stores the result in the low quadword

element of the destination operand (the first operand) according to the writemask. The maximum relative error for

this approximation is less than 2^-14. The source operand can be an XMM register or a 32-bit memory location. The

destination operand is an XMM register.

Bits (127:64) of the XMM register destination are copied from corresponding bits in the first source operand. Bits

(MAXVL-1:128) of the destination register are zeroed.

The VRSQRT14SD instruction is not affected by the rounding control bits in the MXCSR register. When a source

value is a 0.0, an ∞ with the sign of the source value is returned. When the source operand is an +∞ then +ZERO

value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated

correctly and performs the approximation with the specified masked response. When a source value is a negative

value (other than 0.0) a floating-point QNaN_indefinite is returned. When a source value is an SNaN or QNaN, the

SNaN is converted to a QNaN or the source QNaN is returned.

MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.

A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-

cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation

VRSQRT14SD (EVEX version)

IF k1[0] or *no writemask*

THEN DEST[63:0] := APPROXIMATE(1.0/ SQRT(SRC2[63:0]))

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[63:0] remains unchanged*

ELSE

; zeroing-masking

THEN DEST[63:0] := 0

FI;

FI;

DEST[127:64] := SRC1[127:64]

DEST[MAXVL-1:128] := 0

VRSQRT14SD—Compute Approximate Reciprocal of Square Root of Scalar Float64 Value

Vol. 2C

5-673

INSTRUCTION SET REFERENCE, V

Table 5-25. VRSQRT14SD Special Cases

Input value

Result value

Comments

Any denormal

Normal

Cannot generate overflow

X = 2^-2n

2ⁿ

X < 0

QNaN_Indefinite

Including -INF

X = -0

-INF

X = +0

+INF

X = +INF

+0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT14SD __m128d _mm_rsqrt14_sd( __m128d a, __m128d b);

VRSQRT14SD __m128d _mm_mask_rsqrt14_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);

VRSQRT14SD __m128d _mm_maskz_rsqrt14_sd( __mmask8d m, __m128d a, __m128d b);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-51, “Type E5 Class Exception Conditions.”

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VRSQRT14SD—Compute Approximate Reciprocal of Square Root of Scalar Float64 Value

INSTRUCTION SET REFERENCE, V

VRSQRT14PS—Compute Approximate Reciprocals of Square Roots of Packed Float32 Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

EVEX.128.66.0F38.W0 4E /r

A

V/V

AVX512VL

Computes the approximate reciprocal square roots of the

VRSQRT14PS xmm1 {k1}{z},

AVX512F

packed single-precision floating-point values in

xmm2/m128/m32bcst

xmm2/m128/m32bcst and stores the results in xmm1.

Under writemask.

EVEX.256.66.0F38.W0 4E /r

A

V/V

AVX512VL

Computes the approximate reciprocal square roots of the

VRSQRT14PS ymm1 {k1}{z},

AVX512F

packed single-precision floating-point values in

ymm2/m256/m32bcst

ymm2/m256/m32bcst and stores the results in ymm1.

Under writemask.

EVEX.512.66.0F38.W0 4E /r

A

V/V

AVX512F

Computes the approximate reciprocal square roots of the

VRSQRT14PS zmm1 {k1}{z},

packed single-precision floating-point values in

zmm2/m512/m32bcst

zmm2/m512/m32bcst and stores the results in zmm1. Under

writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

Full

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

This instruction performs a SIMD computation of the approximate reciprocals of the square roots of 16 packed

single-precision floating-point values in the source operand (the second operand) and stores the packed single-

precision floating-point results in the destination operand (the first operand) according to the writemask. The

maximum relative error for this approximation is less than 2^-14.

EVEX.512 encoded version: The source operand can be a ZMM register, a 512-bit memory location or a 512-bit

vector broadcasted from a 32-bit memory location. The destination operand is a ZMM register, conditionally

updated using writemask k1.

EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector

broadcasted from a 32-bit memory location. The destination operand is a YMM register, conditionally updated using

writemask k1.

EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector

broadcasted from a 32-bit memory location. The destination operand is a XMM register, conditionally updated using

writemask k1.

The VRSQRT14PS instruction is not affected by the rounding control bits in the MXCSR register. When a source

value is a 0.0, an ∞ with the sign of the source value is returned. When the source operand is an +∞ then +ZERO

value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated

correctly and performs the approximation with the specified masked response. When a source value is a negative

value (other than 0.0) a floating-point QNaN_indefinite is returned. When a source value is an SNaN or QNaN, the

SNaN is converted to a QNaN or the source QNaN is returned.

MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.

Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-

cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

VRSQRT14PS—Compute Approximate Reciprocals of Square Roots of Packed Float32 Values

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INSTRUCTION SET REFERENCE, V

Operation

VRSQRT14PS (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask* THEN

IF (EVEX.b = 1) AND (SRC *is memory*)

THEN DEST[i+31:i] := APPROXIMATE(1.0/ SQRT(SRC[31:0]));

ELSE DEST[i+31:i] := APPROXIMATE(1.0/ SQRT(SRC[i+31:i]));

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

Table 5-26. VRSQRT14PS Special Cases

Input value

Result value

Comments

Any denormal

Normal

Cannot generate overflow

X = 2^-2n

2ⁿ

X < 0

QNaN_Indefinite

Including -INF

X = -0

-INF

X = +0

+INF

X = +INF

+0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT14PS __m512 _mm512_rsqrt14_ps( __m512 a);

VRSQRT14PS __m512 _mm512_mask_rsqrt14_ps(__m512 s, __mmask16 k, __m512 a);

VRSQRT14PS __m512 _mm512_maskz_rsqrt14_ps( __mmask16 k, __m512 a);

VRSQRT14PS __m256 _mm256_rsqrt14_ps( __m256 a);

VRSQRT14PS __m256 _mm256_mask_rsqrt14_ps(__m256 s, __mmask8 k, __m256 a);

VRSQRT14PS __m256 _mm256_maskz_rsqrt14_ps( __mmask8 k, __m256 a);

VRSQRT14PS __m128 _mm_rsqrt14_ps( __m128 a);

VRSQRT14PS __m128 _mm_mask_rsqrt14_ps(__m128 s, __mmask8 k, __m128 a);

VRSQRT14PS __m128 _mm_maskz_rsqrt14_ps( __mmask8 k, __m128 a);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions.”

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VRSQRT14PS—Compute Approximate Reciprocals of Square Roots of Packed Float32 Values

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