Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 104
INSTRUCTION SET REFERENCE, V
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Packed Dword, Packed
Qword with Signed Dword, Signed Qword Indices
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W0 A0 /vsib
A
V/V
AVX512VL
Using signed dword indices, scatter dword values to
VPSCATTERDD vm32x {k1}, xmm1
AVX512F
memory using writemask k1.
EVEX.256.66.0F38.W0 A0 /vsib
A
V/V
AVX512VL
Using signed dword indices, scatter dword values to
VPSCATTERDD vm32y {k1}, ymm1
AVX512F
memory using writemask k1.
EVEX.512.66.0F38.W0 A0 /vsib
A
V/V
AVX512F
Using signed dword indices, scatter dword values to
VPSCATTERDD vm32z {k1}, zmm1
memory using writemask k1.
EVEX.128.66.0F38.W1 A0 /vsib
A
V/V
AVX512VL
Using signed dword indices, scatter qword values to
VPSCATTERDQ vm32x {k1}, xmm1
AVX512F
memory using writemask k1.
EVEX.256.66.0F38.W1 A0 /vsib
A
V/V
AVX512VL
Using signed dword indices, scatter qword values to
VPSCATTERDQ vm32x {k1}, ymm1
AVX512F
memory using writemask k1.
EVEX.512.66.0F38.W1 A0 /vsib
A
V/V
AVX512F
Using signed dword indices, scatter qword values to
VPSCATTERDQ vm32y {k1}, zmm1
memory using writemask k1.
EVEX.128.66.0F38.W0 A1 /vsib
A
V/V
AVX512VL
Using signed qword indices, scatter dword values to
VPSCATTERQD vm64x {k1}, xmm1
AVX512F
memory using writemask k1.
EVEX.256.66.0F38.W0 A1 /vsib
A
V/V
AVX512VL
Using signed qword indices, scatter dword values to
VPSCATTERQD vm64y {k1}, xmm1
AVX512F
memory using writemask k1.
EVEX.512.66.0F38.W0 A1 /vsib
A
V/V
AVX512F
Using signed qword indices, scatter dword values to
VPSCATTERQD vm64z {k1}, ymm1
memory using writemask k1.
EVEX.128.66.0F38.W1 A1 /vsib
A
V/V
AVX512VL
Using signed qword indices, scatter qword values to
VPSCATTERQQ vm64x {k1}, xmm1
AVX512F
memory using writemask k1.
EVEX.256.66.0F38.W1 A1 /vsib
A
V/V
AVX512VL
Using signed qword indices, scatter qword values to
VPSCATTERQQ vm64y {k1}, ymm1
AVX512F
memory using writemask k1.
EVEX.512.66.0F38.W1 A1 /vsib
A
V/V
AVX512F
Using signed qword indices, scatter qword values to
VPSCATTERQQ vm64z {k1}, zmm1
memory using writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
BaseReg (R): VSIB:base,
A
Tuple1 Scalar
ModRM:reg (r)
N/A
N/A
VectorReg(R): VSIB:index
Description
Stores up to 16 elements (8 elements for qword indices) in doubleword vector or 8 elements in quadword vector to
the memory locations pointed by base address BASE_ADDR and index vector VINDEX, with scale SCALE. The
elements are specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements
will only be stored if their corresponding mask bit is one. The entire mask register will be set to zero by this instruc-
tion unless it triggers an exception.
This instruction can be suspended by an exception if at least one element is already scattered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask register are partially updated. If any traps or interrupts are pending from already scattered
elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
Note that:
• Only writes to overlapping vector indices are guaranteed to be ordered with respect to each other (from LSB to
MSB of the source registers). Note that this also include partially overlapping vector indices. Writes that are not
overlapped may happen in any order. Memory ordering with other instructions follows the Intel-64 memory
ordering model. Note that this does not account for non-overlapping indices that map into the same physical
address locations.
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Packed Dword, Packed Qword with Signed Dword, Signed
Vol. 2C
5-577
INSTRUCTION SET REFERENCE, V
• If two or more destination indices completely overlap, the “earlier” write(s) may be skipped.
• Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination ZMM will be completed (and non-faulting). Individual elements
closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
in the conventional order.
• Elements may be scattered in any order, but faults must be delivered in a right-to left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
• This instruction does not perform AC checks, and so will never deliver an AC fault.
• Not valid with 16-bit effective addresses. Will deliver a #UD fault.
• If this instruction overwrites itself and then takes a fault, only a subset of elements may be completed before
the fault is delivered (as described above). If the fault handler completes and attempts to re-execute this
instruction, the new instruction will be executed, and the scatter will not complete.
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are
ignored.
The instruction will #UD fault if the k0 mask register is specified.
The instruction will #UD fault if EVEX.Z = 1.
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a ZMM register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1 or 4 byte displacement
VPSCATTERDD (EVEX encoded versions)
(KL, VL)= (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN MEM[BASE_ADDR +SignExtend(VINDEX[i+31:i]) * SCALE + DISP] := SRC[i+31:i]
k1[j] := 0
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
VPSCATTERDQ (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN MEM[BASE_ADDR +SignExtend(VINDEX[k+31:k]) * SCALE + DISP] := SRC[i+63:i]
k1[j] := 0
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Packed Dword, Packed Qword with Signed Dword, Signed
5-578
Vol. 2C
INSTRUCTION SET REFERENCE, V
VPSCATTERQD (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
k := j * 64
IF k1[j] OR *no writemask*
THEN MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP] := SRC[i+31:i]
k1[j] := 0
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
VPSCATTERQQ (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN MEM[BASE_ADDR + (VINDEX[j+63:j]) * SCALE + DISP] := SRC[i+63:i]
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPSCATTERDD void _mm512_i32scatter_epi32(void * base, __m512i vdx, __m512i a, int scale);
VPSCATTERDD void _mm256_i32scatter_epi32(void * base, __m256i vdx, __m256i a, int scale);
VPSCATTERDD void _mm_i32scatter_epi32(void * base, __m128i vdx, __m128i a, int scale);
VPSCATTERDD void _mm512_mask_i32scatter_epi32(void * base, __mmask16 k, __m512i vdx, __m512i a, int scale);
VPSCATTERDD void _mm256_mask_i32scatter_epi32(void * base, __mmask8 k, __m256i vdx, __m256i a, int scale);
VPSCATTERDD void _mm_mask_i32scatter_epi32(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);
VPSCATTERDQ void _mm512_i32scatter_epi64(void * base, __m256i vdx, __m512i a, int scale);
VPSCATTERDQ void _mm256_i32scatter_epi64(void * base, __m128i vdx, __m256i a, int scale);
VPSCATTERDQ void _mm_i32scatter_epi64(void * base, __m128i vdx, __m128i a, int scale);
VPSCATTERDQ void _mm512_mask_i32scatter_epi64(void * base, __mmask8 k, __m256i vdx, __m512i a, int scale);
VPSCATTERDQ void _mm256_mask_i32scatter_epi64(void * base, __mmask8 k, __m128i vdx, __m256i a, int scale);
VPSCATTERDQ void _mm_mask_i32scatter_epi64(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);
VPSCATTERQD void _mm512_i64scatter_epi32(void * base, __m512i vdx, __m256i a, int scale);
VPSCATTERQD void _mm256_i64scatter_epi32(void * base, __m256i vdx, __m128i a, int scale);
VPSCATTERQD void _mm_i64scatter_epi32(void * base, __m128i vdx, __m128i a, int scale);
VPSCATTERQD void _mm512_mask_i64scatter_epi32(void * base, __mmask8 k, __m512i vdx, __m256i a, int scale);
VPSCATTERQD void _mm256_mask_i64scatter_epi32(void * base, __mmask8 k, __m256i vdx, __m128i a, int scale);
VPSCATTERQD void _mm_mask_i64scatter_epi32(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);
VPSCATTERQQ void _mm512_i64scatter_epi64(void * base, __m512i vdx, __m512i a, int scale);
VPSCATTERQQ void _mm256_i64scatter_epi64(void * base, __m256i vdx, __m256i a, int scale);
VPSCATTERQQ void _mm_i64scatter_epi64(void * base, __m128i vdx, __m128i a, int scale);
VPSCATTERQQ void _mm512_mask_i64scatter_epi64(void * base, __mmask8 k, __m512i vdx, __m512i a, int scale);
VPSCATTERQQ void _mm256_mask_i64scatter_epi64(void * base, __mmask8 k, __m256i vdx, __m256i a, int scale);
VPSCATTERQQ void _mm_mask_i64scatter_epi64(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);
SIMD Floating-Point Exceptions
None.
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Packed Dword, Packed Qword with Signed Dword, Signed
Vol. 2C
5-579
INSTRUCTION SET REFERENCE, V
Other Exceptions
See Table 2-61, “Type E12 Class Exception Conditions.”
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Packed Dword, Packed Qword with Signed Dword, Signed
5-580
Vol. 2C
INSTRUCTION SET REFERENCE, V
VPSHLD—Concatenate and Shift Packed Data Left Logical
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F3A.W1 70 /r /ib
A
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDW xmm1{k1}{z}, xmm2,
AVX512VL
extract result shifted to the left by constant
xmm3/m128, imm8
value in imm8 into xmm1.
EVEX.256.66.0F3A.W1 70 /r /ib
A
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDW ymm1{k1}{z}, ymm2,
AVX512VL
extract result shifted to the left by constant
ymm3/m256, imm8
value in imm8 into ymm1.
EVEX.512.66.0F3A.W1 70 /r /ib
A
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDW zmm1{k1}{z}, zmm2,
extract result shifted to the left by constant
zmm3/m512, imm8
value in imm8 into zmm1.
EVEX.128.66.0F3A.W0 71 /r /ib
B
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDD xmm1{k1}{z}, xmm2,
AVX512VL
extract result shifted to the left by constant
xmm3/m128/m32bcst, imm8
value in imm8 into xmm1.
EVEX.256.66.0F3A.W0 71 /r /ib
B
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDD ymm1{k1}{z}, ymm2,
AVX512VL
extract result shifted to the left by constant
ymm3/m256/m32bcst, imm8
value in imm8 into ymm1.
EVEX.512.66.0F3A.W0 71 /r /ib
B
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDD zmm1{k1}{z}, zmm2,
extract result shifted to the left by constant
zmm3/m512/m32bcst, imm8
value in imm8 into zmm1.
EVEX.128.66.0F3A.W1 71 /r /ib
B
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDQ xmm1{k1}{z}, xmm2,
AVX512VL
extract result shifted to the left by constant
xmm3/m128/m64bcst, imm8
value in imm8 into xmm1.
EVEX.256.66.0F3A.W1 71 /r /ib
B
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDQ ymm1{k1}{z}, ymm2,
AVX512VL
extract result shifted to the left by constant
ymm3/m256/m64bcst, imm8
value in imm8 into ymm1.
EVEX.512.66.0F3A.W1 71 /r /ib
B
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHLDQ zmm1{k1}{z}, zmm2,
extract result shifted to the left by constant
zmm3/m512/m64bcst, imm8
value in imm8 into zmm1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8 (r)
B
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8 (r)
Description
Concatenate packed data, extract result shifted to the left by constant value.
This instruction supports memory fault suppression.
VPSHLD—Concatenate and Shift Packed Data Left Logical
Vol. 2C
5-581
INSTRUCTION SET REFERENCE, V
Operation
VPSHLDW DEST, SRC2, SRC3, imm8
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1:
IF MaskBit(j) OR *no writemask*:
tmp := concat(SRC2.word[j], SRC3.word[j]) << (imm8 & 15)
DEST.word[j] := tmp.word[1]
ELSE IF *zeroing*:
DEST.word[j] := 0
*ELSE DEST.word[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHLDD DEST, SRC2, SRC3, imm8
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1:
IF SRC3 is broadcast memop:
tsrc3 := SRC3.dword[0]
ELSE:
tsrc3 := SRC3.dword[j]
IF MaskBit(j) OR *no writemask*:
tmp := concat(SRC2.dword[j], tsrc3) << (imm8 & 31)
DEST.dword[j] := tmp.dword[1]
ELSE IF *zeroing*:
DEST.dword[j] := 0
*ELSE DEST.dword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHLDQ DEST, SRC2, SRC3, imm8
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1:
IF SRC3 is broadcast memop:
tsrc3 := SRC3.qword[0]
ELSE:
tsrc3 := SRC3.qword[j]
IF MaskBit(j) OR *no writemask*:
tmp := concat(SRC2.qword[j], tsrc3) << (imm8 & 63)
DEST.qword[j] := tmp.qword[1]
ELSE IF *zeroing*:
DEST.qword[j] := 0
*ELSE DEST.qword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
5-582
Vol. 2C
VPSHLD—Concatenate and Shift Packed Data Left Logical
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPSHLDD __m128i _mm_shldi_epi32(__m128i, __m128i, int);
VPSHLDD __m128i _mm_mask_shldi_epi32(__m128i, __mmask8, __m128i, __m128i, int);
VPSHLDD __m128i _mm_maskz_shldi_epi32(__mmask8, __m128i, __m128i, int);
VPSHLDD __m256i _mm256_shldi_epi32(__m256i, __m256i, int);
VPSHLDD __m256i _mm256_mask_shldi_epi32(__m256i, __mmask8, __m256i, __m256i, int);
VPSHLDD __m256i _mm256_maskz_shldi_epi32(__mmask8, __m256i, __m256i, int);
VPSHLDD __m512i _mm512_shldi_epi32(__m512i, __m512i, int);
VPSHLDD __m512i _mm512_mask_shldi_epi32(__m512i, __mmask16, __m512i, __m512i, int);
VPSHLDD __m512i _mm512_maskz_shldi_epi32(__mmask16, __m512i, __m512i, int);
VPSHLDQ __m128i _mm_shldi_epi64(__m128i, __m128i, int);
VPSHLDQ __m128i _mm_mask_shldi_epi64(__m128i, __mmask8, __m128i, __m128i, int);
VPSHLDQ __m128i _mm_maskz_shldi_epi64(__mmask8, __m128i, __m128i, int);
VPSHLDQ __m256i _mm256_shldi_epi64(__m256i, __m256i, int);
VPSHLDQ __m256i _mm256_mask_shldi_epi64(__m256i, __mmask8, __m256i, __m256i, int);
VPSHLDQ __m256i _mm256_maskz_shldi_epi64(__mmask8, __m256i, __m256i, int);
VPSHLDQ __m512i _mm512_shldi_epi64(__m512i, __m512i, int);
VPSHLDQ __m512i _mm512_mask_shldi_epi64(__m512i, __mmask8, __m512i, __m512i, int);
VPSHLDQ __m512i _mm512_maskz_shldi_epi64(__mmask8, __m512i, __m512i, int);
VPSHLDW __m128i _mm_shldi_epi16(__m128i, __m128i, int);
VPSHLDW __m128i _mm_mask_shldi_epi16(__m128i, __mmask8, __m128i, __m128i, int);
VPSHLDW __m128i _mm_maskz_shldi_epi16(__mmask8, __m128i, __m128i, int);
VPSHLDW __m256i _mm256_shldi_epi16(__m256i, __m256i, int);
VPSHLDW __m256i _mm256_mask_shldi_epi16(__m256i, __mmask16, __m256i, __m256i, int);
VPSHLDW __m256i _mm256_maskz_shldi_epi16(__mmask16, __m256i, __m256i, int);
VPSHLDW __m512i _mm512_shldi_epi16(__m512i, __m512i, int);
VPSHLDW __m512i _mm512_mask_shldi_epi16(__m512i, __mmask32, __m512i, __m512i, int);
VPSHLDW __m512i _mm512_maskz_shldi_epi16(__mmask32, __m512i, __m512i, int);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-49, “Type E4 Class Exception Conditions.”
VPSHLD—Concatenate and Shift Packed Data Left Logical
Vol. 2C
5-583
INSTRUCTION SET REFERENCE, V
VPSHLDV—Concatenate and Variable Shift Packed Data Left Logical
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F38.W1 70 /r
A
V/V
AVX512_VBMI2
Concatenate xmm1 and xmm2, extract result
VPSHLDVW xmm1{k1}{z}, xmm2,
AVX512VL
shifted to the left by value in xmm3/m128 into
xmm3/m128
xmm1.
EVEX.256.66.0F38.W1 70 /r
A
V/V
AVX512_VBMI2
Concatenate ymm1 and ymm2, extract result
VPSHLDVW ymm1{k1}{z}, ymm2,
AVX512VL
shifted to the left by value in xmm3/m256 into
ymm3/m256
ymm1.
EVEX.512.66.0F38.W1 70 /r
A
V/V
AVX512_VBMI2
Concatenate zmm1 and zmm2, extract result
VPSHLDVW zmm1{k1}{z}, zmm2,
shifted to the left by value in zmm3/m512 into
zmm3/m512
zmm1.
EVEX.128.66.0F38.W0 71 /r
B
V/V
AVX512_VBMI2
Concatenate xmm1 and xmm2, extract result
VPSHLDVD xmm1{k1}{z}, xmm2,
AVX512VL
shifted to the left by value in xmm3/m128 into
xmm3/m128/m32bcst
xmm1.
EVEX.256.66.0F38.W0 71 /r
B
V/V
AVX512_VBMI2
Concatenate ymm1 and ymm2, extract result
VPSHLDVD ymm1{k1}{z}, ymm2,
AVX512VL
shifted to the left by value in xmm3/m256 into
ymm3/m256/m32bcst
ymm1.
EVEX.512.66.0F38.W0 71 /r
B
V/V
AVX512_VBMI2
Concatenate zmm1 and zmm2, extract result
VPSHLDVD zmm1{k1}{z}, zmm2,
shifted to the left by value in zmm3/m512 into
zmm3/m512/m32bcst
zmm1.
EVEX.128.66.0F38.W1 71 /r
B
V/V
AVX512_VBMI2
Concatenate xmm1 and xmm2, extract result
VPSHLDVQ xmm1{k1}{z}, xmm2,
AVX512VL
shifted to the left by value in xmm3/m128 into
xmm3/m128/m64bcst
xmm1.
EVEX.256.66.0F38.W1 71 /r
B
V/V
AVX512_VBMI2
Concatenate ymm1 and ymm2, extract result
VPSHLDVQ ymm1{k1}{z}, ymm2,
AVX512VL
shifted to the left by value in xmm3/m256 into
ymm3/m256/m64bcst
ymm1.
EVEX.512.66.0F38.W1 71 /r
B
V/V
AVX512_VBMI2
Concatenate zmm1 and zmm2, extract result
VPSHLDVQ zmm1{k1}{z}, zmm2,
shifted to the left by value in zmm3/m512 into
zmm3/m512/m64bcst
zmm1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Concatenate packed data, extract result shifted to the left by variable value.
This instruction supports memory fault suppression.
5-584
Vol. 2C
VPSHLDV—Concatenate and Variable Shift Packed Data Left Logical
INSTRUCTION SET REFERENCE, V
Operation
FUNCTION concat(a,b):
IF words:
d.word[1] := a
d.word[0] := b
return d
ELSE IF dwords:
q.dword[1] := a
q.dword[0] := b
return q
ELSE IF qwords:
o.qword[1] := a
o.qword[0] := b
return o
VPSHLDVW DEST, SRC2, SRC3
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1:
IF MaskBit(j) OR *no writemask*:
tmp := concat(DEST.word[j], SRC2.word[j]) << (SRC3.word[j] & 15)
DEST.word[j] := tmp.word[1]
ELSE IF *zeroing*:
DEST.word[j] := 0
*ELSE DEST.word[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHLDVD DEST, SRC2, SRC3
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1:
IF SRC3 is broadcast memop:
tsrc3 := SRC3.dword[0]
ELSE:
tsrc3 := SRC3.dword[j]
IF MaskBit(j) OR *no writemask*:
tmp := concat(DEST.dword[j], SRC2.dword[j]) << (tsrc3 & 31)
DEST.dword[j] := tmp.dword[1]
ELSE IF *zeroing*:
DEST.dword[j] := 0
*ELSE DEST.dword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHLDV—Concatenate and Variable Shift Packed Data Left Logical
Vol. 2C
5-585
INSTRUCTION SET REFERENCE, V
VPSHLDVQ DEST, SRC2, SRC3
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1:
IF SRC3 is broadcast memop:
tsrc3 := SRC3.qword[0]
ELSE:
tsrc3 := SRC3.qword[j]
IF MaskBit(j) OR *no writemask*:
tmp := concat(DEST.qword[j], SRC2.qword[j]) << (tsrc3 & 63)
DEST.qword[j] := tmp.qword[1]
ELSE IF *zeroing*:
DEST.qword[j] := 0
*ELSE DEST.qword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPSHLDVW __m128i _mm_shldv_epi16(__m128i, __m128i, __m128i);
VPSHLDVW __m128i _mm_mask_shldv_epi16(__m128i, __mmask8, __m128i, __m128i);
VPSHLDVW __m128i _mm_maskz_shldv_epi16(__mmask8, __m128i, __m128i, __m128i);
VPSHLDVW __m256i _mm256_shldv_epi16(__m256i, __m256i, __m256i);
VPSHLDVW __m256i _mm256_mask_shldv_epi16(__m256i, __mmask16, __m256i, __m256i);
VPSHLDVW __m256i _mm256_maskz_shldv_epi16(__mmask16, __m256i, __m256i, __m256i);
VPSHLDVQ __m512i _mm512_shldv_epi64(__m512i, __m512i, __m512i);
VPSHLDVQ __m512i _mm512_mask_shldv_epi64(__m512i, __mmask8, __m512i, __m512i);
VPSHLDVQ __m512i _mm512_maskz_shldv_epi64(__mmask8, __m512i, __m512i, __m512i);
VPSHLDVW __m128i _mm_shldv_epi16(__m128i, __m128i, __m128i);
VPSHLDVW __m128i _mm_mask_shldv_epi16(__m128i, __mmask8, __m128i, __m128i);
VPSHLDVW __m128i _mm_maskz_shldv_epi16(__mmask8, __m128i, __m128i, __m128i);
VPSHLDVW __m256i _mm256_shldv_epi16(__m256i, __m256i, __m256i);
VPSHLDVW __m256i _mm256_mask_shldv_epi16(__m256i, __mmask16, __m256i, __m256i);
VPSHLDVW __m256i _mm256_maskz_shldv_epi16(__mmask16, __m256i, __m256i, __m256i);
VPSHLDVW __m512i _mm512_shldv_epi16(__m512i, __m512i, __m512i);
VPSHLDVW __m512i _mm512_mask_shldv_epi16(__m512i, __mmask32, __m512i, __m512i);
VPSHLDVW __m512i _mm512_maskz_shldv_epi16(__mmask32, __m512i, __m512i, __m512i);
VPSHLDVD __m128i _mm_shldv_epi32(__m128i, __m128i, __m128i);
VPSHLDVD __m128i _mm_mask_shldv_epi32(__m128i, __mmask8, __m128i, __m128i);
VPSHLDVD __m128i _mm_maskz_shldv_epi32(__mmask8, __m128i, __m128i, __m128i);
VPSHLDVD __m256i _mm256_shldv_epi32(__m256i, __m256i, __m256i);
VPSHLDVD __m256i _mm256_mask_shldv_epi32(__m256i, __mmask8, __m256i, __m256i);
VPSHLDVD __m256i _mm256_maskz_shldv_epi32(__mmask8, __m256i, __m256i, __m256i);
VPSHLDVD __m512i _mm512_shldv_epi32(__m512i, __m512i, __m512i);
VPSHLDVD __m512i _mm512_mask_shldv_epi32(__m512i, __mmask16, __m512i, __m512i);
VPSHLDVD __m512i _mm512_maskz_shldv_epi32(__mmask16, __m512i, __m512i, __m512i);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-49, “Type E4 Class Exception Conditions.”
5-586
Vol. 2C
VPSHLDV—Concatenate and Variable Shift Packed Data Left Logical
INSTRUCTION SET REFERENCE, V
VPSHRD—Concatenate and Shift Packed Data Right Logical
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F3A.W1 72 /r /ib
A
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDW xmm1{k1}{z}, xmm2,
AVX512VL
extract result shifted to the right by constant
xmm3/m128, imm8
value in imm8 into xmm1.
EVEX.256.66.0F3A.W1 72 /r /ib
A
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDW ymm1{k1}{z}, ymm2,
AVX512VL
extract result shifted to the right by constant
ymm3/m256, imm8
value in imm8 into ymm1.
EVEX.512.66.0F3A.W1 72 /r /ib
A
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDW zmm1{k1}{z}, zmm2,
extract result shifted to the right by constant
zmm3/m512, imm8
value in imm8 into zmm1.
EVEX.128.66.0F3A.W0 73 /r /ib
B
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDD xmm1{k1}{z}, xmm2,
AVX512VL
extract result shifted to the right by constant
xmm3/m128/m32bcst, imm8
value in imm8 into xmm1.
EVEX.256.66.0F3A.W0 73 /r /ib
B
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDD ymm1{k1}{z}, ymm2,
AVX512VL
extract result shifted to the right by constant
ymm3/m256/m32bcst, imm8
value in imm8 into ymm1.
EVEX.512.66.0F3A.W0 73 /r /ib
B
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDD zmm1{k1}{z}, zmm2,
extract result shifted to the right by constant
zmm3/m512/m32bcst, imm8
value in imm8 into zmm1.
EVEX.128.66.0F3A.W1 73 /r /ib
B
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDQ xmm1{k1}{z}, xmm2,
AVX512VL
extract result shifted to the right by constant
xmm3/m128/m64bcst, imm8
value in imm8 into xmm1.
EVEX.256.66.0F3A.W1 73 /r /ib
B
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDQ ymm1{k1}{z}, ymm2,
AVX512VL
extract result shifted to the right by constant
ymm3/m256/m64bcst, imm8
value in imm8 into ymm1.
EVEX.512.66.0F3A.W1 73 /r /ib
B
V/V
AVX512_VBMI2
Concatenate destination and source operands,
VPSHRDQ zmm1{k1}{z}, zmm2,
extract result shifted to the right by constant
zmm3/m512/m64bcst, imm8
value in imm8 into zmm1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8 (r)
B
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8 (r)
Description
Concatenate packed data, extract result shifted to the right by constant value.
This instruction supports memory fault suppression.
VPSHRD—Concatenate and Shift Packed Data Right Logical
Vol. 2C
5-587
INSTRUCTION SET REFERENCE, V
Operation
VPSHRDW DEST, SRC2, SRC3, imm8
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1:
IF MaskBit(j) OR *no writemask*:
DEST.word[j] := concat(SRC3.word[j], SRC2.word[j]) >> (imm8 & 15)
ELSE IF *zeroing*:
DEST.word[j] := 0
*ELSE DEST.word[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHRDD DEST, SRC2, SRC3, imm8
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1:
IF SRC3 is broadcast memop:
tsrc3 := SRC3.dword[0]
ELSE:
tsrc3 := SRC3.dword[j]
IF MaskBit(j) OR *no writemask*:
DEST.dword[j] := concat(tsrc3, SRC2.dword[j]) >> (imm8 & 31)
ELSE IF *zeroing*:
DEST.dword[j] := 0
*ELSE DEST.dword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHRDQ DEST, SRC2, SRC3, imm8
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1:
IF SRC3 is broadcast memop:
tsrc3 := SRC3.qword[0]
ELSE:
tsrc3 := SRC3.qword[j]
IF MaskBit(j) OR *no writemask*:
DEST.qword[j] := concat(tsrc3, SRC2.qword[j]) >> (imm8 & 63)
ELSE IF *zeroing*:
DEST.qword[j] := 0
*ELSE DEST.qword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
5-588
Vol. 2C
VPSHRD—Concatenate and Shift Packed Data Right Logical
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPSHRDQ __m128i _mm_shrdi_epi64(__m128i, __m128i, int);
VPSHRDQ __m128i _mm_mask_shrdi_epi64(__m128i, __mmask8, __m128i, __m128i, int);
VPSHRDQ __m128i _mm_maskz_shrdi_epi64(__mmask8, __m128i, __m128i, int);
VPSHRDQ __m256i _mm256_shrdi_epi64(__m256i, __m256i, int);
VPSHRDQ __m256i _mm256_mask_shrdi_epi64(__m256i, __mmask8, __m256i, __m256i, int);
VPSHRDQ __m256i _mm256_maskz_shrdi_epi64(__mmask8, __m256i, __m256i, int);
VPSHRDQ __m512i _mm512_shrdi_epi64(__m512i, __m512i, int);
VPSHRDQ __m512i _mm512_mask_shrdi_epi64(__m512i, __mmask8, __m512i, __m512i, int);
VPSHRDQ __m512i _mm512_maskz_shrdi_epi64(__mmask8, __m512i, __m512i, int);
VPSHRDD __m128i _mm_shrdi_epi32(__m128i, __m128i, int);
VPSHRDD __m128i _mm_mask_shrdi_epi32(__m128i, __mmask8, __m128i, __m128i, int);
VPSHRDD __m128i _mm_maskz_shrdi_epi32(__mmask8, __m128i, __m128i, int);
VPSHRDD __m256i _mm256_shrdi_epi32(__m256i, __m256i, int);
VPSHRDD __m256i _mm256_mask_shrdi_epi32(__m256i, __mmask8, __m256i, __m256i, int);
VPSHRDD __m256i _mm256_maskz_shrdi_epi32(__mmask8, __m256i, __m256i, int);
VPSHRDD __m512i _mm512_shrdi_epi32(__m512i, __m512i, int);
VPSHRDD __m512i _mm512_mask_shrdi_epi32(__m512i, __mmask16, __m512i, __m512i, int);
VPSHRDD __m512i _mm512_maskz_shrdi_epi32(__mmask16, __m512i, __m512i, int);
VPSHRDW __m128i _mm_shrdi_epi16(__m128i, __m128i, int);
VPSHRDW __m128i _mm_mask_shrdi_epi16(__m128i, __mmask8, __m128i, __m128i, int);
VPSHRDW __m128i _mm_maskz_shrdi_epi16(__mmask8, __m128i, __m128i, int);
VPSHRDW __m256i _mm256_shrdi_epi16(__m256i, __m256i, int);
VPSHRDW __m256i _mm256_mask_shrdi_epi16(__m256i, __mmask16, __m256i, __m256i, int);
VPSHRDW __m256i _mm256_maskz_shrdi_epi16(__mmask16, __m256i, __m256i, int);
VPSHRDW __m512i _mm512_shrdi_epi16(__m512i, __m512i, int);
VPSHRDW __m512i _mm512_mask_shrdi_epi16(__m512i, __mmask32, __m512i, __m512i, int);
VPSHRDW __m512i _mm512_maskz_shrdi_epi16(__mmask32, __m512i, __m512i, int);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-49, “Type E4 Class Exception Conditions.”
VPSHRD—Concatenate and Shift Packed Data Right Logical
Vol. 2C
5-589
INSTRUCTION SET REFERENCE, V
VPSHRDV—Concatenate and Variable Shift Packed Data Right Logical
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F38.W1 72 /r
A
V/V
AVX512_VBMI2
Concatenate xmm1 and xmm2, extract result
VPSHRDVW xmm1{k1}{z}, xmm2,
AVX512VL
shifted to the right by value in xmm3/m128
xmm3/m128
into xmm1.
EVEX.256.66.0F38.W1 72 /r
A
V/V
AVX512_VBMI2
Concatenate ymm1 and ymm2, extract result
VPSHRDVW ymm1{k1}{z}, ymm2,
AVX512VL
shifted to the right by value in xmm3/m256
ymm3/m256
into ymm1.
EVEX.512.66.0F38.W1 72 /r
A
V/V
AVX512_VBMI2
Concatenate zmm1 and zmm2, extract result
VPSHRDVW zmm1{k1}{z}, zmm2,
shifted to the right by value in zmm3/m512
zmm3/m512
into zmm1.
EVEX.128.66.0F38.W0 73 /r
B
V/V
AVX512_VBMI2
Concatenate xmm1 and xmm2, extract result
VPSHRDVD xmm1{k1}{z}, xmm2,
AVX512VL
shifted to the right by value in xmm3/m128
xmm3/m128/m32bcst
into xmm1.
EVEX.256.66.0F38.W0 73 /r
B
V/V
AVX512_VBMI2
Concatenate ymm1 and ymm2, extract result
VPSHRDVD ymm1{k1}{z}, ymm2,
AVX512VL
shifted to the right by value in xmm3/m256
ymm3/m256/m32bcst
into ymm1.
EVEX.512.66.0F38.W0 73 /r
B
V/V
AVX512_VBMI2
Concatenate zmm1 and zmm2, extract result
VPSHRDVD zmm1{k1}{z}, zmm2,
shifted to the right by value in zmm3/m512
zmm3/m512/m32bcst
into zmm1.
EVEX.128.66.0F38.W1 73 /r
B
V/V
AVX512_VBMI2
Concatenate xmm1 and xmm2, extract result
VPSHRDVQ xmm1{k1}{z}, xmm2,
AVX512VL
shifted to the right by value in xmm3/m128
xmm3/m128/m64bcst
into xmm1.
EVEX.256.66.0F38.W1 73 /r
B
V/V
AVX512_VBMI2
Concatenate ymm1 and ymm2, extract result
VPSHRDVQ ymm1{k1}{z}, ymm2,
AVX512VL
shifted to the right by value in xmm3/m256
ymm3/m256/m64bcst
into ymm1.
EVEX.512.66.0F38.W1 73 /r
B
V/V
AVX512_VBMI2
Concatenate zmm1 and zmm2, extract result
VPSHRDVQ zmm1{k1}{z}, zmm2,
shifted to the right by value in zmm3/m512
zmm3/m512/m64bcst
into zmm1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Concatenate packed data, extract result shifted to the right by variable value.
This instruction supports memory fault suppression.
5-590
Vol. 2C
VPSHRDV—Concatenate and Variable Shift Packed Data Right Logical
INSTRUCTION SET REFERENCE, V
Operation
VPSHRDVW DEST, SRC2, SRC3
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1:
IF MaskBit(j) OR *no writemask*:
DEST.word[j] := concat(SRC2.word[j], DEST.word[j]) >> (SRC3.word[j] & 15)
ELSE IF *zeroing*:
DEST.word[j] := 0
*ELSE DEST.word[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHRDVD DEST, SRC2, SRC3
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1:
IF SRC3 is broadcast memop:
tsrc3 := SRC3.dword[0]
ELSE:
tsrc3 := SRC3.dword[j]
IF MaskBit(j) OR *no writemask*:
DEST.dword[j] := concat(SRC2.dword[j], DEST.dword[j]) >> (tsrc3 & 31)
ELSE IF *zeroing*:
DEST.dword[j] := 0
*ELSE DEST.dword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHRDVQ DEST, SRC2, SRC3
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1:
IF SRC3 is broadcast memop:
tsrc3 := SRC3.qword[0]
ELSE:
tsrc3 := SRC3.qword[j]
IF MaskBit(j) OR *no writemask*:
DEST.qword[j] := concat(SRC2.qword[j], DEST.qword[j]) >> (tsrc3 & 63)
ELSE IF *zeroing*:
DEST.qword[j] := 0
*ELSE DEST.qword[j] remains unchanged*
DEST[MAX_VL-1:VL] := 0
VPSHRDV—Concatenate and Variable Shift Packed Data Right Logical
Vol. 2C
5-591
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPSHRDVQ __m128i _mm_shrdv_epi64(__m128i, __m128i, __m128i);
VPSHRDVQ __m128i _mm_mask_shrdv_epi64(__m128i, __mmask8, __m128i, __m128i);
VPSHRDVQ __m128i _mm_maskz_shrdv_epi64(__mmask8, __m128i, __m128i, __m128i);
VPSHRDVQ __m256i _mm256_shrdv_epi64(__m256i, __m256i, __m256i);
VPSHRDVQ __m256i _mm256_mask_shrdv_epi64(__m256i, __mmask8, __m256i, __m256i);
VPSHRDVQ __m256i _mm256_maskz_shrdv_epi64(__mmask8, __m256i, __m256i, __m256i);
VPSHRDVQ __m512i _mm512_shrdv_epi64(__m512i, __m512i, __m512i);
VPSHRDVQ __m512i _mm512_mask_shrdv_epi64(__m512i, __mmask8, __m512i, __m512i);
VPSHRDVQ __m512i _mm512_maskz_shrdv_epi64(__mmask8, __m512i, __m512i, __m512i);
VPSHRDVD __m128i _mm_shrdv_epi32(__m128i, __m128i, __m128i);
VPSHRDVD __m128i _mm_mask_shrdv_epi32(__m128i, __mmask8, __m128i, __m128i);
VPSHRDVD __m128i _mm_maskz_shrdv_epi32(__mmask8, __m128i, __m128i, __m128i);
VPSHRDVD __m256i _mm256_shrdv_epi32(__m256i, __m256i, __m256i);
VPSHRDVD __m256i _mm256_mask_shrdv_epi32(__m256i, __mmask8, __m256i, __m256i);
VPSHRDVD __m256i _mm256_maskz_shrdv_epi32(__mmask8, __m256i, __m256i, __m256i);
VPSHRDVD __m512i _mm512_shrdv_epi32(__m512i, __m512i, __m512i);
VPSHRDVD __m512i _mm512_mask_shrdv_epi32(__m512i, __mmask16, __m512i, __m512i);
VPSHRDVD __m512i _mm512_maskz_shrdv_epi32(__mmask16, __m512i, __m512i, __m512i);
VPSHRDVW __m128i _mm_shrdv_epi16(__m128i, __m128i, __m128i);
VPSHRDVW __m128i _mm_mask_shrdv_epi16(__m128i, __mmask8, __m128i, __m128i);
VPSHRDVW __m128i _mm_maskz_shrdv_epi16(__mmask8, __m128i, __m128i, __m128i);
VPSHRDVW __m256i _mm256_shrdv_epi16(__m256i, __m256i, __m256i);
VPSHRDVW __m256i _mm256_mask_shrdv_epi16(__m256i, __mmask16, __m256i, __m256i);
VPSHRDVW __m256i _mm256_maskz_shrdv_epi16(__mmask16, __m256i, __m256i, __m256i);
VPSHRDVW __m512i _mm512_shrdv_epi16(__m512i, __m512i, __m512i);
VPSHRDVW __m512i _mm512_mask_shrdv_epi16(__m512i, __mmask32, __m512i, __m512i);
VPSHRDVW __m512i _mm512_maskz_shrdv_epi16(__mmask32, __m512i, __m512i, __m512i);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-49, “Type E4 Class Exception Conditions.”
5-592
Vol. 2C
VPSHRDV—Concatenate and Variable Shift Packed Data Right Logical
INSTRUCTION SET REFERENCE, V
VPSHUFBITQMB—Shuffle Bits From Quadword Elements Using Byte Indexes Into Mask
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F38.W0 8F /r
A
V/V
AVX512_BITALG
Extract values in xmm2 using control bits of
VPSHUFBITQMB k1{k2}, xmm2,
AVX512VL
xmm3/m128 with writemask k2 and leave the
xmm3/m128
result in mask register k1.
EVEX.256.66.0F38.W0 8F /r
A
V/V
AVX512_BITALG
Extract values in ymm2 using control bits of
VPSHUFBITQMB k1{k2}, ymm2,
AVX512VL
ymm3/m256 with writemask k2 and leave the
ymm3/m256
result in mask register k1.
EVEX.512.66.0F38.W0 8F /r
A
V/V
AVX512_BITALG
Extract values in zmm2 using control bits of
VPSHUFBITQMB k1{k2}, zmm2,
zmm3/m512 with writemask k2 and leave the
zmm3/m512
result in mask register k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
The VPSHUFBITQMB instruction performs a bit gather select using second source as control and first source as
data. Each bit uses 6 control bits (2nd source operand) to select which data bit is going to be gathered (first source
operand). A given bit can only access 64 different bits of data (first 64 destination bits can access first 64 data bits,
second 64 destination bits can access second 64 data bits, etc.).
Control data for each output bit is stored in 8 bit elements of SRC2, but only the 6 least significant bits of each
element are used.
This instruction uses write masking (zeroing only). This instruction supports memory fault suppression.
The first source operand is a ZMM register. The second source operand is a ZMM register or a memory location. The
destination operand is a mask register.
Operation
VPSHUFBITQMB DEST, SRC1, SRC2
(KL, VL) = (16,128), (32,256), (64, 512)
FOR i := 0 TO KL/8-1:
//Qword
FOR j := 0 to 7:
// Byte
IF k2[i*8+j] or *no writemask*:
m := SRC2.qword[i].byte[j] & 0x3F
k1[i*8+j] := SRC1.qword[i].bit[m]
ELSE:
k1[i*8+j] := 0
k1[MAX_KL-1:KL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPSHUFBITQMB __mmask16 _mm_bitshuffle_epi64_mask(__m128i, __m128i);
VPSHUFBITQMB __mmask16 _mm_mask_bitshuffle_epi64_mask(__mmask16, __m128i, __m128i);
VPSHUFBITQMB __mmask32 _mm256_bitshuffle_epi64_mask(__m256i, __m256i);
VPSHUFBITQMB __mmask32 _mm256_mask_bitshuffle_epi64_mask(__mmask32, __m256i, __m256i);
VPSHUFBITQMB __mmask64 _mm512_bitshuffle_epi64_mask(__m512i, __m512i);
VPSHUFBITQMB __mmask64 _mm512_mask_bitshuffle_epi64_mask(__mmask64, __m512i, __m512i);
VPSHUFBITQMB—Shuffle Bits From Quadword Elements Using Byte Indexes Into Mask
Vol. 2C
5-593
INSTRUCTION SET REFERENCE, V
VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left Logical
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
VEX.128.66.0F38.W0 47 /r
A
V/V
AVX2
Shift doublewords in xmm2 left by amount specified in
VPSLLVD xmm1, xmm2, xmm3/m128
the corresponding element of xmm3/m128 while
shifting in 0s.
VEX.128.66.0F38.W1 47 /r
A
V/V
AVX2
Shift quadwords in xmm2 left by amount specified in
VPSLLVQ xmm1, xmm2, xmm3/m128
the corresponding element of xmm3/m128 while
shifting in 0s.
VEX.256.66.0F38.W0 47 /r
A
V/V
AVX2
Shift doublewords in ymm2 left by amount specified in
VPSLLVD ymm1, ymm2, ymm3/m256
the corresponding element of ymm3/m256 while
shifting in 0s.
VEX.256.66.0F38.W1 47 /r
A
V/V
AVX2
Shift quadwords in ymm2 left by amount specified in
VPSLLVQ ymm1, ymm2, ymm3/m256
the corresponding element of ymm3/m256 while
shifting in 0s.
EVEX.128.66.0F38.W1 12 /r
B
V/V
AVX512VL
Shift words in xmm2 left by amount specified in the
VPSLLVW xmm1 {k1}{z}, xmm2,
AVX512BW
corresponding element of xmm3/m128 while shifting
xmm3/m128
in 0s using writemask k1.
EVEX.256.66.0F38.W1 12 /r
B
V/V
AVX512VL
Shift words in ymm2 left by amount specified in the
VPSLLVW ymm1 {k1}{z}, ymm2,
AVX512BW
corresponding element of ymm3/m256 while shifting
ymm3/m256
in 0s using writemask k1.
EVEX.512.66.0F38.W1 12 /r
B
V/V
AVX512BW
Shift words in zmm2 left by amount specified in the
VPSLLVW zmm1 {k1}{z}, zmm2,
corresponding element of zmm3/m512 while shifting
zmm3/m512
in 0s using writemask k1.
EVEX.128.66.0F38.W0 47 /r
C
V/V
AVX512VL
Shift doublewords in xmm2 left by amount specified in
VPSLLVD xmm1 {k1}{z}, xmm2,
AVX512F
the corresponding element of xmm3/m128/m32bcst
xmm3/m128/m32bcst
while shifting in 0s using writemask k1.
EVEX.256.66.0F38.W0 47 /r
C
V/V
AVX512VL
Shift doublewords in ymm2 left by amount specified in
VPSLLVD ymm1 {k1}{z}, ymm2,
AVX512F
the corresponding element of ymm3/m256/m32bcst
ymm3/m256/m32bcst
while shifting in 0s using writemask k1.
EVEX.512.66.0F38.W0 47 /r
C
V/V
AVX512F
Shift doublewords in zmm2 left by amount specified in
VPSLLVD zmm1 {k1}{z}, zmm2,
the corresponding element of zmm3/m512/m32bcst
zmm3/m512/m32bcst
while shifting in 0s using writemask k1.
EVEX.128.66.0F38.W1 47 /r
C
V/V
AVX512VL
Shift quadwords in xmm2 left by amount specified in
VPSLLVQ xmm1 {k1}{z}, xmm2,
AVX512F
the corresponding element of xmm3/m128/m64bcst
xmm3/m128/m64bcst
while shifting in 0s using writemask k1.
EVEX.256.66.0F38.W1 47 /r
C
V/V
AVX512VL
Shift quadwords in ymm2 left by amount specified in
VPSLLVQ ymm1 {k1}{z}, ymm2,
AVX512F
the corresponding element of ymm3/m256/m64bcst
ymm3/m256/m64bcst
while shifting in 0s using writemask k1.
EVEX.512.66.0F38.W1 47 /r
C
V/V
AVX512F
Shift quadwords in zmm2 left by amount specified in
VPSLLVQ zmm1 {k1}{z}, zmm2,
the corresponding element of zmm3/m512/m64bcst
zmm3/m512/m64bcst
while shifting in 0s using writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
5-594
Vol. 2C
VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left Logical
INSTRUCTION SET REFERENCE, V
Description
Shifts the bits in the individual data elements (words, doublewords or quadword) in the first source operand to the
left by the count value of respective data elements in the second source operand. As the bits in the data elements
are shifted left, the empty low-order bits are cleared (set to 0).
The count values are specified individually in each data element of the second source operand. If the unsigned
integer value specified in the respective data element of the second source operand is greater than 15 (for word),
31 (for doublewords), or 63 (for a quadword), then the destination data element are written with 0.
VEX.128 encoded version: The destination and first source operands are XMM registers. The count operand can be
either an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding destination register
are zeroed.
VEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be
either an YMM register or a 256-bit memory. Bits (MAXVL-1:256) of the corresponding ZMM register are zeroed.
EVEX encoded VPSLLVD/Q: The destination and first source operands are ZMM/YMM/XMM registers. The count
operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512-bit vector broad-
casted from a 32/64-bit memory location. The destination is conditionally updated with writemask k1.
EVEX encoded VPSLLVW: The destination and first source operands are ZMM/YMM/XMM registers. The count
operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is condition-
ally updated with writemask k1.
Operation
VPSLLVW (EVEX encoded version)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := ZeroExtend(SRC1[i+15:i] << SRC2[i+15:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0;
VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left Logical
Vol. 2C
5-595
INSTRUCTION SET REFERENCE, V
VPSLLVD (VEX.128 version)
COUNT_0 := SRC2[31 : 0]
(* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 := SRC2[127 : 96];
IF COUNT_0 < 32 THEN
DEST[31:0] := ZeroExtend(SRC1[31:0] << COUNT_0);
ELSE
DEST[31:0] := 0;
(* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 32 THEN
DEST[127:96] := ZeroExtend(SRC1[127:96] << COUNT_3);
ELSE
DEST[127:96] := 0;
DEST[MAXVL-1:128] := 0;
VPSLLVD (VEX.256 version)
COUNT_0 := SRC2[31 : 0];
(* Repeat Each COUNT_i for the 2nd through 7th dwords of SRC2*)
COUNT_7 := SRC2[255 : 224];
IF COUNT_0 < 32 THEN
DEST[31:0] := ZeroExtend(SRC1[31:0] << COUNT_0);
ELSE
DEST[31:0] := 0;
(* Repeat shift operation for 2nd through 7th dwords *)
IF COUNT_7 < 32 THEN
DEST[255:224] := ZeroExtend(SRC1[255:224] << COUNT_7);
ELSE
DEST[255:224] := 0;
DEST[MAXVL-1:256] := 0;
VPSLLVD (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] := ZeroExtend(SRC1[i+31:i] << SRC2[31:0])
ELSE DEST[i+31:i] := ZeroExtend(SRC1[i+31:i] << SRC2[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0;
5-596
Vol. 2C
VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left Logical
INSTRUCTION SET REFERENCE, V
VPSLLVQ (VEX.128 version)
COUNT_0 := SRC2[63 : 0];
COUNT_1 := SRC2[127 : 64];
IF COUNT_0 < 64THEN
DEST[63:0] := ZeroExtend(SRC1[63:0] << COUNT_0);
ELSE
DEST[63:0] := 0;
IF COUNT_1 < 64 THEN
DEST[127:64] := ZeroExtend(SRC1[127:64] << COUNT_1);
ELSE
DEST[127:96] := 0;
DEST[MAXVL-1:128] := 0;
VPSLLVQ (VEX.256 version)
COUNT_0 := SRC2[63 : 0];
(* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 := SRC2[255 : 192];
IF COUNT_0 < 64THEN
DEST[63:0] := ZeroExtend(SRC1[63:0] << COUNT_0);
ELSE
DEST[63:0] := 0;
(* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 64 THEN
DEST[255:192] := ZeroExtend(SRC1[255:192] << COUNT_3);
ELSE
DEST[255:192] := 0;
DEST[MAXVL-1:256] := 0;
VPSLLVQ (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] := ZeroExtend(SRC1[i+63:i] << SRC2[63:0])
ELSE DEST[i+63:i] := ZeroExtend(SRC1[i+63:i] << SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0;
VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left Logical
Vol. 2C
5-597
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPSLLVW __m512i _mm512_sllv_epi16(__m512i a, __m512i cnt);
VPSLLVW __m512i _mm512_mask_sllv_epi16(__m512i s, __mmask32 k, __m512i a, __m512i cnt);
VPSLLVW __m512i _mm512_maskz_sllv_epi16( __mmask32 k, __m512i a, __m512i cnt);
VPSLLVW __m256i _mm256_mask_sllv_epi16(__m256i s, __mmask16 k, __m256i a, __m256i cnt);
VPSLLVW __m256i _mm256_maskz_sllv_epi16( __mmask16 k, __m256i a, __m256i cnt);
VPSLLVW __m128i _mm_mask_sllv_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLVW __m128i _mm_maskz_sllv_epi16( __mmask8 k, __m128i a, __m128i cnt);
VPSLLVD __m512i _mm512_sllv_epi32(__m512i a, __m512i cnt);
VPSLLVD __m512i _mm512_mask_sllv_epi32(__m512i s, __mmask16 k, __m512i a, __m512i cnt);
VPSLLVD __m512i _mm512_maskz_sllv_epi32( __mmask16 k, __m512i a, __m512i cnt);
VPSLLVD __m256i _mm256_mask_sllv_epi32(__m256i s, __mmask8 k, __m256i a, __m256i cnt);
VPSLLVD __m256i _mm256_maskz_sllv_epi32( __mmask8 k, __m256i a, __m256i cnt);
VPSLLVD __m128i _mm_mask_sllv_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLVD __m128i _mm_maskz_sllv_epi32( __mmask8 k, __m128i a, __m128i cnt);
VPSLLVQ __m512i _mm512_sllv_epi64(__m512i a, __m512i cnt);
VPSLLVQ __m512i _mm512_mask_sllv_epi64(__m512i s, __mmask8 k, __m512i a, __m512i cnt);
VPSLLVQ __m512i _mm512_maskz_sllv_epi64( __mmask8 k, __m512i a, __m512i cnt);
VPSLLVD __m256i _mm256_mask_sllv_epi64(__m256i s, __mmask8 k, __m256i a, __m256i cnt);
VPSLLVD __m256i _mm256_maskz_sllv_epi64( __mmask8 k, __m256i a, __m256i cnt);
VPSLLVD __m128i _mm_mask_sllv_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLVD __m128i _mm_maskz_sllv_epi64( __mmask8 k, __m128i a, __m128i cnt);
VPSLLVD __m256i _mm256_sllv_epi32 (__m256i m, __m256i count)
VPSLLVQ __m256i _mm256_sllv_epi64 (__m256i m, __m256i count)
SIMD Floating-Point Exceptions
None.
Other Exceptions
VEX-encoded instructions, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded VPSLLVD/VPSLLVQ, see Table 2-49, “Type E4 Class Exception Conditions.”
EVEX-encoded VPSLLVW, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”
5-598
Vol. 2C
VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left Logical
INSTRUCTION SET REFERENCE, V
VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
VEX.128.66.0F38.W0 46 /r
A
V/V
AVX2
Shift doublewords in xmm2 right by amount specified
VPSRAVD xmm1, xmm2, xmm3/m128
in the corresponding element of xmm3/m128 while
shifting in sign bits.
VEX.256.66.0F38.W0 46 /r
A
V/V
AVX2
Shift doublewords in ymm2 right by amount specified
VPSRAVD ymm1, ymm2, ymm3/m256
in the corresponding element of ymm3/m256 while
shifting in sign bits.
EVEX.128.66.0F38.W1 11 /r
B
V/V
AVX512VL
Shift words in xmm2 right by amount specified in the
VPSRAVW xmm1 {k1}{z}, xmm2,
AVX512BW
corresponding element of xmm3/m128 while shifting
xmm3/m128
in sign bits using writemask k1.
EVEX.256.66.0F38.W1 11 /r
B
V/V
AVX512VL
Shift words in ymm2 right by amount specified in the
VPSRAVW ymm1 {k1}{z}, ymm2,
AVX512BW
corresponding element of ymm3/m256 while shifting
ymm3/m256
in sign bits using writemask k1.
EVEX.512.66.0F38.W1 11 /r
B
V/V
AVX512BW
Shift words in zmm2 right by amount specified in the
VPSRAVW zmm1 {k1}{z}, zmm2,
corresponding element of zmm3/m512 while shifting
zmm3/m512
in sign bits using writemask k1.
EVEX.128.66.0F38.W0 46 /r
C
V/V
AVX512VL
Shift doublewords in xmm2 right by amount specified
VPSRAVD xmm1 {k1}{z}, xmm2,
AVX512F
in the corresponding element of
xmm3/m128/m32bcst
xmm3/m128/m32bcst while shifting in sign bits
using writemask k1.
EVEX.256.66.0F38.W0 46 /r
C
V/V
AVX512VL
Shift doublewords in ymm2 right by amount specified
VPSRAVD ymm1 {k1}{z}, ymm2,
AVX512F
in the corresponding element of
ymm3/m256/m32bcst
ymm3/m256/m32bcst while shifting in sign bits
using writemask k1.
EVEX.512.66.0F38.W0 46 /r
C
V/V
AVX512F
Shift doublewords in zmm2 right by amount specified
VPSRAVD zmm1 {k1}{z}, zmm2,
in the corresponding element of
zmm3/m512/m32bcst
zmm3/m512/m32bcst while shifting in sign bits using
writemask k1.
EVEX.128.66.0F38.W1 46 /r
C
V/V
AVX512VL
Shift quadwords in xmm2 right by amount specified
VPSRAVQ xmm1 {k1}{z}, xmm2,
AVX512F
in the corresponding element of
xmm3/m128/m64bcst
xmm3/m128/m64bcst while shifting in sign bits
using writemask k1.
EVEX.256.66.0F38.W1 46 /r
C
V/V
AVX512VL
Shift quadwords in ymm2 right by amount specified
VPSRAVQ ymm1 {k1}{z}, ymm2,
AVX512F
in the corresponding element of
ymm3/m256/m64bcst
ymm3/m256/m64bcst while shifting in sign bits
using writemask k1.
EVEX.512.66.0F38.W1 46 /r
C
V/V
AVX512F
Shift quadwords in zmm2 right by amount specified in
VPSRAVQ zmm1 {k1}{z}, zmm2,
the corresponding element of zmm3/m512/m64bcst
zmm3/m512/m64bcst
while shifting in sign bits using writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic
Vol. 2C
5-599
INSTRUCTION SET REFERENCE, V
Description
Shifts the bits in the individual data elements (word/doublewords/quadword) in the first source operand (the
second operand) to the right by the number of bits specified in the count value of respective data elements in the
second source operand (the third operand). As the bits in the data elements are shifted right, the empty high-order
bits are set to the MSB (sign extension).
The count values are specified individually in each data element of the second source operand. If the unsigned
integer value specified in the respective data element of the second source operand is greater than 15 (for words),
31 (for doublewords), or 63 (for a quadword), then the destination data element is filled with the corresponding
sign bit of the source element.
VEX.128 encoded version: The destination and first source operands are XMM registers. The count operand can be
either an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding destination register
are zeroed.
VEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be
either an YMM register or a 256-bit memory. Bits (MAXVL-1:256) of the corresponding destination register are
zeroed.
EVEX.512/256/128 encoded VPSRAVD/W: The destination and first source operands are ZMM/YMM/XMM registers.
The count operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-
bit vector broadcasted from a 32/64-bit memory location. The destination is conditionally updated with writemask
k1.
EVEX.512/256/128 encoded VPSRAVQ: The destination and first source operands are ZMM/YMM/XMM registers.
The count operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is
conditionally updated with writemask k1.
Operation
VPSRAVW (EVEX encoded version)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF k1[j] OR *no writemask*
THEN
COUNT := SRC2[i+3:i]
IF COUNT < 16
THEN DEST[i+15:i] := SignExtend(SRC1[i+15:i] >> COUNT)
ELSE
FOR k := 0 TO 15
DEST[i+k] := SRC1[i+15]
ENDFOR;
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0;
5-600
Vol. 2C
VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic
INSTRUCTION SET REFERENCE, V
VPSRAVD (VEX.128 version)
COUNT_0 := SRC2[31 : 0]
(* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 := SRC2[127 : 96];
DEST[31:0] := SignExtend(SRC1[31:0] >> COUNT_0);
(* Repeat shift operation for 2nd through 4th dwords *)
DEST[127:96] := SignExtend(SRC1[127:96] >> COUNT_3);
DEST[MAXVL-1:128] := 0;
VPSRAVD (VEX.256 version)
COUNT_0 := SRC2[31 : 0];
(* Repeat Each COUNT_i for the 2nd through 8th dwords of SRC2*)
COUNT_7 := SRC2[255 : 224];
DEST[31:0] := SignExtend(SRC1[31:0] >> COUNT_0);
(* Repeat shift operation for 2nd through 7th dwords *)
DEST[255:224] := SignExtend(SRC1[255:224] >> COUNT_7);
DEST[MAXVL-1:256] := 0;
VPSRAVD (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
COUNT := SRC2[4:0]
IF COUNT < 32
THEN DEST[i+31:i] := SignExtend(SRC1[i+31:i] >> COUNT)
ELSE
FOR k := 0 TO 31
DEST[i+k] := SRC1[i+31]
ENDFOR;
FI
ELSE
COUNT := SRC2[i+4:i]
IF COUNT < 32
THEN DEST[i+31:i] := SignExtend(SRC1[i+31:i] >> COUNT)
ELSE
FOR k := 0 TO 31
DEST[i+k] := SRC1[i+31]
ENDFOR;
FI
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
DEST[31:0] := 0
FI
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0;
VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic
Vol. 2C
5-601
INSTRUCTION SET REFERENCE, V
VPSRAVQ (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
COUNT := SRC2[5:0]
IF COUNT < 64
THEN DEST[i+63:i] := SignExtend(SRC1[i+63:i] >> COUNT)
ELSE
FOR k := 0 TO 63
DEST[i+k] := SRC1[i+63]
ENDFOR;
FI
ELSE
COUNT := SRC2[i+5:i]
IF COUNT < 64
THEN DEST[i+63:i] := SignExtend(SRC1[i+63:i] >> COUNT)
ELSE
FOR k := 0 TO 63
DEST[i+k] := SRC1[i+63]
ENDFOR;
FI
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
DEST[63:0] := 0
FI
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0;
5-602
Vol. 2C
VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPSRAVD __m512i _mm512_srav_epi32(__m512i a, __m512i cnt);
VPSRAVD __m512i _mm512_mask_srav_epi32(__m512i s, __mmask16 m, __m512i a, __m512i cnt);
VPSRAVD __m512i _mm512_maskz_srav_epi32(__mmask16 m, __m512i a, __m512i cnt);
VPSRAVD __m256i _mm256_srav_epi32(__m256i a, __m256i cnt);
VPSRAVD __m256i _mm256_mask_srav_epi32(__m256i s, __mmask8 m, __m256i a, __m256i cnt);
VPSRAVD __m256i _mm256_maskz_srav_epi32(__mmask8 m, __m256i a, __m256i cnt);
VPSRAVD __m128i _mm_srav_epi32(__m128i a, __m128i cnt);
VPSRAVD __m128i _mm_mask_srav_epi32(__m128i s, __mmask8 m, __m128i a, __m128i cnt);
VPSRAVD __m128i _mm_maskz_srav_epi32(__mmask8 m, __m128i a, __m128i cnt);
VPSRAVQ __m512i _mm512_srav_epi64(__m512i a, __m512i cnt);
VPSRAVQ __m512i _mm512_mask_srav_epi64(__m512i s, __mmask8 m, __m512i a, __m512i cnt);
VPSRAVQ __m512i _mm512_maskz_srav_epi64( __mmask8 m, __m512i a, __m512i cnt);
VPSRAVQ __m256i _mm256_srav_epi64(__m256i a, __m256i cnt);
VPSRAVQ __m256i _mm256_mask_srav_epi64(__m256i s, __mmask8 m, __m256i a, __m256i cnt);
VPSRAVQ __m256i _mm256_maskz_srav_epi64( __mmask8 m, __m256i a, __m256i cnt);
VPSRAVQ __m128i _mm_srav_epi64(__m128i a, __m128i cnt);
VPSRAVQ __m128i _mm_mask_srav_epi64(__m128i s, __mmask8 m, __m128i a, __m128i cnt);
VPSRAVQ __m128i _mm_maskz_srav_epi64( __mmask8 m, __m128i a, __m128i cnt);
VPSRAVW __m512i _mm512_srav_epi16(__m512i a, __m512i cnt);
VPSRAVW __m512i _mm512_mask_srav_epi16(__m512i s, __mmask32 m, __m512i a, __m512i cnt);
VPSRAVW __m512i _mm512_maskz_srav_epi16(__mmask32 m, __m512i a, __m512i cnt);
VPSRAVW __m256i _mm256_srav_epi16(__m256i a, __m256i cnt);
VPSRAVW __m256i _mm256_mask_srav_epi16(__m256i s, __mmask16 m, __m256i a, __m256i cnt);
VPSRAVW __m256i _mm256_maskz_srav_epi16(__mmask16 m, __m256i a, __m256i cnt);
VPSRAVW __m128i _mm_srav_epi16(__m128i a, __m128i cnt);
VPSRAVW __m128i _mm_mask_srav_epi16(__m128i s, __mmask8 m, __m128i a, __m128i cnt);
VPSRAVW __m128i _mm_maskz_srav_epi32(__mmask8 m, __m128i a, __m128i cnt);
VPSRAVD __m256i _mm256_srav_epi32 (__m256i m, __m256i count)
SIMD Floating-Point Exceptions
None.
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”
VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic
Vol. 2C
5-603
INSTRUCTION SET REFERENCE, V
VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right Logical
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
VEX.128.66.0F38.W0 45 /r
A
V/V
AVX2
Shift doublewords in xmm2 right by amount specified
VPSRLVD xmm1, xmm2, xmm3/m128
in the corresponding element of xmm3/m128 while
shifting in 0s.
VEX.128.66.0F38.W1 45 /r
A
V/V
AVX2
Shift quadwords in xmm2 right by amount specified in
VPSRLVQ xmm1, xmm2, xmm3/m128
the corresponding element of xmm3/m128 while
shifting in 0s.
VEX.256.66.0F38.W0 45 /r
A
V/V
AVX2
Shift doublewords in ymm2 right by amount specified
VPSRLVD ymm1, ymm2, ymm3/m256
in the corresponding element of ymm3/m256 while
shifting in 0s.
VEX.256.66.0F38.W1 45 /r
A
V/V
AVX2
Shift quadwords in ymm2 right by amount specified in
VPSRLVQ ymm1, ymm2, ymm3/m256
the corresponding element of ymm3/m256 while
shifting in 0s.
EVEX.128.66.0F38.W1 10 /r
B
V/V
AVX512VL
Shift words in xmm2 right by amount specified in the
VPSRLVW xmm1 {k1}{z}, xmm2,
AVX512BW
corresponding element of xmm3/m128 while shifting
xmm3/m128
in 0s using writemask k1.
EVEX.256.66.0F38.W1 10 /r
B
V/V
AVX512VL
Shift words in ymm2 right by amount specified in the
VPSRLVW ymm1 {k1}{z}, ymm2,
AVX512BW
corresponding element of ymm3/m256 while shifting
ymm3/m256
in 0s using writemask k1.
EVEX.512.66.0F38.W1 10 /r
B
V/V
AVX512BW
Shift words in zmm2 right by amount specified in the
VPSRLVW zmm1 {k1}{z}, zmm2,
corresponding element of zmm3/m512 while shifting
zmm3/m512
in 0s using writemask k1.
EVEX.128.66.0F38.W0 45 /r
C
V/V
AVX512VL
Shift doublewords in xmm2 right by amount specified
VPSRLVD xmm1 {k1}{z}, xmm2,
AVX512F
in the corresponding element of xmm3/m128/m32bcst
xmm3/m128/m32bcst
while shifting in 0s using writemask k1.
EVEX.256.66.0F38.W0 45 /r
C
V/V
AVX512VL
Shift doublewords in ymm2 right by amount specified
VPSRLVD ymm1 {k1}{z}, ymm2,
AVX512F
in the corresponding element of ymm3/m256/m32bcst
ymm3/m256/m32bcst
while shifting in 0s using writemask k1.
EVEX.512.66.0F38.W0 45 /r
C
V/V
AVX512F
Shift doublewords in zmm2 right by amount specified
VPSRLVD zmm1 {k1}{z}, zmm2,
in the corresponding element of zmm3/m512/m32bcst
zmm3/m512/m32bcst
while shifting in 0s using writemask k1.
EVEX.128.66.0F38.W1 45 /r
C
V/V
AVX512VL
Shift quadwords in xmm2 right by amount specified in
VPSRLVQ xmm1 {k1}{z}, xmm2,
AVX512F
the corresponding element of xmm3/m128/m64bcst
xmm3/m128/m64bcst
while shifting in 0s using writemask k1.
EVEX.256.66.0F38.W1 45 /r
C
V/V
AVX512VL
Shift quadwords in ymm2 right by amount specified in
VPSRLVQ ymm1 {k1}{z}, ymm2,
AVX512F
the corresponding element of ymm3/m256/m64bcst
ymm3/m256/m64bcst
while shifting in 0s using writemask k1.
EVEX.512.66.0F38.W1 45 /r
C
V/V
AVX512F
Shift quadwords in zmm2 right by amount specified in
VPSRLVQ zmm1 {k1}{z}, zmm2,
the corresponding element of zmm3/m512/m64bcst
zmm3/m512/m64bcst
while shifting in 0s using writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
5-604
Vol. 2C
VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right Logical
INSTRUCTION SET REFERENCE, V
Description
Shifts the bits in the individual data elements (words, doublewords or quadword) in the first source operand to the
right by the count value of respective data elements in the second source operand. As the bits in the data elements
are shifted right, the empty high-order bits are cleared (set to 0).
The count values are specified individually in each data element of the second source operand. If the unsigned
integer value specified in the respective data element of the second source operand is greater than 15 (for word),
31 (for doublewords), or 63 (for a quadword), then the destination data element are written with 0.
VEX.128 encoded version: The destination and first source operands are XMM registers. The count operand can be
either an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding destination register
are zeroed.
VEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be
either an YMM register or a 256-bit memory. Bits (MAXVL-1:256) of the corresponding ZMM register are zeroed.
EVEX encoded VPSRLVD/Q: The destination and first source operands are ZMM/YMM/XMM registers. The count
operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512-bit vector broad-
casted from a 32/64-bit memory location. The destination is conditionally updated with writemask k1.
EVEX encoded VPSRLVW: The destination and first source operands are ZMM/YMM/XMM registers. The count
operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is condition-
ally updated with writemask k1.
Operation
VPSRLVW (EVEX encoded version)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF k1[j] OR *no writemask*
THEN DEST[i+15:i] := ZeroExtend(SRC1[i+15:i] >> SRC2[i+15:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+15:i] := 0
FI
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0;
VPSRLVD (VEX.128 version)
COUNT_0 := SRC2[31 : 0]
(* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 := SRC2[127 : 96];
IF COUNT_0 < 32 THEN
DEST[31:0] := ZeroExtend(SRC1[31:0] >> COUNT_0);
ELSE
DEST[31:0] := 0;
(* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 32 THEN
DEST[127:96] := ZeroExtend(SRC1[127:96] >> COUNT_3);
ELSE
DEST[127:96] := 0;
DEST[MAXVL-1:128] := 0;
VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right Logical
Vol. 2C
5-605
INSTRUCTION SET REFERENCE, V
VPSRLVD (VEX.256 version)
COUNT_0 := SRC2[31 : 0];
(* Repeat Each COUNT_i for the 2nd through 7th dwords of SRC2*)
COUNT_7 := SRC2[255 : 224];
IF COUNT_0 < 32 THEN
DEST[31:0] := ZeroExtend(SRC1[31:0] >> COUNT_0);
ELSE
DEST[31:0] := 0;
(* Repeat shift operation for 2nd through 7th dwords *)
IF COUNT_7 < 32 THEN
DEST[255:224] := ZeroExtend(SRC1[255:224] >> COUNT_7);
ELSE
DEST[255:224] := 0;
DEST[MAXVL-1:256] := 0;
VPSRLVD (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] := ZeroExtend(SRC1[i+31:i] >> SRC2[31:0])
ELSE DEST[i+31:i] := ZeroExtend(SRC1[i+31:i] >> SRC2[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0;
VPSRLVQ (VEX.128 version)
COUNT_0 := SRC2[63 : 0];
COUNT_1 := SRC2[127 : 64];
IF COUNT_0 < 64 THEN
DEST[63:0] := ZeroExtend(SRC1[63:0] >> COUNT_0);
ELSE
DEST[63:0] := 0;
IF COUNT_1 < 64 THEN
DEST[127:64] := ZeroExtend(SRC1[127:64] >> COUNT_1);
ELSE
DEST[127:64] := 0;
DEST[MAXVL-1:128] := 0;
5-606
Vol. 2C
VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right Logical
INSTRUCTION SET REFERENCE, V
VPSRLVQ (VEX.256 version)
COUNT_0 := SRC2[63 : 0];
(* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 := SRC2[255 : 192];
IF COUNT_0 < 64 THEN
DEST[63:0] := ZeroExtend(SRC1[63:0] >> COUNT_0);
ELSE
DEST[63:0] := 0;
(* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 64 THEN
DEST[255:192] := ZeroExtend(SRC1[255:192] >> COUNT_3);
ELSE
DEST[255:192] := 0;
DEST[MAXVL-1:256] := 0;
VPSRLVQ (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] := ZeroExtend(SRC1[i+63:i] >> SRC2[63:0])
ELSE DEST[i+63:i] := ZeroExtend(SRC1[i+63:i] >> SRC2[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0;
VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right Logical
Vol. 2C
5-607
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPSRLVW __m512i _mm512_srlv_epi16(__m512i a, __m512i cnt);
VPSRLVW __m512i _mm512_mask_srlv_epi16(__m512i s, __mmask32 k, __m512i a, __m512i cnt);
VPSRLVW __m512i _mm512_maskz_srlv_epi16( __mmask32 k, __m512i a, __m512i cnt);
VPSRLVW __m256i _mm256_mask_srlv_epi16(__m256i s, __mmask16 k, __m256i a, __m256i cnt);
VPSRLVW __m256i _mm256_maskz_srlv_epi16( __mmask16 k, __m256i a, __m256i cnt);
VPSRLVW __m128i _mm_mask_srlv_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLVW __m128i _mm_maskz_srlv_epi16( __mmask8 k, __m128i a, __m128i cnt);
VPSRLVW __m256i _mm256_srlv_epi32 (__m256i m, __m256i count)
VPSRLVD __m512i _mm512_srlv_epi32(__m512i a, __m512i cnt);
VPSRLVD __m512i _mm512_mask_srlv_epi32(__m512i s, __mmask16 k, __m512i a, __m512i cnt);
VPSRLVD __m512i _mm512_maskz_srlv_epi32( __mmask16 k, __m512i a, __m512i cnt);
VPSRLVD __m256i _mm256_mask_srlv_epi32(__m256i s, __mmask8 k, __m256i a, __m256i cnt);
VPSRLVD __m256i _mm256_maskz_srlv_epi32( __mmask8 k, __m256i a, __m256i cnt);
VPSRLVD __m128i _mm_mask_srlv_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLVD __m128i _mm_maskz_srlv_epi32( __mmask8 k, __m128i a, __m128i cnt);
VPSRLVQ __m512i _mm512_srlv_epi64(__m512i a, __m512i cnt);
VPSRLVQ __m512i _mm512_mask_srlv_epi64(__m512i s, __mmask8 k, __m512i a, __m512i cnt);
VPSRLVQ __m512i _mm512_maskz_srlv_epi64( __mmask8 k, __m512i a, __m512i cnt);
VPSRLVQ __m256i _mm256_mask_srlv_epi64(__m256i s, __mmask8 k, __m256i a, __m256i cnt);
VPSRLVQ __m256i _mm256_maskz_srlv_epi64( __mmask8 k, __m256i a, __m256i cnt);
VPSRLVQ __m128i _mm_mask_srlv_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLVQ __m128i _mm_maskz_srlv_epi64( __mmask8 k, __m128i a, __m128i cnt);
VPSRLVQ __m256i _mm256_srlv_epi64 (__m256i m, __m256i count)
VPSRLVD __m128i _mm_srlv_epi32( __m128i a, __m128i cnt);
VPSRLVQ __m128i _mm_srlv_epi64( __m128i a, __m128i cnt);
SIMD Floating-Point Exceptions
None.
Other Exceptions
VEX-encoded instructions, see Table 2-21, “Type 4 Class Exception Conditions.”
EVEX-encoded VPSRLVD/Q, see Table 2-49, “Type E4 Class Exception Conditions.”
EVEX-encoded VPSRLVW, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”
5-608
Vol. 2C
VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right Logical
INSTRUCTION SET REFERENCE, V
VPTERNLOGD/VPTERNLOGQ—Bitwise Ternary Logic
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F3A.W0 25 /r ib
A
V/V
AVX512VL
Bitwise ternary logic taking xmm1, xmm2, and
VPTERNLOGD xmm1 {k1}{z}, xmm2,
AVX512F
xmm3/m128/m32bcst as source operands and writing
xmm3/m128/m32bcst, imm8
the result to xmm1 under writemask k1 with dword
granularity. The immediate value determines the specific
binary function being implemented.
EVEX.256.66.0F3A.W0 25 /r ib
A
V/V
AVX512VL
Bitwise ternary logic taking ymm1, ymm2, and
VPTERNLOGD ymm1 {k1}{z}, ymm2,
AVX512F
ymm3/m256/m32bcst as source operands and writing
ymm3/m256/m32bcst, imm8
the result to ymm1 under writemask k1 with dword
granularity. The immediate value determines the specific
binary function being implemented.
EVEX.512.66.0F3A.W0 25 /r ib
A
V/V
AVX512F
Bitwise ternary logic taking zmm1, zmm2, and
VPTERNLOGD zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst as source operands and writing
zmm3/m512/m32bcst, imm8
the result to zmm1 under writemask k1 with dword
granularity. The immediate value determines the specific
binary function being implemented.
EVEX.128.66.0F3A.W1 25 /r ib
A
V/V
AVX512VL
Bitwise ternary logic taking xmm1, xmm2, and
VPTERNLOGQ xmm1 {k1}{z}, xmm2,
AVX512F
xmm3/m128/m64bcst as source operands and writing
xmm3/m128/m64bcst, imm8
the result to xmm1 under writemask k1 with qword
granularity. The immediate value determines the specific
binary function being implemented.
EVEX.256.66.0F3A.W1 25 /r ib
A
V/V
AVX512VL
Bitwise ternary logic taking ymm1, ymm2, and
VPTERNLOGQ ymm1 {k1}{z}, ymm2,
AVX512F
ymm3/m256/m64bcst as source operands and writing
ymm3/m256/m64bcst, imm8
the result to ymm1 under writemask k1 with qword
granularity. The immediate value determines the specific
binary function being implemented.
EVEX.512.66.0F3A.W1 25 /r ib
A
V/V
AVX512F
Bitwise ternary logic taking zmm1, zmm2, and
VPTERNLOGQ zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst as source operands and writing
zmm3/m512/m64bcst, imm8
the result to zmm1 under writemask k1 with qword
granularity. The immediate value determines the specific
binary function being implemented.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
VPTERNLOGD/Q takes three bit vectors of 512-bit length (in the first, second, and third operand) as input data to
form a set of 512 indices, each index is comprised of one bit from each input vector. The imm8 byte specifies a
boolean logic table producing a binary value for each 3-bit index value. The final 512-bit boolean result is written
to the destination operand (the first operand) using the writemask k1 with the granularity of doubleword element
or quadword element into the destination.
The destination operand is a ZMM (EVEX.512)/YMM (EVEX.256)/XMM (EVEX.128) register. The first source
operand is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a
512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location The
destination operand is a ZMM register conditionally updated with writemask k1.
VPTERNLOGD/VPTERNLOGQ—Bitwise Ternary Logic
Vol. 2C
5-609
INSTRUCTION SET REFERENCE, V
Table 5-12 shows two examples of Boolean functions specified by immediate values 0xE2 and 0xE4, with the look
up result listed in the fourth column following the three columns containing all possible values of the 3-bit index.
Table 5-12. Examples of VPTERNLOGD/Q Imm8 Boolean Function and Input Index Values
VPTERNLOGD reg1, reg2, src3, 0xE2
Bit Result with
VPTERNLOGD reg1, reg2, src3, 0xE4
Bit Result with
Imm8=0xE2
Imm8=0xE4
Bit(reg1)
Bit(reg2)
Bit(src3)
Bit(reg1)
Bit(reg2)
Bit(src3)
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
Specifying different values in imm8 will allow any arbitrary three-input Boolean functions to be implemented in
software using VPTERNLOGD/Q. Table 5-1 and Table 5-2 provide a mapping of all 256 possible imm8 values to
various Boolean expressions.
Operation
VPTERNLOGD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN
FOR k := 0 TO 31
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[j][k] := imm[(DEST[i+k] << 2) + (SRC1[ i+k ] << 1) + SRC2[ k ]]
ELSE DEST[j][k] := imm[(DEST[i+k] << 2) + (SRC1[ i+k ] << 1) + SRC2[ i+k ]]
FI;
; table lookup of immediate bellow;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31+i:i] remains unchanged*
ELSE
; zeroing-masking
DEST[31+i:i] := 0
FI;
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0
5-610
Vol. 2C
VPTERNLOGD/VPTERNLOGQ—Bitwise Ternary Logic
INSTRUCTION SET REFERENCE, V
VPTERNLOGQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
FOR k := 0 TO 63
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[j][k] := imm[(DEST[i+k] << 2) + (SRC1[ i+k ] << 1) + SRC2[ k ]]
ELSE DEST[j][k] := imm[(DEST[i+k] << 2) + (SRC1[ i+k ] << 1) + SRC2[ i+k ]]
FI;
; table lookup of immediate bellow;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63+i:i] remains unchanged*
ELSE
; zeroing-masking
DEST[63+i:i] := 0
FI;
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalents
VPTERNLOGD __m512i _mm512_ternarylogic_epi32(__m512i a, __m512i b, int imm);
VPTERNLOGD __m512i _mm512_mask_ternarylogic_epi32(__m512i s, __mmask16 m, __m512i a, __m512i b, int imm);
VPTERNLOGD __m512i _mm512_maskz_ternarylogic_epi32(__mmask m, __m512i a, __m512i b, int imm);
VPTERNLOGD __m256i _mm256_ternarylogic_epi32(__m256i a, __m256i b, int imm);
VPTERNLOGD __m256i _mm256_mask_ternarylogic_epi32(__m256i s, __mmask8 m, __m256i a, __m256i b, int imm);
VPTERNLOGD __m256i _mm256_maskz_ternarylogic_epi32( __mmask8 m, __m256i a, __m256i b, int imm);
VPTERNLOGD __m128i _mm_ternarylogic_epi32(__m128i a, __m128i b, int imm);
VPTERNLOGD __m128i _mm_mask_ternarylogic_epi32(__m128i s, __mmask8 m, __m128i a, __m128i b, int imm);
VPTERNLOGD __m128i _mm_maskz_ternarylogic_epi32( __mmask8 m, __m128i a, __m128i b, int imm);
VPTERNLOGQ __m512i _mm512_ternarylogic_epi64(__m512i a, __m512i b, int imm);
VPTERNLOGQ __m512i _mm512_mask_ternarylogic_epi64(__m512i s, __mmask8 m, __m512i a, __m512i b, int imm);
VPTERNLOGQ __m512i _mm512_maskz_ternarylogic_epi64( __mmask8 m, __m512i a, __m512i b, int imm);
VPTERNLOGQ __m256i _mm256_ternarylogic_epi64(__m256i a, __m256i b, int imm);
VPTERNLOGQ __m256i _mm256_mask_ternarylogic_epi64(__m256i s, __mmask8 m, __m256i a, __m256i b, int imm);
VPTERNLOGQ __m256i _mm256_maskz_ternarylogic_epi64( __mmask8 m, __m256i a, __m256i b, int imm);
VPTERNLOGQ __m128i _mm_ternarylogic_epi64(__m128i a, __m128i b, int imm);
VPTERNLOGQ __m128i _mm_mask_ternarylogic_epi64(__m128i s, __mmask8 m, __m128i a, __m128i b, int imm);
VPTERNLOGQ __m128i _mm_maskz_ternarylogic_epi64( __mmask8 m, __m128i a, __m128i b, int imm);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-49, “Type E4 Class Exception Conditions.”
VPTERNLOGD/VPTERNLOGQ—Bitwise Ternary Logic
Vol. 2C
5-611
INSTRUCTION SET REFERENCE, V
VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set Mask
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W0 26 /r
A
V/V
AVX512VL
Bitwise AND of packed byte integers in xmm2 and
VPTESTMB k2 {k1}, xmm2,
AVX512BW
xmm3/m128 and set mask k2 to reflect the zero/non-zero
xmm3/m128
status of each element of the result, under writemask k1.
EVEX.256.66.0F38.W0 26 /r
A
V/V
AVX512VL
Bitwise AND of packed byte integers in ymm2 and
VPTESTMB k2 {k1}, ymm2,
AVX512BW
ymm3/m256 and set mask k2 to reflect the zero/non-zero
ymm3/m256
status of each element of the result, under writemask k1.
EVEX.512.66.0F38.W0 26 /r
A
V/V
AVX512BW
Bitwise AND of packed byte integers in zmm2 and
VPTESTMB k2 {k1}, zmm2,
zmm3/m512 and set mask k2 to reflect the zero/non-zero
zmm3/m512
status of each element of the result, under writemask k1.
EVEX.128.66.0F38.W1 26 /r
A
V/V
AVX512VL
Bitwise AND of packed word integers in xmm2 and
VPTESTMW k2 {k1}, xmm2,
AVX512BW
xmm3/m128 and set mask k2 to reflect the zero/non-zero
xmm3/m128
status of each element of the result, under writemask k1.
EVEX.256.66.0F38.W1 26 /r
A
V/V
AVX512VL
Bitwise AND of packed word integers in ymm2 and
VPTESTMW k2 {k1}, ymm2,
AVX512BW
ymm3/m256 and set mask k2 to reflect the zero/non-zero
ymm3/m256
status of each element of the result, under writemask k1.
EVEX.512.66.0F38.W1 26 /r
A
V/V
AVX512BW
Bitwise AND of packed word integers in zmm2 and
VPTESTMW k2 {k1}, zmm2,
zmm3/m512 and set mask k2 to reflect the zero/non-zero
zmm3/m512
status of each element of the result, under writemask k1.
EVEX.128.66.0F38.W0 27 /r
B
V/V
AVX512VL
Bitwise AND of packed doubleword integers in xmm2 and
VPTESTMD k2 {k1}, xmm2,
AVX512F
xmm3/m128/m32bcst and set mask k2 to reflect the
xmm3/m128/m32bcst
zero/non-zero status of each element of the result, under
writemask k1.
EVEX.256.66.0F38.W0 27 /r
B
V/V
AVX512VL
Bitwise AND of packed doubleword integers in ymm2 and
VPTESTMD k2 {k1}, ymm2,
AVX512F
ymm3/m256/m32bcst and set mask k2 to reflect the
ymm3/m256/m32bcst
zero/non-zero status of each element of the result, under
writemask k1.
EVEX.512.66.0F38.W0 27 /r
B
V/V
AVX512F
Bitwise AND of packed doubleword integers in zmm2 and
VPTESTMD k2 {k1}, zmm2,
zmm3/m512/m32bcst and set mask k2 to reflect the
zmm3/m512/m32bcst
zero/non-zero status of each element of the result, under
writemask k1.
EVEX.128.66.0F38.W1 27 /r
B
V/V
AVX512VL
Bitwise AND of packed quadword integers in xmm2 and
VPTESTMQ k2 {k1}, xmm2,
AVX512F
xmm3/m128/m64bcst and set mask k2 to reflect the
xmm3/m128/m64bcst
zero/non-zero status of each element of the result, under
writemask k1.
EVEX.256.66.0F38.W1 27 /r
B
V/V
AVX512VL
Bitwise AND of packed quadword integers in ymm2 and
VPTESTMQ k2 {k1}, ymm2,
AVX512F
ymm3/m256/m64bcst and set mask k2 to reflect the
ymm3/m256/m64bcst
zero/non-zero status of each element of the result, under
writemask k1.
EVEX.512.66.0F38.W1 27 /r
B
V/V
AVX512F
Bitwise AND of packed quadword integers in zmm2 and
VPTESTMQ k2 {k1}, zmm2,
zmm3/m512/m64bcst and set mask k2 to reflect the
zmm3/m512/m64bcst
zero/non-zero status of each element of the result, under
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
5-612
Vol. 2C
VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set Mask
INSTRUCTION SET REFERENCE, V
Description
Performs a bitwise logical AND operation on the first source operand (the second operand) and second source
operand (the third operand) and stores the result in the destination operand (the first operand) under the
writemask. Each bit of the result is set to 1 if the bitwise AND of the corresponding elements of the first and second
src operands is non-zero; otherwise it is set to 0.
VPTESTMD/VPTESTMQ: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is a mask register updated under the writemask.
VPTESTMB/VPTESTMW: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is a mask register
updated under the writemask.
Operation
VPTESTMB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1
i := j * 8
IF k1[j] OR *no writemask*
THEN DEST[j] := (SRC1[i+7:i] BITWISE AND SRC2[i+7:i] != 0)? 1 : 0;
ELSE
DEST[j] = 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPTESTMW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j * 16
IF k1[j] OR *no writemask*
THEN DEST[j] := (SRC1[i+15:i] BITWISE AND SRC2[i+15:i] != 0)? 1 : 0;
ELSE
DEST[j] = 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPTESTMD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[j] := (SRC1[i+31:i] BITWISE AND SRC2[31:0] != 0)? 1 : 0;
ELSE DEST[j] := (SRC1[i+31:i] BITWISE AND SRC2[i+31:i] != 0)? 1 : 0;
FI;
ELSE
DEST[j] := 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set Mask
Vol. 2C
5-613
INSTRUCTION SET REFERENCE, V
VPTESTMQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[j] := (SRC1[i+63:i] BITWISE AND SRC2[63:0] != 0)? 1 : 0;
ELSE DEST[j] := (SRC1[i+63:i] BITWISE AND SRC2[i+63:i] != 0)? 1 : 0;
FI;
ELSE
DEST[j] := 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
Intel C/C++ Compiler Intrinsic Equivalents
VPTESTMB __mmask64 _mm512_test_epi8_mask( __m512i a, __m512i b);
VPTESTMB __mmask64 _mm512_mask_test_epi8_mask(__mmask64, __m512i a, __m512i b);
VPTESTMW __mmask32 _mm512_test_epi16_mask( __m512i a, __m512i b);
VPTESTMW __mmask32 _mm512_mask_test_epi16_mask(__mmask32, __m512i a, __m512i b);
VPTESTMD __mmask16 _mm512_test_epi32_mask( __m512i a, __m512i b);
VPTESTMD __mmask16 _mm512_mask_test_epi32_mask(__mmask16, __m512i a, __m512i b);
VPTESTMQ __mmask8 _mm512_test_epi64_mask(__m512i a, __m512i b);
VPTESTMQ __mmask8 _mm512_mask_test_epi64_mask(__mmask8, __m512i a, __m512i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
VPTESTMD/Q: See Table 2-49, “Type E4 Class Exception Conditions.”
VPTESTMB/W: See Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”
5-614
Vol. 2C
VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set Mask
INSTRUCTION SET REFERENCE, V
VPTESTNMB/W/D/Q—Logical NAND and Set
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Support
EVEX.128.F3.0F38.W0 26 /r
A
V/V
AVX512VL
Bitwise NAND of packed byte integers in xmm2 and
VPTESTNMB k2 {k1}, xmm2,
AVX512BW
xmm3/m128 and set mask k2 to reflect the zero/non-zero
xmm3/m128
status of each element of the result, under writemask k1.
EVEX.256.F3.0F38.W0 26 /r
A
V/V
AVX512VL
Bitwise NAND of packed byte integers in ymm2 and
VPTESTNMB k2 {k1}, ymm2,
AVX512BW
ymm3/m256 and set mask k2 to reflect the zero/non-zero
ymm3/m256
status of each element of the result, under writemask k1.
EVEX.512.F3.0F38.W0 26 /r
A
V/V
AVX512F
Bitwise NAND of packed byte integers in zmm2 and
VPTESTNMB k2 {k1}, zmm2,
AVX512BW
zmm3/m512 and set mask k2 to reflect the zero/non-zero
zmm3/m512
status of each element of the result, under writemask k1.
EVEX.128.F3.0F38.W1 26 /r
A
V/V
AVX512VL
Bitwise NAND of packed word integers in xmm2 and
VPTESTNMW k2 {k1}, xmm2,
AVX512BW
xmm3/m128 and set mask k2 to reflect the zero/non-zero
xmm3/m128
status of each element of the result, under writemask k1.
EVEX.256.F3.0F38.W1 26 /r
A
V/V
AVX512VL
Bitwise NAND of packed word integers in ymm2 and
VPTESTNMW k2 {k1}, ymm2,
AVX512BW
ymm3/m256 and set mask k2 to reflect the zero/non-zero
ymm3/m256
status of each element of the result, under writemask k1.
EVEX.512.F3.0F38.W1 26 /r
A
V/V
AVX512F
Bitwise NAND of packed word integers in zmm2 and
VPTESTNMW k2 {k1}, zmm2,
AVX512BW
zmm3/m512 and set mask k2 to reflect the zero/non-zero
zmm3/m512
status of each element of the result, under writemask k1.
EVEX.128.F3.0F38.W0 27 /r
B
V/V
AVX512VL
Bitwise NAND of packed doubleword integers in xmm2 and
VPTESTNMD k2 {k1}, xmm2,
AVX512F
xmm3/m128/m32bcst and set mask k2 to reflect the
xmm3/m128/m32bcst
zero/non-zero status of each element of the result, under
writemask k1.
EVEX.256.F3.0F38.W0 27 /r
B
V/V
AVX512VL
Bitwise NAND of packed doubleword integers in ymm2 and
VPTESTNMD k2 {k1}, ymm2,
AVX512F
ymm3/m256/m32bcst and set mask k2 to reflect the
ymm3/m256/m32bcst
zero/non-zero status of each element of the result, under
writemask k1.
EVEX.512.F3.0F38.W0 27 /r
B
V/V
AVX512F
Bitwise NAND of packed doubleword integers in zmm2 and
VPTESTNMD k2 {k1}, zmm2,
zmm3/m512/m32bcst and set mask k2 to reflect the
zmm3/m512/m32bcst
zero/non-zero status of each element of the result, under
writemask k1.
EVEX.128.F3.0F38.W1 27 /r
B
V/V
AVX512VL
Bitwise NAND of packed quadword integers in xmm2 and
VPTESTNMQ k2 {k1}, xmm2,
AVX512F
xmm3/m128/m64bcst and set mask k2 to reflect the
xmm3/m128/m64bcst
zero/non-zero status of each element of the result, under
writemask k1.
EVEX.256.F3.0F38.W1 27 /r
B
V/V
AVX512VL
Bitwise NAND of packed quadword integers in ymm2 and
VPTESTNMQ k2 {k1}, ymm2,
AVX512F
ymm3/m256/m64bcst and set mask k2 to reflect the
ymm3/m256/m64bcst
zero/non-zero status of each element of the result, under
writemask k1.
EVEX.512.F3.0F38.W1 27 /r
B
V/V
AVX512F
Bitwise NAND of packed quadword integers in zmm2 and
VPTESTNMQ k2 {k1}, zmm2,
zmm3/m512/m64bcst and set mask k2 to reflect the
zmm3/m512/m64bcst
zero/non-zero status of each element of the result, under
writemask k1.
VPTESTNMB/W/D/Q—Logical NAND and Set
Vol. 2C
5-615
INSTRUCTION SET REFERENCE, V
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Performs a bitwise logical NAND operation on the byte/word/doubleword/quadword element of the first source
operand (the second operand) with the corresponding element of the second source operand (the third operand)
and stores the logical comparison result into each bit of the destination operand (the first operand) according to the
writemask k1. Each bit of the result is set to 1 if the bitwise AND of the corresponding elements of the first and
second src operands is zero; otherwise it is set to 0.
EVEX encoded VPTESTNMD/Q: The first source operand is a ZMM/YMM/XMM registers. The second source operand
can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted
from a 32/64-bit memory location. The destination is updated according to the writemask.
EVEX encoded VPTESTNMB/W: The first source operand is a ZMM/YMM/XMM registers. The second source operand
can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is updated according to the
writemask.
Operation
VPTESTNMB
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j := 0 TO KL-1
i := j*8
IF MaskBit(j) OR *no writemask*
THEN
DEST[j] := (SRC1[i+7:i] BITWISE AND SRC2[i+7:i] == 0)? 1 : 0
ELSE DEST[j] := 0; zeroing masking only
FI
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPTESTNMW
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j := 0 TO KL-1
i := j*16
IF MaskBit(j) OR *no writemask*
THEN
DEST[j] := (SRC1[i+15:i] BITWISE AND SRC2[i+15:i] == 0)? 1 : 0
ELSE DEST[j] := 0; zeroing masking only
FI
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPTESTNMD
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j*32
IF MaskBit(j) OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] := (SRC1[i+31:i] BITWISE AND SRC2[31:0] == 0)? 1 : 0
ELSE DEST[j] := (SRC1[i+31:i] BITWISE AND SRC2[i+31:i] == 0)? 1 : 0
FI
5-616
Vol. 2C
VPTESTNMB/W/D/Q—Logical NAND and Set
INSTRUCTION SET REFERENCE, V
ELSE DEST[j] := 0; zeroing masking only
FI
ENDFOR
DEST[MAX_KL-1:KL] := 0
VPTESTNMQ
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j*64
IF MaskBit(j) OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN DEST[j] := (SRC1[i+63:i] BITWISE AND SRC2[63:0] == 0)? 1 : 0;
ELSE DEST[j] := (SRC1[i+63:i] BITWISE AND SRC2[i+63:i] == 0)? 1 : 0;
FI;
ELSE DEST[j] := 0; zeroing masking only
FI
ENDFOR
DEST[MAX_KL-1:KL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPTESTNMB __mmask64 _mm512_testn_epi8_mask( __m512i a, __m512i b);
VPTESTNMB __mmask64 _mm512_mask_testn_epi8_mask(__mmask64, __m512i a, __m512i b);
VPTESTNMB __mmask32 _mm256_testn_epi8_mask(__m256i a, __m256i b);
VPTESTNMB __mmask32 _mm256_mask_testn_epi8_mask(__mmask32, __m256i a, __m256i b);
VPTESTNMB __mmask16 _mm_testn_epi8_mask(__m128i a, __m128i b);
VPTESTNMB __mmask16 _mm_mask_testn_epi8_mask(__mmask16, __m128i a, __m128i b);
VPTESTNMW __mmask32 _mm512_testn_epi16_mask( __m512i a, __m512i b);
VPTESTNMW __mmask32 _mm512_mask_testn_epi16_mask(__mmask32, __m512i a, __m512i b);
VPTESTNMW __mmask16 _mm256_testn_epi16_mask(__m256i a, __m256i b);
VPTESTNMW __mmask16 _mm256_mask_testn_epi16_mask(__mmask16, __m256i a, __m256i b);
VPTESTNMW __mmask8 _mm_testn_epi16_mask(__m128i a, __m128i b);
VPTESTNMW __mmask8 _mm_mask_testn_epi16_mask(__mmask8, __m128i a, __m128i b);
VPTESTNMD __mmask16 _mm512_testn_epi32_mask( __m512i a, __m512i b);
VPTESTNMD __mmask16 _mm512_mask_testn_epi32_mask(__mmask16, __m512i a, __m512i b);
VPTESTNMD __mmask8 _mm256_testn_epi32_mask(__m256i a, __m256i b);
VPTESTNMD __mmask8 _mm256_mask_testn_epi32_mask(__mmask8, __m256i a, __m256i b);
VPTESTNMD __mmask8 _mm_testn_epi32_mask(__m128i a, __m128i b);
VPTESTNMD __mmask8 _mm_mask_testn_epi32_mask(__mmask8, __m128i a, __m128i b);
VPTESTNMQ __mmask8 _mm512_testn_epi64_mask(__m512i a, __m512i b);
VPTESTNMQ __mmask8 _mm512_mask_testn_epi64_mask(__mmask8, __m512i a, __m512i b);
VPTESTNMQ __mmask8 _mm256_testn_epi64_mask(__m256i a, __m256i b);
VPTESTNMQ __mmask8 _mm256_mask_testn_epi64_mask(__mmask8, __m256i a, __m256i b);
VPTESTNMQ __mmask8 _mm_testn_epi64_mask(__m128i a, __m128i b);
VPTESTNMQ __mmask8 _mm_mask_testn_epi64_mask(__mmask8, __m128i a, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
VPTESTNMD/VPTESTNMQ: See Table 2-49, “Type E4 Class Exception Conditions.”
VPTESTNMB/VPTESTNMW: See Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”
VPTESTNMB/W/D/Q—Logical NAND and Set
Vol. 2C
5-617
INSTRUCTION SET REFERENCE, V
VRANGEPD—Range Restriction Calculation for Packed Pairs of Float64 Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F3A.W1 50 /r ib
A
V/V
AVX512VL
Calculate two RANGE operation output value from 2 pairs
VRANGEPD xmm1 {k1}{z}, xmm2,
AVX512DQ
of double precision floating-point values in xmm2 and
xmm3/m128/m64bcst, imm8
xmm3/m128/m32bcst, store the results to xmm1 under
the writemask k1. Imm8 specifies the comparison and sign
of the range operation.
EVEX.256.66.0F3A.W1 50 /r ib
A
V/V
AVX512VL
Calculate four RANGE operation output value from 4pairs
VRANGEPD ymm1 {k1}{z}, ymm2,
AVX512DQ
of double precision floating-point values in ymm2 and
ymm3/m256/m64bcst, imm8
ymm3/m256/m32bcst, store the results to ymm1 under
the writemask k1. Imm8 specifies the comparison and sign
of the range operation.
EVEX.512.66.0F3A.W1 50 /r ib
A
V/V
AVX512DQ
Calculate eight RANGE operation output value from 8
VRANGEPD zmm1 {k1}{z}, zmm2,
pairs of double precision floating-point values in zmm2
zmm3/m512/m64bcst{sae}, imm8
and zmm3/m512/m32bcst, store the results to zmm1
under the writemask k1. Imm8 specifies the comparison
and sign of the range operation.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
This instruction calculates 2/4/8 range operation outputs from two sets of packed input double precision floating-
point values in the first source operand (the second operand) and the second source operand (the third operand).
The range outputs are written to the destination operand (the first operand) under the writemask k1.
Bits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a
two-bit control field within imm8[3:0]:
• Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min
absolute value of the input value pair. Each comparison of two input values produces an intermediate result that
combines with the sign selection control (imm8[3:2]) to determine the final range operation output.
• Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input
value, from the comparison result, set or clear.
The encodings of imm8[1:0] and imm8[3:2] are shown in Figure 5-27.
7
6
5
4
3
2
1
0
imm8
Must Be Zero
Sign Control (SC)
Compare Operation Select
Imm8[1:0] = 00b : Select Min value
Imm8[3:2] = 00b : Select sign(SRC1)
Imm8[1:0] = 01b : Select Max value
Imm8[3:2] = 01b : Select sign(Compare_Result)
Imm8[1:0] = 10b : Select Min-Abs value
Imm8[3:2] = 10b : Set sign to 0
Imm8[1:0] = 11b : Select Max-Abs value
Imm8[3:2] = 11b : Set sign to 1
Figure 5-27. Imm8 Controls for VRANGEPD/SD/PS/SS
5-618
Vol. 2C
VRANGEPD—Range Restriction Calculation for Packed Pairs of Float64 Values
INSTRUCTION SET REFERENCE, V
When one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details
with one of more input value is NAN is listed in Table 5-13. If the comparison raises an IE, the sign select control
(imm8[3:2]) has no effect to the range operation output; this is indicated also in Table 5-13.
When both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare
operation is slightly different from the conceptually similar floating-point MIN/MAX operation that are found in the
instructions VMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS
for magnitude-0, opposite-signed input cases are listed in Table 5-14.
Additionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS compar-
ison operation with result listed in Table 5-15.
Table 5-13. Signaling of Comparison Operation of One or More NaN Input Values and Effect of Imm8[3:2]
Src1
Src2
Result
IE Signaling Due to Comparison
Imm8[3:2] Effect to Range Output
sNaN1
sNaN2
Quiet(sNaN1)
Yes
Ignored
sNaN1
qNaN2
Quiet(sNaN1)
Yes
Ignored
sNaN1
Norm2
Quiet(sNaN1)
Yes
Ignored
qNaN1
sNaN2
Quiet(sNaN2)
Yes
Ignored
qNaN1
qNaN2
qNaN1
No
Applicable
qNaN1
Norm2
Norm2
No
Applicable
Norm1
sNaN2
Quiet(sNaN2)
Yes
Ignored
Norm1
qNaN2
Norm1
No
Applicable
Table 5-14. Comparison Result for Opposite-Signed Zero Cases for MIN, MIN_ABS, and MAX, MAX_ABS
MIN and MIN_ABS
MAX and MAX_ABS
Src1
Src2
Result
Src1
Src2
Result
+0
-0
-0
+0
-0
+0
-0
+0
-0
-0
+0
+0
Table 5-15. Comparison Result of Equal-Magnitude Input Cases for MIN_ABS and MAX_ABS, (|a| = |b|, a>0, b<0)
MIN_ABS (|a| = |b|, a>0, b<0)
MAX_ABS (|a| = |b|, a>0, b<0)
Src1
Src2
Result
Src1
Src2
Result
a
b
b
a
b
a
b
a
b
b
a
a
Operation
RangeDP(SRC1[63:0], SRC2[63:0], CmpOpCtl[1:0], SignSelCtl[1:0])
{
// Check if SNAN and report IE, see also Table 5-13
IF (SRC1 = SNAN) THEN RETURN (QNAN(SRC1), set IE);
IF (SRC2 = SNAN) THEN RETURN (QNAN(SRC2), set IE);
Src1.exp := SRC1[62:52];
Src1.fraction := SRC1[51:0];
IF ((Src1.exp = 0 ) and (Src1.fraction != 0)) THEN// Src1 is a denormal number
IF DAZ THEN Src1.fraction := 0;
ELSE IF (SRC2 <> QNAN) Set DE; FI;
FI;
VRANGEPD—Range Restriction Calculation for Packed Pairs of Float64 Values
Vol. 2C
5-619
INSTRUCTION SET REFERENCE, V
Src2.exp := SRC2[62:52];
Src2.fraction := SRC2[51:0];
IF ((Src2.exp = 0) and (Src2.fraction !=0 )) THEN// Src2 is a denormal number
IF DAZ THEN Src2.fraction := 0;
ELSE IF (SRC1 <> QNAN) Set DE; FI;
FI;
IF
(SRC2 = QNAN) THEN{TMP[63:0] := SRC1[63:0]}
ELSE IF(SRC1 = QNAN) THEN{TMP[63:0] := SRC2[63:0]}
ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[63:0] := from Table 5-14
ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-signed and CmpOpCtl[1:0] > 01) TMP[63:0] := from Table 5-15
ELSE
Case(CmpOpCtl[1:0])
00: TMP[63:0] := (SRC1[63:0] ≤ SRC2[63:0]) ? SRC1[63:0] : SRC2[63:0];
01: TMP[63:0] := (SRC1[63:0] ≤ SRC2[63:0]) ? SRC2[63:0] : SRC1[63:0];
10: TMP[63:0] := (ABS(SRC1[63:0]) ≤ ABS(SRC2[63:0])) ? SRC1[63:0] : SRC2[63:0];
11: TMP[63:0] := (ABS(SRC1[63:0]) ≤ ABS(SRC2[63:0])) ? SRC2[63:0] : SRC1[63:0];
ESAC;
FI;
Case(SignSelCtl[1:0])
00: dest := (SRC1[63] << 63) OR (TMP[62:0]);// Preserve Src1 sign bit
01: dest := TMP[63:0];// Preserve sign of compare result
10: dest := (0 << 63) OR (TMP[62:0]);// Zero out sign bit
11: dest := (1 << 63) OR (TMP[62:0]);// Set the sign bit
ESAC;
RETURN dest[63:0];
}
CmpOpCtl[1:0]= imm8[1:0];
SignSelCtl[1:0]=imm8[3:2];
VRANGEPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask* THEN
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN DEST[i+63:i] := RangeDP (SRC1[i+63:i], SRC2[63:0], CmpOpCtl[1:0], SignSelCtl[1:0]);
ELSE DEST[i+63:i] := RangeDP (SRC1[i+63:i], SRC2[i+63:i], CmpOpCtl[1:0], SignSelCtl[1:0]);
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] = 0
FI;
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0
The following example describes a common usage of this instruction for checking that the input operand is bound-
ed between ±1023.
5-620
Vol. 2C
VRANGEPD—Range Restriction Calculation for Packed Pairs of Float64 Values
INSTRUCTION SET REFERENCE, V
VRANGEPD zmm_dst, zmm_src, zmm_1023, 02h;
Where:
zmm_dst is the destination operand.
zmm_src is the input operand to compare against ±1023 (this is SRC1).
zmm_1023 is the reference operand, contains the value of 1023 (and this is SRC2).
IMM=02(imm8[1:0]='10) selects the Min Absolute value operation with selection of SRC1.sign.
In case |zmm_src| < 1023 (i.e., SRC1 is smaller than 1023 in magnitude), then its value will be written into
zmm_dst. Otherwise, the value stored in zmm_dst will get the value of 1023 (received on zmm_1023, which is
SRC2).
However, the sign control (imm8[3:2]='00) instructs to select the sign of SRC1 received from zmm_src. So, even
in the case of |zmm_src| ≥ 1023, the selected sign of SRC1 is kept.
Thus, if zmm_src < -1023, the result of VRANGEPD will be the minimal value of -1023 while if zmm_src > +1023,
the result of VRANGE will be the maximal value of +1023.
Intel C/C++ Compiler Intrinsic Equivalent
VRANGEPD __m512d _mm512_range_pd ( __m512d a, __m512d b, int imm);
VRANGEPD __m512d _mm512_range_round_pd ( __m512d a, __m512d b, int imm, int sae);
VRANGEPD __m512d _mm512_mask_range_pd (__m512 ds, __mmask8 k, __m512d a, __m512d b, int imm);
VRANGEPD __m512d _mm512_mask_range_round_pd (__m512d s, __mmask8 k, __m512d a, __m512d b, int imm, int sae);
VRANGEPD __m512d _mm512_maskz_range_pd ( __mmask8 k, __m512d a, __m512d b, int imm);
VRANGEPD __m512d _mm512_maskz_range_round_pd ( __mmask8 k, __m512d a, __m512d b, int imm, int sae);
VRANGEPD __m256d _mm256_range_pd ( __m256d a, __m256d b, int imm);
VRANGEPD __m256d _mm256_mask_range_pd (__m256d s, __mmask8 k, __m256d a, __m256d b, int imm);
VRANGEPD __m256d _mm256_maskz_range_pd ( __mmask8 k, __m256d a, __m256d b, int imm);
VRANGEPD __m128d _mm_range_pd ( __m128 a, __m128d b, int imm);
VRANGEPD __m128d _mm_mask_range_pd (__m128 s, __mmask8 k, __m128d a, __m128d b, int imm);
VRANGEPD __m128d _mm_maskz_range_pd ( __mmask8 k, __m128d a, __m128d b, int imm);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
See Table 2-46, “Type E2 Class Exception Conditions.”
VRANGEPD—Range Restriction Calculation for Packed Pairs of Float64 Values
Vol. 2C
5-621
INSTRUCTION SET REFERENCE, V
VRANGEPS—Range Restriction Calculation for Packed Pairs of Float32 Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F3A.W0 50 /r ib
A
V/V
AVX512VL
Calculate four RANGE operation output value from 4 pairs
VRANGEPS xmm1 {k1}{z}, xmm2,
AVX512DQ
of single-precision floating-point values in xmm2 and
xmm3/m128/m32bcst, imm8
xmm3/m128/m32bcst, store the results to xmm1 under
the writemask k1. Imm8 specifies the comparison and sign
of the range operation.
EVEX.256.66.0F3A.W0 50 /r ib
A
V/V
AVX512VL
Calculate eight RANGE operation output value from 8 pairs
VRANGEPS ymm1 {k1}{z}, ymm2,
AVX512DQ
of single-precision floating-point values in ymm2 and
ymm3/m256/m32bcst, imm8
ymm3/m256/m32bcst, store the results to ymm1 under
the writemask k1. Imm8 specifies the comparison and sign
of the range operation.
EVEX.512.66.0F3A.W0 50 /r ib
A
V/V
AVX512DQ
Calculate 16 RANGE operation output value from 16 pairs
VRANGEPS zmm1 {k1}{z}, zmm2,
of single-precision floating-point values in zmm2 and
zmm3/m512/m32bcst{sae}, imm8
zmm3/m512/m32bcst, store the results to zmm1 under
the writemask k1. Imm8 specifies the comparison and sign
of the range operation.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
This instruction calculates 4/8/16 range operation outputs from two sets of packed input single-precision floating-
point values in the first source operand (the second operand) and the second source operand (the third operand).
The range outputs are written to the destination operand (the first operand) under the writemask k1.
Bits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a
two-bit control field within imm8[3:0]:
• Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min
absolute value of the input value pair. Each comparison of two input values produces an intermediate result that
combines with the sign selection control (imm8[3:2]) to determine the final range operation output.
• Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input
value, from the comparison result, set or clear.
The encodings of imm8[1:0] and imm8[3:2] are shown in Figure 5-27.
When one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details
with one of more input value is NAN is listed in Table 5-13. If the comparison raises an IE, the sign select control
(imm8[3:2]) has no effect to the range operation output; this is indicated also in Table 5-13.
When both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare
operation is slightly different from the conceptually similar floating-point MIN/MAX operation that are found in the
instructions VMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS
for magnitude-0, opposite-signed input cases are listed in Table 5-14.
Additionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS compar-
ison operation with result listed in Table 5-15.
5-622
Vol. 2C
VRANGEPS—Range Restriction Calculation for Packed Pairs of Float32 Values
INSTRUCTION SET REFERENCE, V
Operation
RangeSP(SRC1[31:0], SRC2[31:0], CmpOpCtl[1:0], SignSelCtl[1:0])
{
// Check if SNAN and report IE, see also Table 5-13
IF (SRC1=SNAN) THEN RETURN (QNAN(SRC1), set IE);
IF (SRC2=SNAN) THEN RETURN (QNAN(SRC2), set IE);
Src1.exp := SRC1[30:23];
Src1.fraction := SRC1[22:0];
IF ((Src1.exp = 0 ) and (Src1.fraction != 0 )) THEN// Src1 is a denormal number
IF DAZ THEN Src1.fraction := 0;
ELSE IF (SRC2 <> QNAN) Set DE; FI;
FI;
Src2.exp := SRC2[30:23];
Src2.fraction := SRC2[22:0];
IF ((Src2.exp = 0 ) and (Src2.fraction != 0 )) THEN// Src2 is a denormal number
IF DAZ THEN Src2.fraction := 0;
ELSE IF (SRC1 <> QNAN) Set DE; FI;
FI;
IF
(SRC2 = QNAN) THEN{TMP[31:0] := SRC1[31:0]}
ELSE IF(SRC1 = QNAN) THEN{TMP[31:0] := SRC2[31:0]}
ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[31:0] := from Table 5-14
ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-signed and CmpOpCtl[1:0] > 01) TMP[31:0] := from Table 5-15
ELSE
Case(CmpOpCtl[1:0])
00: TMP[31:0] := (SRC1[31:0] ≤ SRC2[31:0]) ? SRC1[31:0] : SRC2[31:0];
01: TMP[31:0] := (SRC1[31:0] ≤ SRC2[31:0]) ? SRC2[31:0] : SRC1[31:0];
10: TMP[31:0] := (ABS(SRC1[31:0]) ≤ ABS(SRC2[31:0])) ? SRC1[31:0] : SRC2[31:0];
11: TMP[31:0] := (ABS(SRC1[31:0]) ≤ ABS(SRC2[31:0])) ? SRC2[31:0] : SRC1[31:0];
ESAC;
FI;
Case(SignSelCtl[1:0])
00: dest := (SRC1[31] << 31) OR (TMP[30:0]);// Preserve Src1 sign bit
01: dest := TMP[31:0];// Preserve sign of compare result
10: dest := (0 << 31) OR (TMP[30:0]);// Zero out sign bit
11: dest := (1 << 31) OR (TMP[30:0]);// Set the sign bit
ESAC;
RETURN dest[31:0];
}
CmpOpCtl[1:0]= imm8[1:0];
SignSelCtl[1:0]=imm8[3:2];
VRANGEPS
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask* THEN
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN DEST[i+31:i] := RangeSP (SRC1[i+31:i], SRC2[31:0], CmpOpCtl[1:0], SignSelCtl[1:0]);
ELSE DEST[i+31:i] := RangeSP (SRC1[i+31:i], SRC2[i+31:i], CmpOpCtl[1:0], SignSelCtl[1:0]);
FI;
VRANGEPS—Range Restriction Calculation for Packed Pairs of Float32 Values
Vol. 2C
5-623
INSTRUCTION SET REFERENCE, V
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] = 0
FI;
FI;
ENDFOR;
DEST[MAXVL-1:VL] := 0
The following example describes a common usage of this instruction for checking that the input operand is bound-
ed between ±150.
VRANGEPS zmm_dst, zmm_src, zmm_150, 02h;
Where:
zmm_dst is the destination operand.
zmm_src is the input operand to compare against ±150.
zmm_150 is the reference operand, contains the value of 150.
IMM=02(imm8[1:0]=’10) selects the Min Absolute value operation with selection of src1.sign.
In case |zmm_src| < 150, then its value will be written into zmm_dst. Otherwise, the value stored in zmm_dst
will get the value of 150 (received on zmm_150).
However, the sign control (imm8[3:2]=’00) instructs to select the sign of SRC1 received from zmm_src. So, even
in the case of |zmm_src| ≥ 150, the selected sign of SRC1 is kept.
Thus, if zmm_src < -150, the result of VRANGEPS will be the minimal value of -150 while if zmm_src > +150,
the result of VRANGE will be the maximal value of +150.
Intel C/C++ Compiler Intrinsic Equivalent
VRANGEPS __m512 _mm512_range_ps ( __m512 a, __m512 b, int imm);
VRANGEPS __m512 _mm512_range_round_ps ( __m512 a, __m512 b, int imm, int sae);
VRANGEPS __m512 _mm512_mask_range_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int imm);
VRANGEPS __m512 _mm512_mask_range_round_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int imm, int sae);
VRANGEPS __m512 _mm512_maskz_range_ps ( __mmask16 k, __m512 a, __m512 b, int imm);
VRANGEPS __m512 _mm512_maskz_range_round_ps ( __mmask16 k, __m512 a, __m512 b, int imm, int sae);
VRANGEPS __m256 _mm256_range_ps ( __m256 a, __m256 b, int imm);
VRANGEPS __m256 _mm256_mask_range_ps (__m256 s, __mmask8 k, __m256 a, __m256 b, int imm);
VRANGEPS __m256 _mm256_maskz_range_ps ( __mmask8 k, __m256 a, __m256 b, int imm);
VRANGEPS __m128 _mm_range_ps ( __m128 a, __m128 b, int imm);
VRANGEPS __m128 _mm_mask_range_ps (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);
VRANGEPS __m128 _mm_maskz_range_ps ( __mmask8 k, __m128 a, __m128 b, int imm);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
See Table 2-46, “Type E2 Class Exception Conditions.”
5-624
Vol. 2C
VRANGEPS—Range Restriction Calculation for Packed Pairs of Float32 Values
INSTRUCTION SET REFERENCE, V
VRANGESD—Range Restriction Calculation From a Pair of Scalar Float64 Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.LLIG.66.0F3A.W1 51 /r
A
V/V
AVX512DQ
Calculate a RANGE operation output value from 2 double
VRANGESD xmm1 {k1}{z},
precision floating-point values in xmm2 and xmm3/m64,
xmm2, xmm3/m64{sae}, imm8
store the output to xmm1 under writemask. Imm8 specifies
the comparison and sign of the range operation.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
This instruction calculates a range operation output from two input double precision floating-point values in the low
qword element of the first source operand (the second operand) and second source operand (the third operand).
The range output is written to the low qword element of the destination operand (the first operand) under the
writemask k1.
Bits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a
two-bit control field within imm8[3:0]:
• Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min
absolute value of the input value pair. Each comparison of two input values produces an intermediate result
that combines with the sign selection control (imm8[3:2]) to determine the final range operation output.
• Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input
value, from the comparison result, set or clear.
The encodings of imm8[1:0] and imm8[3:2] are shown in Figure 5-27.
Bits 128:63 of the destination operand are copied from the respective element of the first source operand.
When one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details
with one of more input value is NAN is listed in Table 5-13. If the comparison raises an IE, the sign select control
(imm8[3:2]) has no effect to the range operation output; this is indicated also in Table 5-13.
When both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare
operation is slightly different from the conceptually similar floating-point MIN/MAX operation that are found in the
instructions VMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS
for magnitude-0, opposite-signed input cases are listed in Table 5-14.
Additionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS compar-
ison operation with result listed in Table 5-15.
VRANGESD—Range Restriction Calculation From a Pair of Scalar Float64 Values
Vol. 2C
5-625
INSTRUCTION SET REFERENCE, V
Operation
RangeDP(SRC1[63:0], SRC2[63:0], CmpOpCtl[1:0], SignSelCtl[1:0])
{
// Check if SNAN and report IE, see also Table 5-13
IF (SRC1 = SNAN) THEN RETURN (QNAN(SRC1), set IE);
IF (SRC2 = SNAN) THEN RETURN (QNAN(SRC2), set IE);
Src1.exp := SRC1[62:52];
Src1.fraction := SRC1[51:0];
IF ((Src1.exp = 0 ) and (Src1.fraction != 0)) THEN// Src1 is a denormal number
IF DAZ THEN Src1.fraction := 0;
ELSE IF (SRC2 <> QNAN) Set DE; FI;
FI;
Src2.exp := SRC2[62:52];
Src2.fraction := SRC2[51:0];
IF ((Src2.exp = 0) and (Src2.fraction !=0 )) THEN// Src2 is a denormal number
IF DAZ THEN Src2.fraction := 0;
ELSE IF (SRC1 <> QNAN) Set DE; FI;
FI;
IF
(SRC2 = QNAN) THEN{TMP[63:0] := SRC1[63:0]}
ELSE IF(SRC1 = QNAN) THEN{TMP[63:0] := SRC2[63:0]}
ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[63:0] := from Table 5-14
ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-signed and CmpOpCtl[1:0] > 01) TMP[63:0] := from Table 5-15
ELSE
Case(CmpOpCtl[1:0])
00: TMP[63:0] := (SRC1[63:0] ≤ SRC2[63:0]) ? SRC1[63:0] : SRC2[63:0];
01: TMP[63:0] := (SRC1[63:0] ≤ SRC2[63:0]) ? SRC2[63:0] : SRC1[63:0];
10: TMP[63:0] := (ABS(SRC1[63:0]) ≤ ABS(SRC2[63:0])) ? SRC1[63:0] : SRC2[63:0];
11: TMP[63:0] := (ABS(SRC1[63:0]) ≤ ABS(SRC2[63:0])) ? SRC2[63:0] : SRC1[63:0];
ESAC;
FI;
Case(SignSelCtl[1:0])
00: dest := (SRC1[63] << 63) OR (TMP[62:0]);// Preserve Src1 sign bit
01: dest := TMP[63:0];// Preserve sign of compare result
10: dest := (0 << 63) OR (TMP[62:0]);// Zero out sign bit
11: dest := (1 << 63) OR (TMP[62:0]);// Set the sign bit
ESAC;
RETURN dest[63:0];
}
CmpOpCtl[1:0]= imm8[1:0];
SignSelCtl[1:0]=imm8[3:2];
5-626
Vol. 2C
VRANGESD—Range Restriction Calculation From a Pair of Scalar Float64 Values