Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 102
INSTRUCTION SET REFERENCE, V
VPERMILPD—Permute In-Lane of Pairs of Double Precision Floating-Point Values
Opcode/
Op / En
64/32
CPUID
Description
Instruction
bit Mode
Feature
Support
Flag
VEX.128.66.0F38.W0 0D /r
A
V/V
AVX
Permute double precision floating-point values in
VPERMILPD xmm1, xmm2, xmm3/m128
xmm2 using controls from xmm3/m128 and store
result in xmm1.
VEX.256.66.0F38.W0 0D /r
A
V/V
AVX
Permute double precision floating-point values in
VPERMILPD ymm1, ymm2, ymm3/m256
ymm2 using controls from ymm3/m256 and store
result in ymm1.
EVEX.128.66.0F38.W1 0D /r
C
V/V
AVX512VL
Permute double precision floating-point values in
VPERMILPD xmm1 {k1}{z}, xmm2,
AVX512F
xmm2 using control from xmm3/m128/m64bcst
xmm3/m128/m64bcst
and store the result in xmm1 using writemask k1.
EVEX.256.66.0F38.W1 0D /r
C
V/V
AVX512VL
Permute double precision floating-point values in
VPERMILPD ymm1 {k1}{z}, ymm2,
AVX512F
ymm2 using control from ymm3/m256/m64bcst
ymm3/m256/m64bcst
and store the result in ymm1 using writemask k1.
EVEX.512.66.0F38.W1 0D /r
C
V/V
AVX512F
Permute double precision floating-point values in
VPERMILPD zmm1 {k1}{z}, zmm2,
zmm2 using control from zmm3/m512/m64bcst
zmm3/m512/m64bcst
and store the result in zmm1 using writemask k1.
VEX.128.66.0F3A.W0 05 /r ib
B
V/V
AVX
Permute double precision floating-point values in
VPERMILPD xmm1, xmm2/m128, imm8
xmm2/m128 using controls from imm8.
VEX.256.66.0F3A.W0 05 /r ib
B
V/V
AVX
Permute double precision floating-point values in
VPERMILPD ymm1, ymm2/m256, imm8
ymm2/m256 using controls from imm8.
EVEX.128.66.0F3A.W1 05 /r ib
D
V/V
AVX512VL
Permute double precision floating-point values in
VPERMILPD xmm1 {k1}{z},
AVX512F
xmm2/m128/m64bcst using controls from imm8
xmm2/m128/m64bcst, imm8
and store the result in xmm1 using writemask k1.
EVEX.256.66.0F3A.W1 05 /r ib
D
V/V
AVX512VL
Permute double precision floating-point values in
VPERMILPD ymm1 {k1}{z},
AVX512F
ymm2/m256/m64bcst using controls from imm8
ymm2/m256/m64bcst, imm8
and store the result in ymm1 using writemask k1.
EVEX.512.66.0F3A.W1 05 /r ib
D
V/V
AVX512F
Permute double precision floating-point values in
VPERMILPD zmm1 {k1}{z},
zmm2/m512/m64bcst using controls from imm8
zmm2/m512/m64bcst, imm8
and store the result in zmm1 using writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
B
N/A
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
C
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
D
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
VPERMILPD—Permute In-Lane of Pairs of Double Precision Floating-Point Values
Vol. 2C
5-477
INSTRUCTION SET REFERENCE, V
Description
(variable control version)
Permute pairs of double precision floating-point values in the first source operand (second operand), each using a
1-bit control field residing in the corresponding quadword element of the second source operand (third operand).
Permuted results are stored in the destination operand (first operand).
The control bits are located at bit 0 of each quadword element (see Figure 5-24). Each control determines which of
the source element in an input pair is selected for the destination element. Each pair of source elements must lie in
the same 128-bit region as the destination.
EVEX version: The second source operand (third operand) is a ZMM/YMM/XMM register, a 512/256/128-bit
memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. Permuted results are
written to the destination under the writemask.
SRC1
X3
X2
X1
X0
DEST
X2..X3
X2..X3
X0..X1
X0..X1
Figure 5-23. VPERMILPD Operation
VEX.256 encoded version: Bits (MAXVL-1:256) of the corresponding ZMM register are zeroed.
Bit
255
194 193
127
66
65
63
2
1
ignored
sel
ignored
sel
ignored
sel
Control Field 4
Control Field 2
Control Field1
Figure 5-24. VPERMILPD Shuffle Control
Immediate control version: Permute pairs of double precision floating-point values in the first source operand
(second operand), each pair using a 1-bit control field in the imm8 byte. Each element in the destination operand
(first operand) use a separate control bit of the imm8 byte.
VEX version: The source operand is a YMM/XMM register or a 256/128-bit memory location and the destination
operand is a YMM/XMM register. Imm8 byte provides the lower 4/2 bit as permute control fields.
EVEX version: The source operand (second operand) is a ZMM/YMM/XMM register, a 512/256/128-bit memory
location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. Permuted results are written to
the destination under the writemask. Imm8 byte provides the lower 8/4/2 bit as permute control fields.
Note: For the imm8 versions, VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will
#UD.
5-478
Vol. 2C
VPERMILPD—Permute In-Lane of Pairs of Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V
Operation
VPERMILPD (EVEX immediate versions)
(KL, VL) = (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN TMP_SRC1[i+63:i] := SRC1[63:0];
ELSE TMP_SRC1[i+63:i] := SRC1[i+63:i];
FI;
ENDFOR;
IF (imm8[0] = 0) THEN TMP_DEST[63:0] := SRC1[63:0]; FI;
IF (imm8[0] = 1) THEN TMP_DEST[63:0] := TMP_SRC1[127:64]; FI;
IF (imm8[1] = 0) THEN TMP_DEST[127:64] := TMP_SRC1[63:0]; FI;
IF (imm8[1] = 1) THEN TMP_DEST[127:64] := TMP_SRC1[127:64]; FI;
IF VL >= 256
IF (imm8[2] = 0) THEN TMP_DEST[191:128] := TMP_SRC1[191:128]; FI;
IF (imm8[2] = 1) THEN TMP_DEST[191:128] := TMP_SRC1[255:192]; FI;
IF (imm8[3] = 0) THEN TMP_DEST[255:192] := TMP_SRC1[191:128]; FI;
IF (imm8[3] = 1) THEN TMP_DEST[255:192] := TMP_SRC1[255:192]; FI;
FI;
IF VL >= 512
IF (imm8[4] = 0) THEN TMP_DEST[319:256] := TMP_SRC1[319:256]; FI;
IF (imm8[4] = 1) THEN TMP_DEST[319:256] := TMP_SRC1[383:320]; FI;
IF (imm8[5] = 0) THEN TMP_DEST[383:320] := TMP_SRC1[319:256]; FI;
IF (imm8[5] = 1) THEN TMP_DEST[383:320] := TMP_SRC1[383:320]; FI;
IF (imm8[6] = 0) THEN TMP_DEST[447:384] := TMP_SRC1[447:384]; FI;
IF (imm8[6] = 1) THEN TMP_DEST[447:384] := TMP_SRC1[511:448]; FI;
IF (imm8[7] = 0) THEN TMP_DEST[511:448] := TMP_SRC1[447:384]; FI;
IF (imm8[7] = 1) THEN TMP_DEST[511:448] := TMP_SRC1[511:448]; FI;
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPERMILPD (256-bit immediate version)
IF (imm8[0] = 0) THEN DEST[63:0] := SRC1[63:0]
IF (imm8[0] = 1) THEN DEST[63:0] := SRC1[127:64]
IF (imm8[1] = 0) THEN DEST[127:64] := SRC1[63:0]
IF (imm8[1] = 1) THEN DEST[127:64] := SRC1[127:64]
IF (imm8[2] = 0) THEN DEST[191:128] := SRC1[191:128]
IF (imm8[2] = 1) THEN DEST[191:128] := SRC1[255:192]
IF (imm8[3] = 0) THEN DEST[255:192] := SRC1[191:128]
IF (imm8[3] = 1) THEN DEST[255:192] := SRC1[255:192]
DEST[MAXVL-1:256] := 0
VPERMILPD—Permute In-Lane of Pairs of Double Precision Floating-Point Values
Vol. 2C
5-479
INSTRUCTION SET REFERENCE, V
VPERMILPD (128-bit immediate version)
IF (imm8[0] = 0) THEN DEST[63:0] := SRC1[63:0]
IF (imm8[0] = 1) THEN DEST[63:0] := SRC1[127:64]
IF (imm8[1] = 0) THEN DEST[127:64] := SRC1[63:0]
IF (imm8[1] = 1) THEN DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0
VPERMILPD (EVEX variable versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+63:i] := SRC2[63:0];
ELSE TMP_SRC2[i+63:i] := SRC2[i+63:i];
FI;
ENDFOR;
IF (TMP_SRC2[1] = 0) THEN TMP_DEST[63:0] := SRC1[63:0]; FI;
IF (TMP_SRC2[1] = 1) THEN TMP_DEST[63:0] := SRC1[127:64]; FI;
IF (TMP_SRC2[65] = 0) THEN TMP_DEST[127:64] := SRC1[63:0]; FI;
IF (TMP_SRC2[65] = 1) THEN TMP_DEST[127:64] := SRC1[127:64]; FI;
IF VL >= 256
IF (TMP_SRC2[129] = 0) THEN TMP_DEST[191:128] := SRC1[191:128]; FI;
IF (TMP_SRC2[129] = 1) THEN TMP_DEST[191:128] := SRC1[255:192]; FI;
IF (TMP_SRC2[193] = 0) THEN TMP_DEST[255:192] := SRC1[191:128]; FI;
IF (TMP_SRC2[193] = 1) THEN TMP_DEST[255:192] := SRC1[255:192]; FI;
FI;
IF VL >= 512
IF (TMP_SRC2[257] = 0) THEN TMP_DEST[319:256] := SRC1[319:256]; FI;
IF (TMP_SRC2[257] = 1) THEN TMP_DEST[319:256] := SRC1[383:320]; FI;
IF (TMP_SRC2[321] = 0) THEN TMP_DEST[383:320] := SRC1[319:256]; FI;
IF (TMP_SRC2[321] = 1) THEN TMP_DEST[383:320] := SRC1[383:320]; FI;
IF (TMP_SRC2[385] = 0) THEN TMP_DEST[447:384] := SRC1[447:384]; FI;
IF (TMP_SRC2[385] = 1) THEN TMP_DEST[447:384] := SRC1[511:448]; FI;
IF (TMP_SRC2[449] = 0) THEN TMP_DEST[511:448] := SRC1[447:384]; FI;
IF (TMP_SRC2[449] = 1) THEN TMP_DEST[511:448] := SRC1[511:448]; FI;
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
5-480
Vol. 2C
VPERMILPD—Permute In-Lane of Pairs of Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V
VPERMILPD (256-bit variable version)
IF (SRC2[1] = 0) THEN DEST[63:0] := SRC1[63:0]
IF (SRC2[1] = 1) THEN DEST[63:0] := SRC1[127:64]
IF (SRC2[65] = 0) THEN DEST[127:64] := SRC1[63:0]
IF (SRC2[65] = 1) THEN DEST[127:64] := SRC1[127:64]
IF (SRC2[129] = 0) THEN DEST[191:128] := SRC1[191:128]
IF (SRC2[129] = 1) THEN DEST[191:128] := SRC1[255:192]
IF (SRC2[193] = 0) THEN DEST[255:192] := SRC1[191:128]
IF (SRC2[193] = 1) THEN DEST[255:192] := SRC1[255:192]
DEST[MAXVL-1:256] := 0
VPERMILPD (128-bit variable version)
IF (SRC2[1] = 0) THEN DEST[63:0] := SRC1[63:0]
IF (SRC2[1] = 1) THEN DEST[63:0] := SRC1[127:64]
IF (SRC2[65] = 0) THEN DEST[127:64] := SRC1[63:0]
IF (SRC2[65] = 1) THEN DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPERMILPD __m512d _mm512_permute_pd( __m512d a, int imm);
VPERMILPD __m512d _mm512_mask_permute_pd(__m512d s, __mmask8 k, __m512d a, int imm);
VPERMILPD __m512d _mm512_maskz_permute_pd( __mmask8 k, __m512d a, int imm);
VPERMILPD __m256d _mm256_mask_permute_pd(__m256d s, __mmask8 k, __m256d a, int imm);
VPERMILPD __m256d _mm256_maskz_permute_pd( __mmask8 k, __m256d a, int imm);
VPERMILPD __m128d _mm_mask_permute_pd(__m128d s, __mmask8 k, __m128d a, int imm);
VPERMILPD __m128d _mm_maskz_permute_pd( __mmask8 k, __m128d a, int imm);
VPERMILPD __m512d _mm512_permutevar_pd( __m512i i, __m512d a);
VPERMILPD __m512d _mm512_mask_permutevar_pd(__m512d s, __mmask8 k, __m512i i, __m512d a);
VPERMILPD __m512d _mm512_maskz_permutevar_pd( __mmask8 k, __m512i i, __m512d a);
VPERMILPD __m256d _mm256_mask_permutevar_pd(__m256d s, __mmask8 k, __m256d i, __m256d a);
VPERMILPD __m256d _mm256_maskz_permutevar_pd( __mmask8 k, __m256d i, __m256d a);
VPERMILPD __m128d _mm_mask_permutevar_pd(__m128d s, __mmask8 k, __m128d i, __m128d a);
VPERMILPD __m128d _mm_maskz_permutevar_pd( __mmask8 k, __m128d i, __m128d a);
VPERMILPD __m128d _mm_permute_pd (__m128d a, int control)
VPERMILPD __m256d _mm256_permute_pd (__m256d a, int control)
VPERMILPD __m128d _mm_permutevar_pd (__m128d a, __m128i control);
VPERMILPD __m256d _mm256_permutevar_pd (__m256d a, __m256i control);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
Additionally:
#UD
If VEX.W = 1.
EVEX-encoded instruction, see Table 2-50, “Type E4NF Class Exception Conditions.”
Additionally:
#UD
If either (E)VEX.vvvv != 1111B and with imm8.
VPERMILPD—Permute In-Lane of Pairs of Double Precision Floating-Point Values
Vol. 2C
5-481
INSTRUCTION SET REFERENCE, V
VPERMILPS—Permute In-Lane of Quadruples of Single Precision Floating-Point Values
Opcode/
Op / En
64/32
CPUID
Description
Instruction
bit Mode
Feature
Support
Flag
VEX.128.66.0F38.W0 0C /r
A
V/V
AVX
Permute single-precision floating-point values in
VPERMILPS xmm1, xmm2, xmm3/m128
xmm2 using controls from xmm3/m128 and
store result in xmm1.
VEX.128.66.0F3A.W0 04 /r ib
B
V/V
AVX
Permute single-precision floating-point values in
VPERMILPS xmm1, xmm2/m128, imm8
xmm2/m128 using controls from imm8 and store
result in xmm1.
VEX.256.66.0F38.W0 0C /r
A
V/V
AVX
Permute single-precision floating-point values in
VPERMILPS ymm1, ymm2, ymm3/m256
ymm2 using controls from ymm3/m256 and
store result in ymm1.
VEX.256.66.0F3A.W0 04 /r ib
B
V/V
AVX
Permute single-precision floating-point values in
VPERMILPS ymm1, ymm2/m256, imm8
ymm2/m256 using controls from imm8 and store
result in ymm1.
EVEX.128.66.0F38.W0 0C /r
C
V/V
AVX512VL
Permute single-precision floating-point values
VPERMILPS xmm1 {k1}{z}, xmm2,
AVX512F
xmm2 using control from xmm3/m128/m32bcst
xmm3/m128/m32bcst
and store the result in xmm1 using writemask k1.
EVEX.256.66.0F38.W0 0C /r
C
V/V
AVX512VL
Permute single-precision floating-point values
VPERMILPS ymm1 {k1}{z}, ymm2,
AVX512F
ymm2 using control from ymm3/m256/m32bcst
ymm3/m256/m32bcst
and store the result in ymm1 using writemask k1.
EVEX.512.66.0F38.W0 0C /r
C
V/V
AVX512F
Permute single-precision floating-point values
VPERMILPS zmm1 {k1}{z}, zmm2,
zmm2 using control from zmm3/m512/m32bcst
zmm3/m512/m32bcst
and store the result in zmm1 using writemask k1.
EVEX.128.66.0F3A.W0 04 /r ib
D
V/V
AVX512VL
Permute single-precision floating-point values
VPERMILPS xmm1 {k1}{z},
AVX512F
xmm2/m128/m32bcst using controls from imm8
xmm2/m128/m32bcst, imm8
and store the result in xmm1 using writemask k1.
EVEX.256.66.0F3A.W0 04 /r ib
D
V/V
AVX512VL
Permute single-precision floating-point values
VPERMILPS ymm1 {k1}{z},
AVX512F
ymm2/m256/m32bcst using controls from imm8
ymm2/m256/m32bcst, imm8
and store the result in ymm1 using writemask k1.
EVEX.512.66.0F3A.W0 04 /r
D
V/V
AVX512F
Permute single-precision floating-point values
ibVPERMILPS zmm1 {k1}{z},
zmm2/m512/m32bcst using controls from imm8
zmm2/m512/m32bcst, imm8
and store the result in zmm1 using writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
B
N/A
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
C
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
D
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
5-482
Vol. 2C
VPERMILPS—Permute In-Lane of Quadruples of Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V
Description
Variable control version:
Permute quadruples of single-precision floating-point values in the first source operand (second operand), each
quadruplet using a 2-bit control field in the corresponding dword element of the second source operand. Permuted
results are stored in the destination operand (first operand).
The 2-bit control fields are located at the low two bits of each dword element (see Figure 5-26). Each control deter-
mines which of the source element in an input quadruple is selected for the destination element. Each quadruple of
source elements must lie in the same 128-bit region as the destination.
EVEX version: The second source operand (third operand) is a ZMM/YMM/XMM register, a 512/256/128-bit
memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. Permuted results are
written to the destination under the writemask.
SRC1
X7
X6
X5
X4
X3
X2
X1
X0
DEST
X7 .. X4
X7 .. X4
X7 .. X4
X7 .. X4
X3 ..X0
X3 ..X0
X3 .. X0
X3 .. X0
Figure 5-25. VPERMILPS Operation
Bit
255
226
225 224
63
34
33 32
31
1
0
ignored
sel
ignored
sel
ignored
sel
Control Field 7
Control Field 2
Control Field 1
Figure 5-26. VPERMILPS Shuffle Control
(immediate control version)
Permute quadruples of single-precision floating-point values in the first source operand (second operand), each
quadruplet using a 2-bit control field in the imm8 byte. Each 128-bit lane in the destination operand (first operand)
use the four control fields of the same imm8 byte.
VEX version: The source operand is a YMM/XMM register or a 256/128-bit memory location and the destination
operand is a YMM/XMM register.
EVEX version: The source operand (second operand) is a ZMM/YMM/XMM register, a 512/256/128-bit memory
location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. Permuted results are written to
the destination under the writemask.
Note: For the imm8 version, VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will
#UD.
VPERMILPS—Permute In-Lane of Quadruples of Single Precision Floating-Point Values
Vol. 2C
5-483
INSTRUCTION SET REFERENCE, V
Operation
Select4(SRC, control) {
CASE (control[1:0]) OF
0: TMP := SRC[31:0];
1: TMP := SRC[63:32];
2: TMP := SRC[95:64];
3: TMP := SRC[127:96];
ESAC;
RETURN TMP
}
VPERMILPS (EVEX immediate versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF (EVEX.b = 1) AND (SRC1 *is memory*)
THEN TMP_SRC1[i+31:i] := SRC1[31:0];
ELSE TMP_SRC1[i+31:i] := SRC1[i+31:i];
FI;
ENDFOR;
TMP_DEST[31:0] := Select4(TMP_SRC1[127:0], imm8[1:0]);
TMP_DEST[63:32] := Select4(TMP_SRC1[127:0], imm8[3:2]);
TMP_DEST[95:64] := Select4(TMP_SRC1[127:0], imm8[5:4]);
TMP_DEST[127:96] := Select4(TMP_SRC1[127:0], imm8[7:6]); FI;
IF VL >= 256
TMP_DEST[159:128] := Select4(TMP_SRC1[255:128], imm8[1:0]); FI;
TMP_DEST[191:160] := Select4(TMP_SRC1[255:128], imm8[3:2]); FI;
TMP_DEST[223:192] := Select4(TMP_SRC1[255:128], imm8[5:4]); FI;
TMP_DEST[255:224] := Select4(TMP_SRC1[255:128], imm8[7:6]); FI;
FI;
IF VL >= 512
TMP_DEST[287:256] := Select4(TMP_SRC1[383:256], imm8[1:0]); FI;
TMP_DEST[319:288] := Select4(TMP_SRC1[383:256], imm8[3:2]); FI;
TMP_DEST[351:320] := Select4(TMP_SRC1[383:256], imm8[5:4]); FI;
TMP_DEST[383:352] := Select4(TMP_SRC1[383:256], imm8[7:6]); FI;
TMP_DEST[415:384] := Select4(TMP_SRC1[511:384], imm8[1:0]); FI;
TMP_DEST[447:416] := Select4(TMP_SRC1[511:384], imm8[3:2]); FI;
TMP_DEST[479:448] := Select4(TMP_SRC1[511:384], imm8[5:4]); FI;
TMP_DEST[511:480] := Select4(TMP_SRC1[511:384], imm8[7:6]); FI;
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] := 0
;zeroing-masking
FI;
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
5-484
Vol. 2C
VPERMILPS—Permute In-Lane of Quadruples of Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V
VPERMILPS (256-bit immediate version)
DEST[31:0] := Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] := Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] := Select4(SRC1[127:0], imm8[5:4]);
DEST[127:96] := Select4(SRC1[127:0], imm8[7:6]);
DEST[159:128] := Select4(SRC1[255:128], imm8[1:0]);
DEST[191:160] := Select4(SRC1[255:128], imm8[3:2]);
DEST[223:192] := Select4(SRC1[255:128], imm8[5:4]);
DEST[255:224] := Select4(SRC1[255:128], imm8[7:6]);
VPERMILPS (128-bit immediate version)
DEST[31:0] := Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] := Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] := Select4(SRC1[127:0], imm8[5:4]);
DEST[127:96] := Select4(SRC1[127:0], imm8[7:6]);
DEST[MAXVL-1:128] := 0
VPERMILPS (EVEX variable versions)
(KL, VL) = (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+31:i] := SRC2[31:0];
ELSE TMP_SRC2[i+31:i] := SRC2[i+31:i];
FI;
ENDFOR;
TMP_DEST[31:0] := Select4(SRC1[127:0], TMP_SRC2[1:0]);
TMP_DEST[63:32] := Select4(SRC1[127:0], TMP_SRC2[33:32]);
TMP_DEST[95:64] := Select4(SRC1[127:0], TMP_SRC2[65:64]);
TMP_DEST[127:96] := Select4(SRC1[127:0], TMP_SRC2[97:96]);
IF VL >= 256
TMP_DEST[159:128] := Select4(SRC1[255:128], TMP_SRC2[129:128]);
TMP_DEST[191:160] := Select4(SRC1[255:128], TMP_SRC2[161:160]);
TMP_DEST[223:192] := Select4(SRC1[255:128], TMP_SRC2[193:192]);
TMP_DEST[255:224] := Select4(SRC1[255:128], TMP_SRC2[225:224]);
FI;
IF VL >= 512
TMP_DEST[287:256] := Select4(SRC1[383:256], TMP_SRC2[257:256]);
TMP_DEST[319:288] := Select4(SRC1[383:256], TMP_SRC2[289:288]);
TMP_DEST[351:320] := Select4(SRC1[383:256], TMP_SRC2[321:320]);
TMP_DEST[383:352] := Select4(SRC1[383:256], TMP_SRC2[353:352]);
TMP_DEST[415:384] := Select4(SRC1[511:384], TMP_SRC2[385:384]);
TMP_DEST[447:416] := Select4(SRC1[511:384], TMP_SRC2[417:416]);
TMP_DEST[479:448] := Select4(SRC1[511:384], TMP_SRC2[449:448]);
TMP_DEST[511:480] := Select4(SRC1[511:384], TMP_SRC2[481:480]);
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] := 0
;zeroing-masking
VPERMILPS—Permute In-Lane of Quadruples of Single Precision Floating-Point Values
Vol. 2C
5-485
INSTRUCTION SET REFERENCE, V
FI;
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPERMILPS (256-bit variable version)
DEST[31:0] := Select4(SRC1[127:0], SRC2[1:0]);
DEST[63:32] := Select4(SRC1[127:0], SRC2[33:32]);
DEST[95:64] := Select4(SRC1[127:0], SRC2[65:64]);
DEST[127:96] := Select4(SRC1[127:0], SRC2[97:96]);
DEST[159:128] := Select4(SRC1[255:128], SRC2[129:128]);
DEST[191:160] := Select4(SRC1[255:128], SRC2[161:160]);
DEST[223:192] := Select4(SRC1[255:128], SRC2[193:192]);
DEST[255:224] := Select4(SRC1[255:128], SRC2[225:224]);
DEST[MAXVL-1:256] := 0
VPERMILPS (128-bit variable version)
DEST[31:0] := Select4(SRC1[127:0], SRC2[1:0]);
DEST[63:32] := Select4(SRC1[127:0], SRC2[33:32]);
DEST[95:64] :=Select4(SRC1[127:0], SRC2[65:64]);
DEST[127:96] := Select4(SRC1[127:0], SRC2[97:96]);
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPERMILPS __m512 _mm512_permute_ps( __m512 a, int imm);
VPERMILPS __m512 _mm512_mask_permute_ps(__m512 s, __mmask16 k, __m512 a, int imm);
VPERMILPS __m512 _mm512_maskz_permute_ps( __mmask16 k, __m512 a, int imm);
VPERMILPS __m256 _mm256_mask_permute_ps(__m256 s, __mmask8 k, __m256 a, int imm);
VPERMILPS __m256 _mm256_maskz_permute_ps( __mmask8 k, __m256 a, int imm);
VPERMILPS __m128 _mm_mask_permute_ps(__m128 s, __mmask8 k, __m128 a, int imm);
VPERMILPS __m128 _mm_maskz_permute_ps( __mmask8 k, __m128 a, int imm);
VPERMILPS __m512 _mm512_permutevar_ps( __m512i i, __m512 a);
VPERMILPS __m512 _mm512_mask_permutevar_ps(__m512 s, __mmask16 k, __m512i i, __m512 a);
VPERMILPS __m512 _mm512_maskz_permutevar_ps( __mmask16 k, __m512i i, __m512 a);
VPERMILPS __m256 _mm256_mask_permutevar_ps(__m256 s, __mmask8 k, __m256 i, __m256 a);
VPERMILPS __m256 _mm256_maskz_permutevar_ps( __mmask8 k, __m256 i, __m256 a);
VPERMILPS __m128 _mm_mask_permutevar_ps(__m128 s, __mmask8 k, __m128 i, __m128 a);
VPERMILPS __m128 _mm_maskz_permutevar_ps( __mmask8 k, __m128 i, __m128 a);
VPERMILPS __m128 _mm_permute_ps (__m128 a, int control);
VPERMILPS __m256 _mm256_permute_ps (__m256 a, int control);
VPERMILPS __m128 _mm_permutevar_ps (__m128 a, __m128i control);
VPERMILPS __m256 _mm256_permutevar_ps (__m256 a, __m256i control);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
Additionally:
#UD
If VEX.W = 1.
EVEX-encoded instruction, see Table 2-50, “Type E4NF Class Exception Conditions.”
Additionally:
#UD
If either (E)VEX.vvvv != 1111B and with imm8.
5-486
Vol. 2C
VPERMILPS—Permute In-Lane of Quadruples of Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V
VPERMPD—Permute Double Precision Floating-Point Elements
Opcode/
Op / En
64/32
CPUID
Description
Instruction
bit Mode
Feature
Support
Flag
VEX.256.66.0F3A.W1 01 /r ib
A
V/V
AVX2
Permute double precision floating-point elements in
VPERMPD ymm1, ymm2/m256, imm8
ymm2/m256 using indices in imm8 and store the
result in ymm1.
EVEX.256.66.0F3A.W1 01 /r ib
B
V/V
AVX512VL
Permute double precision floating-point elements in
VPERMPD ymm1 {k1}{z},
AVX512F
ymm2/m256/m64bcst using indexes in imm8 and
ymm2/m256/m64bcst, imm8
store the result in ymm1 subject to writemask k1.
EVEX.512.66.0F3A.W1 01 /r ib
B
V/V
AVX512F
Permute double precision floating-point elements in
VPERMPD zmm1 {k1}{z},
zmm2/m512/m64bcst using indices in imm8 and
zmm2/m512/m64bcst, imm8
store the result in zmm1 subject to writemask k1.
EVEX.256.66.0F38.W1 16 /r
C
V/V
AVX512VL
Permute double precision floating-point elements in
VPERMPD ymm1 {k1}{z}, ymm2,
AVX512F
ymm3/m256/m64bcst using indexes in ymm2 and
ymm3/m256/m64bcst
store the result in ymm1 subject to writemask k1.
EVEX.512.66.0F38.W1 16 /r
C
V/V
AVX512F
Permute double precision floating-point elements in
VPERMPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst using indices in zmm2 and
zmm3/m512/m64bcst
store the result in zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
ModRM:r/m (r)
imm8
N/A
B
Full
ModRM:reg (w)
ModRM:r/m (r)
imm8
N/A
C
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
The imm8 version: Copies quadword elements of double precision floating-point values from the source operand
(the second operand) to the destination operand (the first operand) according to the indices specified by the imme-
diate operand (the third operand). Each two-bit value in the immediate byte selects a qword element in the source
operand.
VEX version: The source operand can be a YMM register or a memory location. Bits (MAXVL-1:256) of the corre-
sponding destination register are zeroed.
In EVEX.512 encoded version, The elements in the destination are updated using the writemask k1 and the imm8
bits are reused as control bits for the upper 256-bit half when the control bits are coming from immediate. The
source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit
memory location.
The imm8 versions: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
The vector control version: Copies quadword elements of double precision floating-point values from the second
source operand (the third operand) to the destination operand (the first operand) according to the indices in the
first source operand (the second operand). The first 3 bits of each 64 bit element in the index operand selects which
quadword in the second source operand to copy. The first and second operands are ZMM registers, the third
operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit memory
location. The elements in the destination are updated using the writemask k1.
Note that this instruction permits a qword in the source operand to be copied to multiple locations in the destination
operand.
If VPERMPD is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will cause an
#UD exception.
VPERMPD—Permute Double Precision Floating-Point Elements
Vol. 2C
5-487
INSTRUCTION SET REFERENCE, V
Operation
VPERMPD (EVEX - imm8 control forms)
(KL, VL) = (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN TMP_SRC[i+63:i] := SRC[63:0];
ELSE TMP_SRC[i+63:i] := SRC[i+63:i];
FI;
ENDFOR;
TMP_DEST[63:0] := (TMP_SRC[256:0] >> (IMM8[1:0] * 64))[63:0];
TMP_DEST[127:64] := (TMP_SRC[256:0] >> (IMM8[3:2] * 64))[63:0];
TMP_DEST[191:128] := (TMP_SRC[256:0] >> (IMM8[5:4] * 64))[63:0];
TMP_DEST[255:192] := (TMP_SRC[256:0] >> (IMM8[7:6] * 64))[63:0];
IF VL >= 512
TMP_DEST[319:256] := (TMP_SRC[511:256] >> (IMM8[1:0] * 64))[63:0];
TMP_DEST[383:320] := (TMP_SRC[511:256] >> (IMM8[3:2] * 64))[63:0];
TMP_DEST[447:384] := (TMP_SRC[511:256] >> (IMM8[5:4] * 64))[63:0];
TMP_DEST[511:448] := (TMP_SRC[511:256] >> (IMM8[7:6] * 64))[63:0];
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
;zeroing-masking
FI;
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPERMPD (EVEX - vector control forms)
(KL, VL) = (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+63:i] := SRC2[63:0];
ELSE TMP_SRC2[i+63:i] := SRC2[i+63:i];
FI;
ENDFOR;
IF VL = 256
TMP_DEST[63:0] := (TMP_SRC2[255:0] >> (SRC1[1:0] * 64))[63:0];
TMP_DEST[127:64] := (TMP_SRC2[255:0] >> (SRC1[65:64] * 64))[63:0];
TMP_DEST[191:128] := (TMP_SRC2[255:0] >> (SRC1[129:128] * 64))[63:0];
TMP_DEST[255:192] := (TMP_SRC2[255:0] >> (SRC1[193:192] * 64))[63:0];
FI;
IF VL = 512
TMP_DEST[63:0] := (TMP_SRC2[511:0] >> (SRC1[2:0] * 64))[63:0];
5-488
Vol. 2C
VPERMPD—Permute Double Precision Floating-Point Elements
INSTRUCTION SET REFERENCE, V
TMP_DEST[127:64] := (TMP_SRC2[511:0] >> (SRC1[66:64] * 64))[63:0];
TMP_DEST[191:128] := (TMP_SRC2[511:0] >> (SRC1[130:128] * 64))[63:0];
TMP_DEST[255:192] := (TMP_SRC2[511:0] >> (SRC1[194:192] * 64))[63:0];
TMP_DEST[319:256] := (TMP_SRC2[511:0] >> (SRC1[258:256] * 64))[63:0];
TMP_DEST[383:320] := (TMP_SRC2[511:0] >> (SRC1[322:320] * 64))[63:0];
TMP_DEST[447:384] := (TMP_SRC2[511:0] >> (SRC1[386:384] * 64))[63:0];
TMP_DEST[511:448] := (TMP_SRC2[511:0] >> (SRC1[450:448] * 64))[63:0];
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
;zeroing-masking
FI;
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPERMPD (VEX.256 encoded version)
DEST[63:0] := (SRC[255:0] >> (IMM8[1:0] * 64))[63:0];
DEST[127:64] := (SRC[255:0] >> (IMM8[3:2] * 64))[63:0];
DEST[191:128] := (SRC[255:0] >> (IMM8[5:4] * 64))[63:0];
DEST[255:192] := (SRC[255:0] >> (IMM8[7:6] * 64))[63:0];
DEST[MAXVL-1:256] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPERMPD __m512d _mm512_permutex_pd( __m512d a, int imm);
VPERMPD __m512d _mm512_mask_permutex_pd(__m512d s, __mmask16 k, __m512d a, int imm);
VPERMPD __m512d _mm512_maskz_permutex_pd( __mmask16 k, __m512d a, int imm);
VPERMPD __m512d _mm512_permutexvar_pd( __m512i i, __m512d a);
VPERMPD __m512d _mm512_mask_permutexvar_pd(__m512d s, __mmask16 k, __m512i i, __m512d a);
VPERMPD __m512d _mm512_maskz_permutexvar_pd( __mmask16 k, __m512i i, __m512d a);
VPERMPD __m256d _mm256_permutex_epi64( __m256d a, int imm);
VPERMPD __m256d _mm256_mask_permutex_epi64(__m256i s, __mmask8 k, __m256d a, int imm);
VPERMPD __m256d _mm256_maskz_permutex_epi64( __mmask8 k, __m256d a, int imm);
VPERMPD __m256d _mm256_permutexvar_epi64( __m256i i, __m256d a);
VPERMPD __m256d _mm256_mask_permutexvar_epi64(__m256i s, __mmask8 k, __m256i i, __m256d a);
VPERMPD __m256d _mm256_maskz_permutexvar_epi64( __mmask8 k, __m256i i, __m256d a);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”; additionally:
#UD
If VEX.L = 0.
If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Table 2-50, “Type E4NF Class Exception Conditions”; additionally:
#UD
If encoded with EVEX.128.
If EVEX.vvvv != 1111B and with imm8.
VPERMPD—Permute Double Precision Floating-Point Elements
Vol. 2C
5-489
INSTRUCTION SET REFERENCE, V
VPERMPS—Permute Single Precision Floating-Point Elements
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
VEX.256.66.0F38.W0 16 /r
A
V/V
AVX2
Permute single-precision floating-point elements in
VPERMPS ymm1, ymm2,
ymm3/m256 using indices in ymm2 and store the result in
ymm3/m256
ymm1.
EVEX.256.66.0F38.W0 16 /r
B
V/V
AVX512VL
Permute single-precision floating-point elements in
VPERMPS ymm1 {k1}{z}, ymm2,
AVX512F
ymm3/m256/m32bcst using indexes in ymm2 and store
ymm3/m256/m32bcst
the result in ymm1 subject to write mask k1.
EVEX.512.66.0F38.W0 16 /r
B
V/V
AVX512F
Permute single-precision floating-point values in
VPERMPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst using indices in zmm2 and store the
zmm3/m512/m32bcst
result in zmm1 subject to write mask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Copies doubleword elements of single-precision floating-point values from the second source operand (the third
operand) to the destination operand (the first operand) according to the indices in the first source operand (the
second operand). Note that this instruction permits a doubleword in the source operand to be copied to more than
one location in the destination operand.
VEX.256 versions: The first and second operands are YMM registers, the third operand can be a YMM register or
memory location. Bits (MAXVL-1:256) of the corresponding destination register are zeroed.
EVEX encoded version: The first and second operands are ZMM registers, the third operand can be a ZMM register,
a 512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location. The elements in the
destination are updated using the writemask k1.
If VPERMPS is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will cause an
#UD exception.
Operation
VPERMPS (EVEX forms)
(KL, VL) (8, 256),= (16, 512)
FOR j := 0 TO KL-1
i := j * 64
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+31:i] := SRC2[31:0];
ELSE TMP_SRC2[i+31:i] := SRC2[i+31:i];
FI;
ENDFOR;
IF VL = 256
TMP_DEST[31:0] := (TMP_SRC2[255:0] >> (SRC1[2:0] * 32))[31:0];
TMP_DEST[63:32] := (TMP_SRC2[255:0] >> (SRC1[34:32] * 32))[31:0];
TMP_DEST[95:64] := (TMP_SRC2[255:0] >> (SRC1[66:64] * 32))[31:0];
TMP_DEST[127:96] := (TMP_SRC2[255:0] >> (SRC1[98:96] * 32))[31:0];
TMP_DEST[159:128] := (TMP_SRC2[255:0] >> (SRC1[130:128] * 32))[31:0];
TMP_DEST[191:160] := (TMP_SRC2[255:0] >> (SRC1[162:160] * 32))[31:0];
TMP_DEST[223:192] := (TMP_SRC2[255:0] >> (SRC1[193:192] * 32))[31:0];
TMP_DEST[255:224] := (TMP_SRC2[255:0] >> (SRC1[226:224] * 32))[31:0];
5-490
Vol. 2C
VPERMPS—Permute Single Precision Floating-Point Elements
INSTRUCTION SET REFERENCE, V
FI;
IF VL = 512
TMP_DEST[31:0] := (TMP_SRC2[511:0] >> (SRC1[3:0] * 32))[31:0];
TMP_DEST[63:32] := (TMP_SRC2[511:0] >> (SRC1[35:32] * 32))[31:0];
TMP_DEST[95:64] := (TMP_SRC2[511:0] >> (SRC1[67:64] * 32))[31:0];
TMP_DEST[127:96] := (TMP_SRC2[511:0] >> (SRC1[99:96] * 32))[31:0];
TMP_DEST[159:128] := (TMP_SRC2[511:0] >> (SRC1[131:128] * 32))[31:0];
TMP_DEST[191:160] := (TMP_SRC2[511:0] >> (SRC1[163:160] * 32))[31:0];
TMP_DEST[223:192] := (TMP_SRC2[511:0] >> (SRC1[195:192] * 32))[31:0];
TMP_DEST[255:224] := (TMP_SRC2[511:0] >> (SRC1[227:224] * 32))[31:0];
TMP_DEST[287:256] := (TMP_SRC2[511:0] >> (SRC1[259:256] * 32))[31:0];
TMP_DEST[319:288] := (TMP_SRC2[511:0] >> (SRC1[291:288] * 32))[31:0];
TMP_DEST[351:320] := (TMP_SRC2[511:0] >> (SRC1[323:320] * 32))[31:0];
TMP_DEST[383:352] := (TMP_SRC2[511:0] >> (SRC1[355:352] * 32))[31:0];
TMP_DEST[415:384] := (TMP_SRC2[511:0] >> (SRC1[387:384] * 32))[31:0];
TMP_DEST[447:416] := (TMP_SRC2[511:0] >> (SRC1[419:416] * 32))[31:0];
TMP_DEST[479:448] :=(TMP_SRC2[511:0] >> (SRC1[451:448] * 32))[31:0];
TMP_DEST[511:480] := (TMP_SRC2[511:0] >> (SRC1[483:480] * 32))[31:0];
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] := TMP_DEST[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
;zeroing-masking
FI;
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPERMPS (VEX.256 encoded version)
DEST[31:0] := (SRC2[255:0] >> (SRC1[2:0] * 32))[31:0];
DEST[63:32] := (SRC2[255:0] >> (SRC1[34:32] * 32))[31:0];
DEST[95:64] := (SRC2[255:0] >> (SRC1[66:64] * 32))[31:0];
DEST[127:96] := (SRC2[255:0] >> (SRC1[98:96] * 32))[31:0];
DEST[159:128] := (SRC2[255:0] >> (SRC1[130:128] * 32))[31:0];
DEST[191:160] := (SRC2[255:0] >> (SRC1[162:160] * 32))[31:0];
DEST[223:192] := (SRC2[255:0] >> (SRC1[194:192] * 32))[31:0];
DEST[255:224] := (SRC2[255:0] >> (SRC1[226:224] * 32))[31:0];
DEST[MAXVL-1:256] := 0
VPERMPS—Permute Single Precision Floating-Point Elements
Vol. 2C
5-491
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPERMPS __m512 _mm512_permutexvar_ps(__m512i i, __m512 a);
VPERMPS __m512 _mm512_mask_permutexvar_ps(__m512 s, __mmask16 k, __m512i i, __m512 a);
VPERMPS __m512 _mm512_maskz_permutexvar_ps( __mmask16 k, __m512i i, __m512 a);
VPERMPS __m256 _mm256_permutexvar_ps(__m256 i, __m256 a);
VPERMPS __m256 _mm256_mask_permutexvar_ps(__m256 s, __mmask8 k, __m256 i, __m256 a);
VPERMPS __m256 _mm256_maskz_permutexvar_ps( __mmask8 k, __m256 i, __m256 a);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
Additionally:
#UD
If VEX.L = 0.
EVEX-encoded instruction, see Table 2-50, “Type E4NF Class Exception Conditions.”
5-492
Vol. 2C
VPERMPS—Permute Single Precision Floating-Point Elements
INSTRUCTION SET REFERENCE, V
VPERMQ—Qwords Element Permutation
Opcode/
Op / En
64/32
CPUID
Description
Instruction
bit Mode
Feature
Support
Flag
VEX.256.66.0F3A.W1 00 /r ib
A
V/V
AVX2
Permute qwords in ymm2/m256 using indices in
VPERMQ ymm1, ymm2/m256, imm8
imm8 and store the result in ymm1.
EVEX.256.66.0F3A.W1 00 /r ib
B
V/V
AVX512VL
Permute qwords in ymm2/m256/m64bcst using
VPERMQ ymm1 {k1}{z},
AVX512F
indexes in imm8 and store the result in ymm1.
ymm2/m256/m64bcst, imm8
EVEX.512.66.0F3A.W1 00 /r ib
B
V/V
AVX512F
Permute qwords in zmm2/m512/m64bcst using
VPERMQ zmm1 {k1}{z},
indices in imm8 and store the result in zmm1.
zmm2/m512/m64bcst, imm8
EVEX.256.66.0F38.W1 36 /r
C
V/V
AVX512VL
Permute qwords in ymm3/m256/m64bcst using
VPERMQ ymm1 {k1}{z}, ymm2,
AVX512F
indexes in ymm2 and store the result in ymm1.
ymm3/m256/m64bcst
EVEX.512.66.0F38.W1 36 /r
C
V/V
AVX512F
Permute qwords in zmm3/m512/m64bcst using
VPERMQ zmm1 {k1}{z}, zmm2,
indices in zmm2 and store the result in zmm1.
zmm3/m512/m64bcst
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (w)
ModRM:r/m (r)
imm8
N/A
B
Full
ModRM:reg (w)
ModRM:r/m (r)
imm8
N/A
C
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
The imm8 version: Copies quadwords from the source operand (the second operand) to the destination operand
(the first operand) according to the indices specified by the immediate operand (the third operand). Each two-bit
value in the immediate byte selects a qword element in the source operand.
VEX version: The source operand can be a YMM register or a memory location. Bits (MAXVL-1:256) of the corre-
sponding destination register are zeroed.
In EVEX.512 encoded version, The elements in the destination are updated using the writemask k1 and the imm8
bits are reused as control bits for the upper 256-bit half when the control bits are coming from immediate. The
source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit
memory location.
Immediate control versions: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will
#UD.
The vector control version: Copies quadwords from the second source operand (the third operand) to the destina-
tion operand (the first operand) according to the indices in the first source operand (the second operand). The first
3 bits of each 64 bit element in the index operand selects which quadword in the second source operand to copy.
The first and second operands are ZMM registers, the third operand can be a ZMM register, a 512-bit memory loca-
tion or a 512-bit vector broadcasted from a 64-bit memory location. The elements in the destination are updated
using the writemask k1.
Note that this instruction permits a qword in the source operand to be copied to multiple locations in the destination
operand.
If VPERMPQ is encoded with VEX.L= 0 or EVEX.128, an attempt to execute the instruction will cause an #UD excep-
tion.
VPERMQ—Qwords Element Permutation
Vol. 2C
5-493
INSTRUCTION SET REFERENCE, V
Operation
VPERMQ (EVEX - imm8 control forms)
(KL, VL) = (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN TMP_SRC[i+63:i] := SRC[63:0];
ELSE TMP_SRC[i+63:i] := SRC[i+63:i];
FI;
ENDFOR;
TMP_DEST[63:0] := (TMP_SRC[255:0] >> (IMM8[1:0] * 64))[63:0];
TMP_DEST[127:64] := (TMP_SRC[255:0] >> (IMM8[3:2] * 64))[63:0];
TMP_DEST[191:128] := (TMP_SRC[255:0] >> (IMM8[5:4] * 64))[63:0];
TMP_DEST[255:192] := (TMP_SRC[255:0] >> (IMM8[7:6] * 64))[63:0];
IF VL >= 512
TMP_DEST[319:256] := (TMP_SRC[511:256] >> (IMM8[1:0] * 64))[63:0];
TMP_DEST[383:320] := (TMP_SRC[511:256] >> (IMM8[3:2] * 64))[63:0];
TMP_DEST[447:384] := (TMP_SRC[511:256] >> (IMM8[5:4] * 64))[63:0];
TMP_DEST[511:448] := (TMP_SRC[511:256] >> (IMM8[7:6] * 64))[63:0];
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
;zeroing-masking
FI;
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPERMQ (EVEX - vector control forms)
(KL, VL) = (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN TMP_SRC2[i+63:i] := SRC2[63:0];
ELSE TMP_SRC2[i+63:i] := SRC2[i+63:i];
FI;
ENDFOR;
IF VL = 256
TMP_DEST[63:0] := (TMP_SRC2[255:0] >> (SRC1[1:0] * 64))[63:0];
TMP_DEST[127:64] := (TMP_SRC2[255:0] >> (SRC1[65:64] * 64))[63:0];
TMP_DEST[191:128] := (TMP_SRC2[255:0] >> (SRC1[129:128] * 64))[63:0];
TMP_DEST[255:192] := (TMP_SRC2[255:0] >> (SRC1[193:192] * 64))[63:0];
FI;
IF VL = 512
TMP_DEST[63:0] := (TMP_SRC2[511:0] >> (SRC1[2:0] * 64))[63:0];
TMP_DEST[127:64] := (TMP_SRC2[511:0] >> (SRC1[66:64] * 64))[63:0];
TMP_DEST[191:128] := (TMP_SRC2[511:0] >> (SRC1[130:128] * 64))[63:0];
TMP_DEST[255:192] := (TMP_SRC2[511:0] >> (SRC1[194:192] * 64))[63:0];
5-494
Vol. 2C
VPERMQ—Qwords Element Permutation
INSTRUCTION SET REFERENCE, V
TMP_DEST[319:256] := (TMP_SRC2[511:0] >> (SRC1[258:256] * 64))[63:0];
TMP_DEST[383:320] := (TMP_SRC2[511:0] >> (SRC1[322:320] * 64))[63:0];
TMP_DEST[447:384] := (TMP_SRC2[511:0] >> (SRC1[386:384] * 64))[63:0];
TMP_DEST[511:448] := (TMP_SRC2[511:0] >> (SRC1[450:448] * 64))[63:0];
FI;
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := TMP_DEST[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
;zeroing-masking
FI;
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPERMQ (VEX.256 encoded version)
DEST[63:0] := (SRC[255:0] >> (IMM8[1:0] * 64))[63:0];
DEST[127:64] := (SRC[255:0] >> (IMM8[3:2] * 64))[63:0];
DEST[191:128] := (SRC[255:0] >> (IMM8[5:4] * 64))[63:0];
DEST[255:192] := (SRC[255:0] >> (IMM8[7:6] * 64))[63:0];
DEST[MAXVL-1:256] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPERMQ __m512i _mm512_permutex_epi64( __m512i a, int imm);
VPERMQ __m512i _mm512_mask_permutex_epi64(__m512i s, __mmask8 k, __m512i a, int imm);
VPERMQ __m512i _mm512_maskz_permutex_epi64( __mmask8 k, __m512i a, int imm);
VPERMQ __m512i _mm512_permutexvar_epi64( __m512i a, __m512i b);
VPERMQ __m512i _mm512_mask_permutexvar_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPERMQ __m512i _mm512_maskz_permutexvar_epi64( __mmask8 k, __m512i a, __m512i b);
VPERMQ __m256i _mm256_permutex_epi64( __m256i a, int imm);
VPERMQ __m256i _mm256_mask_permutex_epi64(__m256i s, __mmask8 k, __m256i a, int imm);
VPERMQ __m256i _mm256_maskz_permutex_epi64( __mmask8 k, __m256i a, int imm);
VPERMQ __m256i _mm256_permutexvar_epi64( __m256i a, __m256i b);
VPERMQ __m256i _mm256_mask_permutexvar_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPERMQ __m256i _mm256_maskz_permutexvar_epi64( __mmask8 k, __m256i a, __m256i b);
SIMD Floating-Point Exceptions
None
Other Exceptions
Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions.”
Additionally:
#UD
If VEX.L = 0.
If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Table 2-50, “Type E4NF Class Exception Conditions.”
Additionally:
#UD
If encoded with EVEX.128.
If EVEX.vvvv != 1111B and with imm8.
VPERMQ—Qwords Element Permutation
Vol. 2C
5-495
INSTRUCTION SET REFERENCE, V
VPERMT2B—Full Permute of Bytes From Two Tables Overwriting a Table
Opcode/
Op
64/32
CPUID Feature
Description
Instruction
/
bit Mode
Flag
En
Support
EVEX.128.66.0F38.W0 7D /r
A
V/V
AVX512VL
Permute bytes in xmm3/m128 and xmm1 using byte
VPERMT2B xmm1 {k1}{z}, xmm2,
AVX512_VBMI
indexes in xmm2 and store the byte results in xmm1
xmm3/m128
using writemask k1.
EVEX.256.66.0F38.W0 7D /r
A
V/V
AVX512VL
Permute bytes in ymm3/m256 and ymm1 using byte
VPERMT2B ymm1 {k1}{z}, ymm2,
AVX512_VBMI
indexes in ymm2 and store the byte results in ymm1
ymm3/m256
using writemask k1.
EVEX.512.66.0F38.W0 7D /r
A
V/V
AVX512_VBMI
Permute bytes in zmm3/m512 and zmm1 using byte
VPERMT2B zmm1 {k1}{z}, zmm2,
indexes in zmm2 and store the byte results in zmm1
zmm3/m512
using writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Permutes byte values from two tables, comprising of the first operand (also the destination operand) and the third
operand (the second source operand). The second operand (the first source operand) provides byte indices to
select byte results from the two tables. The selected byte elements are written to the destination at byte granu-
larity under the writemask k1.
The first and second operands are ZMM/YMM/XMM registers. The second operand contains input indices to select
elements from the two input tables in the 1st and 3rd operands. The first operand is also the destination of the
result. The second source operand can be a ZMM/YMM/XMM register, or a 512/256/128-bit memory location. In
each index byte, the id bit for table selection is bit 6/5/4, and bits [5:0]/[4:0]/[3:0] selects element within each
input table.
Note that these instructions permit a byte value in the source operands to be copied to more than one location in
the destination operand. Also, the second table and the indices can be reused in subsequent iterations, but the first
table is overwritten.
Bits (MAX_VL-1:256/128) of the destination are zeroed for VL=256,128.
5-496
Vol. 2C
VPERMT2B—Full Permute of Bytes From Two Tables Overwriting a Table
INSTRUCTION SET REFERENCE, V
Operation
VPERMT2B (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
IF VL = 128:
id := 3;
ELSE IF VL = 256:
id := 4;
ELSE IF VL = 512:
id := 5;
FI;
TMP_DEST[VL-1:0] := DEST[VL-1:0];
FOR j := 0 TO KL-1
off := 8*SRC1[j*8 + id: j*8] ;
IF k1[j] OR *no writemask*:
DEST[j*8 + 7: j*8] := SRC1[j*8+id+1]? SRC2[off+7:off] : TMP_DEST[off+7:off];
ELSE IF *zeroing-masking*
DEST[j*8 + 7: j*8] := 0;
*ELSE
DEST[j*8 + 7: j*8] remains unchanged*
FI;
ENDFOR
DEST[MAX_VL-1:VL] := 0;
Intel C/C++ Compiler Intrinsic Equivalent
VPERMT2B __m512i _mm512_permutex2var_epi8(__m512i a, __m512i idx, __m512i b);
VPERMT2B __m512i _mm512_mask_permutex2var_epi8(__m512i a, __mmask64 k, __m512i idx, __m512i b);
VPERMT2B __m512i _mm512_maskz_permutex2var_epi8(__mmask64 k, __m512i a, __m512i idx, __m512i b);
VPERMT2B __m256i _mm256_permutex2var_epi8(__m256i a, __m256i idx, __m256i b);
VPERMT2B __m256i _mm256_mask_permutex2var_epi8(__m256i a, __mmask32 k, __m256i idx, __m256i b);
VPERMT2B __m256i _mm256_maskz_permutex2var_epi8(__mmask32 k, __m256i a, __m256i idx, __m256i b);
VPERMT2B __m128i _mm_permutex2var_epi8(__m128i a, __m128i idx, __m128i b);
VPERMT2B __m128i _mm_mask_permutex2var_epi8(__m128i a, __mmask16 k, __m128i idx, __m128i b);
VPERMT2B __m128i _mm_maskz_permutex2var_epi8(__mmask16 k, __m128i a, __m128i idx, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions.”
VPERMT2B—Full Permute of Bytes From Two Tables Overwriting a Table
Vol. 2C
5-497
INSTRUCTION SET REFERENCE, V
VPERMT2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting One Table
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W1 7D /r
A
V/V
AVX512VL
Permute word integers from two tables in xmm3/m128
VPERMT2W xmm1 {k1}{z}, xmm2,
AVX512BW
and xmm1 using indexes in xmm2 and store the result in
xmm3/m128
xmm1 using writemask k1.
EVEX.256.66.0F38.W1 7D /r
A
V/V
AVX512VL
Permute word integers from two tables in ymm3/m256
VPERMT2W ymm1 {k1}{z}, ymm2,
AVX512BW
and ymm1 using indexes in ymm2 and store the result in
ymm3/m256
ymm1 using writemask k1.
EVEX.512.66.0F38.W1 7D /r
A
V/V
AVX512BW
Permute word integers from two tables in zmm3/m512
VPERMT2W zmm1 {k1}{z}, zmm2,
and zmm1 using indexes in zmm2 and store the result in
zmm3/m512
zmm1 using writemask k1.
EVEX.128.66.0F38.W0 7E /r
B
V/V
AVX512VL
Permute double-words from two tables in
VPERMT2D xmm1 {k1}{z}, xmm2,
AVX512F
xmm3/m128/m32bcst and xmm1 using indexes in xmm2
xmm3/m128/m32bcst
and store the result in xmm1 using writemask k1.
EVEX.256.66.0F38.W0 7E /r
B
V/V
AVX512VL
Permute double-words from two tables in
VPERMT2D ymm1 {k1}{z}, ymm2,
AVX512F
ymm3/m256/m32bcst and ymm1 using indexes in ymm2
ymm3/m256/m32bcst
and store the result in ymm1 using writemask k1.
EVEX.512.66.0F38.W0 7E /r
B
V/V
AVX512F
Permute double-words from two tables in
VPERMT2D zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst and zmm1 using indices in zmm2
zmm3/m512/m32bcst
and store the result in zmm1 using writemask k1.
EVEX.128.66.0F38.W1 7E /r
B
V/V
AVX512VL
Permute quad-words from two tables in
VPERMT2Q xmm1 {k1}{z}, xmm2,
AVX512F
xmm3/m128/m64bcst and xmm1 using indexes in xmm2
xmm3/m128/m64bcst
and store the result in xmm1 using writemask k1.
EVEX.256.66.0F38.W1 7E /r
B
V/V
AVX512VL
Permute quad-words from two tables in
VPERMT2Q ymm1 {k1}{z}, ymm2,
AVX512F
ymm3/m256/m64bcst and ymm1 using indexes in ymm2
ymm3/m256/m64bcst
and store the result in ymm1 using writemask k1.
EVEX.512.66.0F38.W1 7E /r
B
V/V
AVX512F
Permute quad-words from two tables in
VPERMT2Q zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst and zmm1 using indices in zmm2
zmm3/m512/m64bcst
and store the result in zmm1 using writemask k1.
EVEX.128.66.0F38.W0 7F /r
B
V/V
AVX512VL
Permute single-precision floating-point values from two
VPERMT2PS xmm1 {k1}{z},
AVX512F
tables in xmm3/m128/m32bcst and xmm1 using indexes in
xmm2, xmm3/m128/m32bcst
xmm2 and store the result in xmm1 using writemask k1.
EVEX.256.66.0F38.W0 7F /r
B
V/V
AVX512VL
Permute single-precision floating-point values from two
VPERMT2PS ymm1 {k1}{z},
AVX512F
tables in ymm3/m256/m32bcst and ymm1 using indexes in
ymm2, ymm3/m256/m32bcst
ymm2 and store the result in ymm1 using writemask k1.
EVEX.512.66.0F38.W0 7F /r
B
V/V
AVX512F
Permute single-precision floating-point values from two
VPERMT2PS zmm1 {k1}{z},
tables in zmm3/m512/m32bcst and zmm1 using indices in
zmm2, zmm3/m512/m32bcst
zmm2 and store the result in zmm1 using writemask k1.
EVEX.128.66.0F38.W1 7F /r
B
V/V
AVX512VL
Permute double precision floating-point values from two
VPERMT2PD xmm1 {k1}{z},
AVX512F
tables in xmm3/m128/m64bcst and xmm1 using indexes in
xmm2, xmm3/m128/m64bcst
xmm2 and store the result in xmm1 using writemask k1.
EVEX.256.66.0F38.W1 7F /r
B
V/V
AVX512VL
Permute double precision floating-point values from two
VPERMT2PD ymm1 {k1}{z},
AVX512F
tables in ymm3/m256/m64bcst and ymm1 using indexes in
ymm2, ymm3/m256/m64bcst
ymm2 and store the result in ymm1 using writemask k1.
EVEX.512.66.0F38.W1 7F /r
B
V/V
AVX512F
Permute double precision floating-point values from two
VPERMT2PD zmm1 {k1}{z},
tables in zmm3/m512/m64bcst and zmm1 using indices in
zmm2, zmm3/m512/m64bcst
zmm2 and store the result in zmm1 using writemask k1.
5-498
Vol. 2C
VPERMT2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting One Table
INSTRUCTION SET REFERENCE, V
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full Mem
ModRM:reg (r,w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
B
Full
ModRM:reg (r, w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Permutes 16-bit/32-bit/64-bit values in the first operand and the third operand (the second source operand) using
indices in the second operand (the first source operand) to select elements from the first and third operands. The
selected elements are written to the destination operand (the first operand) according to the writemask k1.
The first and second operands are ZMM/YMM/XMM registers. The second operand contains input indices to select
elements from the two input tables in the 1st and 3rd operands. The first operand is also the destination of the
result.
D/Q/PS/PD element versions: The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit
memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. Broadcast from the
low 32/64-bit memory location is performed if EVEX.b and the id bit for table selection are set (selecting table_2).
Dword/PS versions: The id bit for table selection is bit 4/3/2, depending on VL=512, 256, 128. Bits
[3:0]/[2:0]/[1:0] of each element in the input index vector select an element within the two source operands, If
the id bit is 0, table_1 (the first source) is selected; otherwise the second source operand is selected.
Qword/PD versions: The id bit for table selection is bit 3/2/1, and bits [2:0]/[1:0] /bit 0 selects element within each
input table.
Word element versions: The second source operand can be a ZMM/YMM/XMM register, or a 512/256/128-bit
memory location. The id bit for table selection is bit 5/4/3, and bits [4:0]/[3:0]/[2:0] selects element within each
input table.
Note that these instructions permit a 16-bit/32-bit/64-bit value in the source operands to be copied to more than
one location in the destination operand. Note also that in this case, the same index can be reused for example for
a second iteration, while the table elements being permuted are overwritten.
Bits (MAXVL-1:256/128) of the destination are zeroed for VL=256,128.
Operation
VPERMT2W (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
id := 2
FI;
IF VL = 256
id := 3
FI;
IF VL = 512
id := 4
FI;
TMP_DEST := DEST
FOR j := 0 TO KL-1
i := j * 16
off := 16*SRC1[i+id:i]
IF k1[j] OR *no writemask*
THEN
DEST[i+15:i]=SRC1[i+id+1] ? SRC2[off+15:off]
: TMP_DEST[off+15:off]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+15:i] remains unchanged*
ELSE
; zeroing-masking
VPERMT2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting One Table
Vol. 2C
5-499
INSTRUCTION SET REFERENCE, V
DEST[i+15:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPERMT2D/VPERMT2PS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF VL = 128
id := 1
FI;
IF VL = 256
id := 2
FI;
IF VL = 512
id := 3
FI;
TMP_DEST := DEST
FOR j := 0 TO KL-1
i := j * 32
off := 32*SRC1[i+id:i]
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i] := SRC1[i+id+1] ? SRC2[31:0]
: TMP_DEST[off+31:off]
ELSE
DEST[i+31:i] := SRC1[i+id+1] ? SRC2[off+31:off]
: TMP_DEST[off+31:off]
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VPERMT2Q/VPERMT2PD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8 512)
IF VL = 128
id := 0
FI;
IF VL = 256
id := 1
FI;
IF VL = 512
id := 2
FI;
TMP_DEST:= DEST
FOR j := 0 TO KL-1
5-500
Vol. 2C
VPERMT2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting One Table
INSTRUCTION SET REFERENCE, V
i := j * 64
off := 64*SRC1[i+id:i]
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i] := SRC1[i+id+1] ? SRC2[63:0]
: TMP_DEST[off+63:off]
ELSE
DEST[i+63:i] := SRC1[i+id+1] ? SRC2[off+63:off]
: TMP_DEST[off+63:off]
FI
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPERMT2D __m512i _mm512_permutex2var_epi32(__m512i a, __m512i idx, __m512i b);
VPERMT2D __m512i _mm512_mask_permutex2var_epi32(__m512i a, __mmask16 k, __m512i idx, __m512i b);
VPERMT2D __m512i _mm512_mask2_permutex2var_epi32(__m512i a, __m512i idx, __mmask16 k, __m512i b);
VPERMT2D __m512i _mm512_maskz_permutex2var_epi32(__mmask16 k, __m512i a, __m512i idx, __m512i b);
VPERMT2D __m256i _mm256_permutex2var_epi32(__m256i a, __m256i idx, __m256i b);
VPERMT2D __m256i _mm256_mask_permutex2var_epi32(__m256i a, __mmask8 k, __m256i idx, __m256i b);
VPERMT2D __m256i _mm256_mask2_permutex2var_epi32(__m256i a, __m256i idx, __mmask8 k, __m256i b);
VPERMT2D __m256i _mm256_maskz_permutex2var_epi32(__mmask8 k, __m256i a, __m256i idx, __m256i b);
VPERMT2D __m128i _mm_permutex2var_epi32(__m128i a, __m128i idx, __m128i b);
VPERMT2D __m128i _mm_mask_permutex2var_epi32(__m128i a, __mmask8 k, __m128i idx, __m128i b);
VPERMT2D __m128i _mm_mask2_permutex2var_epi32(__m128i a, __m128i idx, __mmask8 k, __m128i b);
VPERMT2D __m128i _mm_maskz_permutex2var_epi32(__mmask8 k, __m128i a, __m128i idx, __m128i b);
VPERMT2PD __m512d _mm512_permutex2var_pd(__m512d a, __m512i idx, __m512d b);
VPERMT2PD __m512d _mm512_mask_permutex2var_pd(__m512d a, __mmask8 k, __m512i idx, __m512d b);
VPERMT2PD __m512d _mm512_mask2_permutex2var_pd(__m512d a, __m512i idx, __mmask8 k, __m512d b);
VPERMT2PD __m512d _mm512_maskz_permutex2var_pd(__mmask8 k, __m512d a, __m512i idx, __m512d b);
VPERMT2PD __m256d _mm256_permutex2var_pd(__m256d a, __m256i idx, __m256d b);
VPERMT2PD __m256d _mm256_mask_permutex2var_pd(__m256d a, __mmask8 k, __m256i idx, __m256d b);
VPERMT2PD __m256d _mm256_mask2_permutex2var_pd(__m256d a, __m256i idx, __mmask8 k, __m256d b);
VPERMT2PD __m256d _mm256_maskz_permutex2var_pd(__mmask8 k, __m256d a, __m256i idx, __m256d b);
VPERMT2PD __m128d _mm_permutex2var_pd(__m128d a, __m128i idx, __m128d b);
VPERMT2PD __m128d _mm_mask_permutex2var_pd(__m128d a, __mmask8 k, __m128i idx, __m128d b);
VPERMT2PD __m128d _mm_mask2_permutex2var_pd(__m128d a, __m128i idx, __mmask8 k, __m128d b);
VPERMT2PD __m128d _mm_maskz_permutex2var_pd(__mmask8 k, __m128d a, __m128i idx, __m128d b);
VPERMT2PS __m512 _mm512_permutex2var_ps(__m512 a, __m512i idx, __m512 b);
VPERMT2PS __m512 _mm512_mask_permutex2var_ps(__m512 a, __mmask16 k, __m512i idx, __m512 b);
VPERMT2PS __m512 _mm512_mask2_permutex2var_ps(__m512 a, __m512i idx, __mmask16 k, __m512 b);
VPERMT2PS __m512 _mm512_maskz_permutex2var_ps(__mmask16 k, __m512 a, __m512i idx, __m512 b);
VPERMT2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting One Table
Vol. 2C
5-501
INSTRUCTION SET REFERENCE, V
VPERMT2PS __m256 _mm256_permutex2var_ps(__m256 a, __m256i idx, __m256 b);
VPERMT2PS __m256 _mm256_mask_permutex2var_ps(__m256 a, __mmask8 k, __m256i idx, __m256 b);
VPERMT2PS __m256 _mm256_mask2_permutex2var_ps(__m256 a, __m256i idx, __mmask8 k, __m256 b);
VPERMT2PS __m256 _mm256_maskz_permutex2var_ps(__mmask8 k, __m256 a, __m256i idx, __m256 b);
VPERMT2PS __m128 _mm_permutex2var_ps(__m128 a, __m128i idx, __m128 b);
VPERMT2PS __m128 _mm_mask_permutex2var_ps(__m128 a, __mmask8 k, __m128i idx, __m128 b);
VPERMT2PS __m128 _mm_mask2_permutex2var_ps(__m128 a, __m128i idx, __mmask8 k, __m128 b);
VPERMT2PS __m128 _mm_maskz_permutex2var_ps(__mmask8 k, __m128 a, __m128i idx, __m128 b);
VPERMT2Q __m512i _mm512_permutex2var_epi64(__m512i a, __m512i idx, __m512i b);
VPERMT2Q __m512i _mm512_mask_permutex2var_epi64(__m512i a, __mmask8 k, __m512i idx, __m512i b);
VPERMT2Q __m512i _mm512_mask2_permutex2var_epi64(__m512i a, __m512i idx, __mmask8 k, __m512i b);
VPERMT2Q __m512i _mm512_maskz_permutex2var_epi64(__mmask8 k, __m512i a, __m512i idx, __m512i b);
VPERMT2Q __m256i _mm256_permutex2var_epi64(__m256i a, __m256i idx, __m256i b);
VPERMT2Q __m256i _mm256_mask_permutex2var_epi64(__m256i a, __mmask8 k, __m256i idx, __m256i b);
VPERMT2Q __m256i _mm256_mask2_permutex2var_epi64(__m256i a, __m256i idx, __mmask8 k, __m256i b);
VPERMT2Q __m256i _mm256_maskz_permutex2var_epi64(__mmask8 k, __m256i a, __m256i idx, __m256i b);
VPERMT2Q __m128i _mm_permutex2var_epi64(__m128i a, __m128i idx, __m128i b);
VPERMT2Q __m128i _mm_mask_permutex2var_epi64(__m128i a, __mmask8 k, __m128i idx, __m128i b);
VPERMT2Q __m128i _mm_mask2_permutex2var_epi64(__m128i a, __m128i idx, __mmask8 k, __m128i b);
VPERMT2Q __m128i _mm_maskz_permutex2var_epi64(__mmask8 k, __m128i a, __m128i idx, __m128i b);
VPERMT2W __m512i _mm512_permutex2var_epi16(__m512i a, __m512i idx, __m512i b);
VPERMT2W __m512i _mm512_mask_permutex2var_epi16(__m512i a, __mmask32 k, __m512i idx, __m512i b);
VPERMT2W __m512i _mm512_mask2_permutex2var_epi16(__m512i a, __m512i idx, __mmask32 k, __m512i b);
VPERMT2W __m512i _mm512_maskz_permutex2var_epi16(__mmask32 k, __m512i a, __m512i idx, __m512i b);
VPERMT2W __m256i _mm256_permutex2var_epi16(__m256i a, __m256i idx, __m256i b);
VPERMT2W __m256i _mm256_mask_permutex2var_epi16(__m256i a, __mmask16 k, __m256i idx, __m256i b);
VPERMT2W __m256i _mm256_mask2_permutex2var_epi16(__m256i a, __m256i idx, __mmask16 k, __m256i b);
VPERMT2W __m256i _mm256_maskz_permutex2var_epi16(__mmask16 k, __m256i a, __m256i idx, __m256i b);
VPERMT2W __m128i _mm_permutex2var_epi16(__m128i a, __m128i idx, __m128i b);
VPERMT2W __m128i _mm_mask_permutex2var_epi16(__m128i a, __mmask8 k, __m128i idx, __m128i b);
VPERMT2W __m128i _mm_mask2_permutex2var_epi16(__m128i a, __m128i idx, __mmask8 k, __m128i b);
VPERMT2W __m128i _mm_maskz_permutex2var_epi16(__mmask8 k, __m128i a, __m128i idx, __m128i b);
SIMD Floating-Point Exceptions
None.
Other Exceptions
VPERMT2D/Q/PS/PD: See Table 2-50, “Type E4NF Class Exception Conditions.”
VPERMT2W: See Exceptions Type E4NF.nb in Table 2-50, “Type E4NF Class Exception Conditions.”
5-502
Vol. 2C
VPERMT2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting One Table
INSTRUCTION SET REFERENCE, V
VPEXPANDB/VPEXPANDW—Expand Byte/Word Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.0F38.W0 62 /r
A
V/V
AVX512_VBMI2
Expands up to 128 bits of packed byte values
VPEXPANDB xmm1{k1}{z}, m128
AVX512VL
from m128 to xmm1 with writemask k1.
EVEX.128.66.0F38.W0 62 /r
B
V/V
AVX512_VBMI2
Expands up to 128 bits of packed byte values
VPEXPANDB xmm1{k1}{z}, xmm2
AVX512VL
from xmm2 to xmm1 with writemask k1.
EVEX.256.66.0F38.W0 62 /r
A
V/V
AVX512_VBMI2
Expands up to 256 bits of packed byte values
VPEXPANDB ymm1{k1}{z}, m256
AVX512VL
from m256 to ymm1 with writemask k1.
EVEX.256.66.0F38.W0 62 /r
B
V/V
AVX512_VBMI2
Expands up to 256 bits of packed byte values
VPEXPANDB ymm1{k1}{z}, ymm2
AVX512VL
from ymm2 to ymm1 with writemask k1.
EVEX.512.66.0F38.W0 62 /r
A
V/V
AVX512_VBMI2
Expands up to 512 bits of packed byte values
VPEXPANDB zmm1{k1}{z}, m512
from m512 to zmm1 with writemask k1.
EVEX.512.66.0F38.W0 62 /r
B
V/V
AVX512_VBMI2
Expands up to 512 bits of packed byte values
VPEXPANDB zmm1{k1}{z}, zmm2
from zmm2 to zmm1 with writemask k1.
EVEX.128.66.0F38.W1 62 /r
A
V/V
AVX512_VBMI2
Expands up to 128 bits of packed word values
VPEXPANDW xmm1{k1}{z}, m128
AVX512VL
from m128 to xmm1 with writemask k1.
EVEX.128.66.0F38.W1 62 /r
B
V/V
AVX512_VBMI2
Expands up to 128 bits of packed word values
VPEXPANDW xmm1{k1}{z}, xmm2
AVX512VL
from xmm2 to xmm1 with writemask k1.
EVEX.256.66.0F38.W1 62 /r
A
V/V
AVX512_VBMI2
Expands up to 256 bits of packed word values
VPEXPANDW ymm1{k1}{z}, m256
AVX512VL
from m256 to ymm1 with writemask k1.
EVEX.256.66.0F38.W1 62 /r
B
V/V
AVX512_VBMI2
Expands up to 256 bits of packed word values
VPEXPANDW ymm1{k1}{z}, ymm2
AVX512VL
from ymm2 to ymm1 with writemask k1.
EVEX.512.66.0F38.W1 62 /r
A
V/V
AVX512_VBMI2
Expands up to 512 bits of packed word values
VPEXPANDW zmm1{k1}{z}, m512
from m512 to zmm1 with writemask k1.
EVEX.512.66.0F38.W1 62 /r
B
V/V
AVX512_VBMI2
Expands up to 512 bits of packed byte integer
VPEXPANDW zmm1{k1}{z}, zmm2
values from zmm2 to zmm1 with writemask
k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Expands (loads) up to 64 byte integer values or 32 word integer values from the source operand (memory
operand) to the destination operand (register operand), based on the active elements determined by the
writemask operand.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Moves 128, 256 or 512 bits of packed byte integer values from the source operand (memory operand) to the desti-
nation operand (register operand). This instruction is used to load from an int8 vector register or memory location
while inserting the data into sparse elements of destination vector register using the active elements pointed out
by the operand writemask.
This instruction supports memory fault suppression.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
VPEXPANDB/VPEXPANDW—Expand Byte/Word Values
Vol. 2C
5-503
INSTRUCTION SET REFERENCE, V
Operation
VPEXPANDB
(KL, VL) = (16, 128), (32, 256), (64, 512)
k := 0
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
DEST.byte[j] := SRC.byte[k];
k := k + 1
ELSE:
IF *merging-masking*:
*DEST.byte[j] remains unchanged*
ELSE:
; zeroing-masking
DEST.byte[j] := 0
DEST[MAX_VL-1:VL] := 0
VPEXPANDW
(KL, VL) = (8,128), (16,256), (32, 512)
k := 0
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
DEST.word[j] := SRC.word[k];
k := k + 1
ELSE:
IF *merging-masking*:
*DEST.word[j] remains unchanged*
ELSE:
; zeroing-masking
DEST.word[j] := 0
DEST[MAX_VL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VPEXPAND __m128i _mm_mask_expand_epi8(__m128i, __mmask16, __m128i);
VPEXPAND __m128i _mm_maskz_expand_epi8(__mmask16, __m128i);
VPEXPAND __m128i _mm_mask_expandloadu_epi8(__m128i, __mmask16, const void*);
VPEXPAND __m128i _mm_maskz_expandloadu_epi8(__mmask16, const void*);
VPEXPAND __m256i _mm256_mask_expand_epi8(__m256i, __mmask32, __m256i);
VPEXPAND __m256i _mm256_maskz_expand_epi8(__mmask32, __m256i);
VPEXPAND __m256i _mm256_mask_expandloadu_epi8(__m256i, __mmask32, const void*);
VPEXPAND __m256i _mm256_maskz_expandloadu_epi8(__mmask32, const void*);
VPEXPAND __m512i _mm512_mask_expand_epi8(__m512i, __mmask64, __m512i);
VPEXPAND __m512i _mm512_maskz_expand_epi8(__mmask64, __m512i);
VPEXPAND __m512i _mm512_mask_expandloadu_epi8(__m512i, __mmask64, const void*);
VPEXPAND __m512i _mm512_maskz_expandloadu_epi8(__mmask64, const void*);
VPEXPANDW __m128i _mm_mask_expand_epi16(__m128i, __mmask8, __m128i);
VPEXPANDW __m128i _mm_maskz_expand_epi16(__mmask8, __m128i);
VPEXPANDW __m128i _mm_mask_expandloadu_epi16(__m128i, __mmask8, const void*);
VPEXPANDW __m128i _mm_maskz_expandloadu_epi16(__mmask8, const void *);
VPEXPANDW __m256i _mm256_mask_expand_epi16(__m256i, __mmask16, __m256i);
VPEXPANDW __m256i _mm256_maskz_expand_epi16(__mmask16, __m256i);
VPEXPANDW __m256i _mm256_mask_expandloadu_epi16(__m256i, __mmask16, const void*);
VPEXPANDW __m256i _mm256_maskz_expandloadu_epi16(__mmask16, const void*);
VPEXPANDW __m512i _mm512_mask_expand_epi16(__m512i, __mmask32, __m512i);
VPEXPANDW __m512i _mm512_maskz_expand_epi16(__mmask32, __m512i);
VPEXPANDW __m512i _mm512_mask_expandloadu_epi16(__m512i, __mmask32, const void*);
VPEXPANDW __m512i _mm512_maskz_expandloadu_epi16(__mmask32, const void*);
5-504
Vol. 2C
VPEXPANDB/VPEXPANDW—Expand Byte/Word Values
INSTRUCTION SET REFERENCE, V
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-49, “Type E4 Class Exception Conditions.”
VPEXPANDB/VPEXPANDW—Expand Byte/Word Values
Vol. 2C
5-505
INSTRUCTION SET REFERENCE, V
VPEXPANDD—Load Sparse Packed Doubleword Integer Values From Dense Memory/Register
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W0 89 /r
A
V/V
AVX512VL
Expand packed double-word integer values from
VPEXPANDD xmm1 {k1}{z},
AVX512F
xmm2/m128 to xmm1 using writemask k1.
xmm2/m128
EVEX.256.66.0F38.W0 89 /r
A
V/V
AVX512VL
Expand packed double-word integer values from
VPEXPANDD ymm1 {k1}{z},
AVX512F
ymm2/m256 to ymm1 using writemask k1.
ymm2/m256
EVEX.512.66.0F38.W0 89 /r
A
V/V
AVX512F
Expand packed double-word integer values from
VPEXPANDD zmm1 {k1}{z},
zmm2/m512 to zmm1 using writemask k1.
zmm2/m512
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Expand (load) up to 16 contiguous doubleword integer values of the input vector in the source operand (the second
operand) to sparse elements in the destination operand (the first operand), selected by the writemask k1. The
destination operand is a ZMM register, the source operand can be a ZMM register or memory location.
The input vector starts from the lowest element in the source operand. The opmask register k1 selects the destina-
tion elements (a partial vector or sparse elements if less than 8 elements) to be replaced by the ascending
elements in the input vector. Destination elements not selected by the writemask k1 are either unmodified or
zeroed, depending on EVEX.z.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
Operation
VPEXPANDD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
k := 0
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN
DEST[i+31:i] := SRC[k+31:k];
k := k + 32
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
5-506
Vol. 2C
VPEXPANDD—Load Sparse Packed Doubleword Integer Values From Dense Memory/Register
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPEXPANDD __m512i _mm512_mask_expandloadu_epi32(__m512i s, __mmask16 k, void * a);
VPEXPANDD __m512i _mm512_maskz_expandloadu_epi32( __mmask16 k, void * a);
VPEXPANDD __m512i _mm512_mask_expand_epi32(__m512i s, __mmask16 k, __m512i a);
VPEXPANDD __m512i _mm512_maskz_expand_epi32( __mmask16 k, __m512i a);
VPEXPANDD __m256i _mm256_mask_expandloadu_epi32(__m256i s, __mmask8 k, void * a);
VPEXPANDD __m256i _mm256_maskz_expandloadu_epi32( __mmask8 k, void * a);
VPEXPANDD __m256i _mm256_mask_expand_epi32(__m256i s, __mmask8 k, __m256i a);
VPEXPANDD __m256i _mm256_maskz_expand_epi32( __mmask8 k, __m256i a);
VPEXPANDD __m128i _mm_mask_expandloadu_epi32(__m128i s, __mmask8 k, void * a);
VPEXPANDD __m128i _mm_maskz_expandloadu_epi32( __mmask8 k, void * a);
VPEXPANDD __m128i _mm_mask_expand_epi32(__m128i s, __mmask8 k, __m128i a);
VPEXPANDD __m128i _mm_maskz_expand_epi32( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VPEXPANDD—Load Sparse Packed Doubleword Integer Values From Dense Memory/Register
Vol. 2C
5-507
INSTRUCTION SET REFERENCE, V
VPEXPANDQ—Load Sparse Packed Quadword Integer Values From Dense Memory/Register
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W1 89 /r
A
V/V
AVX512VL
Expand packed quad-word integer values from
VPEXPANDQ xmm1 {k1}{z}, xmm2/m128
AVX512F
xmm2/m128 to xmm1 using writemask k1.
EVEX.256.66.0F38.W1 89 /r
A
V/V
AVX512VL
Expand packed quad-word integer values from
VPEXPANDQ ymm1 {k1}{z}, ymm2/m256
AVX512F
ymm2/m256 to ymm1 using writemask k1.
EVEX.512.66.0F38.W1 89 /r
A
V/V
AVX512F
Expand packed quad-word integer values from
VPEXPANDQ zmm1 {k1}{z}, zmm2/m512
zmm2/m512 to zmm1 using writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Expand (load) up to 8 quadword integer values from the source operand (the second operand) to sparse elements
in the destination operand (the first operand), selected by the writemask k1. The destination operand is a ZMM
register, the source operand can be a ZMM register or memory location.
The input vector starts from the lowest element in the source operand. The opmask register k1 selects the destina-
tion elements (a partial vector or sparse elements if less than 8 elements) to be replaced by the ascending
elements in the input vector. Destination elements not selected by the writemask k1 are either unmodified or
zeroed, depending on EVEX.z.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.
Operation
VPEXPANDQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
k := 0
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
DEST[i+63:i] := SRC[k+63:k];
k := k + 64
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
5-508
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VPEXPANDQ—Load Sparse Packed Quadword Integer Values From Dense Memory/Register
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPEXPANDQ __m512i _mm512_mask_expandloadu_epi64(__m512i s, __mmask8 k, void * a);
VPEXPANDQ __m512i _mm512_maskz_expandloadu_epi64( __mmask8 k, void * a);
VPEXPANDQ __m512i _mm512_mask_expand_epi64(__m512i s, __mmask8 k, __m512i a);
VPEXPANDQ __m512i _mm512_maskz_expand_epi64( __mmask8 k, __m512i a);
VPEXPANDQ __m256i _mm256_mask_expandloadu_epi64(__m256i s, __mmask8 k, void * a);
VPEXPANDQ __m256i _mm256_maskz_expandloadu_epi64( __mmask8 k, void * a);
VPEXPANDQ __m256i _mm256_mask_expand_epi64(__m256i s, __mmask8 k, __m256i a);
VPEXPANDQ __m256i _mm256_maskz_expand_epi64( __mmask8 k, __m256i a);
VPEXPANDQ __m128i _mm_mask_expandloadu_epi64(__m128i s, __mmask8 k, void * a);
VPEXPANDQ __m128i _mm_maskz_expandloadu_epi64( __mmask8 k, void * a);
VPEXPANDQ __m128i _mm_mask_expand_epi64(__m128i s, __mmask8 k, __m128i a);
VPEXPANDQ __m128i _mm_maskz_expand_epi64( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VPEXPANDQ—Load Sparse Packed Quadword Integer Values From Dense Memory/Register
Vol. 2C
5-509
INSTRUCTION SET REFERENCE, V
VPGATHERDD/VPGATHERQD—Gather Packed Dword Values Using Signed Dword/Qword Indices
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
-bit
Feature
Mode
Flag
VEX.128.66.0F38.W0 90 /r
RMV
V/V
AVX2
Using dword indices specified in vm32x, gather dword val-
VPGATHERDD xmm1, vm32x, xmm2
ues from memory conditioned on mask specified by xmm2.
Conditionally gathered elements are merged into xmm1.
VEX.128.66.0F38.W0 91 /r
RMV
V/V
AVX2
Using qword indices specified in vm64x, gather dword val-
VPGATHERQD xmm1, vm64x, xmm2
ues from memory conditioned on mask specified by xmm2.
Conditionally gathered elements are merged into xmm1.
VEX.256.66.0F38.W0 90 /r
RMV
V/V
AVX2
Using dword indices specified in vm32y, gather dword
VPGATHERDD ymm1, vm32y, ymm2
from memory conditioned on mask specified by ymm2.
Conditionally gathered elements are merged into ymm1.
VEX.256.66.0F38.W0 91 /r
RMV
V/V
AVX2
Using qword indices specified in vm64y, gather dword val-
VPGATHERQD xmm1, vm64y, xmm2
ues from memory conditioned on mask specified by xmm2.
Conditionally gathered elements are merged into xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMV
ModRM:reg (r,w)
BaseReg (R): VSIB:base,
VEX.vvvv (r, w)
N/A
VectorReg(R): VSIB:index
Description
The instruction conditionally loads up to 4 or 8 dword values from memory addresses specified by the memory
operand (the second operand) and using dword indices. The memory operand uses the VSIB form of the SIB byte
to specify a general purpose register operand as the common base, a vector register for an array of indices relative
to the base and a constant scale factor.
The mask operand (the third operand) specifies the conditional load operation from each memory address and the
corresponding update of each data element of the destination operand (the first operand). Conditionality is speci-
fied by the most significant bit of each data element of the mask register. If an element’s mask bit is not set, the
corresponding element of the destination register is left unchanged. The width of data element in the destination
register and mask register are identical. The entire mask register will be set to zero by this instruction unless the
instruction causes an exception.
Using qword indices, the instruction conditionally loads up to 2 or 4 qword values from the VSIB addressing
memory operand, and updates the lower half of the destination register. The upper 128 or 256 bits of the destina-
tion register are zero’ed with qword indices.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask operand are partially updated; those elements that have been gathered are placed into the
destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gath-
ered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
If the data size and index size are different, part of the destination register and part of the mask register do not
correspond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both
of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception
before gathering any elements.
VEX.128 version: For dword indices, the instruction will gather four dword values. For qword indices, the instruction
will gather two values and zero the upper 64 bits of the destination.
VEX.256 version: For dword indices, the instruction will gather eight dword values. For qword indices, the instruc-
tion will gather four values and zero the upper 128 bits of the destination.
Note that:
• If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault.
5-510
Vol. 2C
VPGATHERDD/VPGATHERQD—Gather Packed Dword Values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V
• The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
64 memory-ordering model.
• Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer
to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the
conventional order.
• Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
• This instruction does not perform AC checks, and so will never deliver an AC fault.
• This instruction will cause a #UD if the address size attribute is 16-bit.
• This instruction will cause a #UD if the memory operand is encoded without the SIB byte.
• This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does
is implementation specific, and some implementations may use loads larger than the data element size or load
elements an indeterminate number of times.
• The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-
bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address
bits are ignored.
Operation
DEST := SRC1;
BASE_ADDR: base register encoded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;
SCALE: scale factor encoded by SIB:[7:6];
DISP: optional 1, 4 byte displacement;
MASK := SRC3;
VPGATHERDD (VEX.128 version)
MASK[MAXVL-1:128] := 0;
FOR j := 0 to 3
i := j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] := FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] := 0;
FI;
ENDFOR
FOR j := 0 to 3
i := j * 32;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX[i+31:i])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] := FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] := 0;
ENDFOR
DEST[MAXVL-1:128] := 0;
VPGATHERDD/VPGATHERQD—Gather Packed Dword Values Using Signed Dword/Qword Indices
Vol. 2C
5-511
INSTRUCTION SET REFERENCE, V
VPGATHERQD (VEX.128 version)
MASK[MAXVL-1:64] := 0;
FOR j := 0 to 3
i := j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] := FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] := 0;
FI;
ENDFOR
FOR j := 0 to 1
k := j * 64;
i := j * 32;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] := FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] := 0;
ENDFOR
DEST[MAXVL-1:64] := 0;
VPGATHERDD (VEX.256 version)
MASK[MAXVL-1:256] := 0;
FOR j := 0 to 7
i := j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] := FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] := 0;
FI;
ENDFOR
FOR j := 0 to 7
i := j * 32;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[i+31:i])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] := FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] := 0;
ENDFOR
DEST[MAXVL-1:256] := 0;
5-512
Vol. 2C
VPGATHERDD/VPGATHERQD—Gather Packed Dword Values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V
VPGATHERQD (VEX.256 version)
MASK[MAXVL-1:128] := 0;
FOR j := 0 to 7
i := j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] := FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] := 0;
FI;
ENDFOR
FOR j := 0 to 3
k := j * 64;
i := j * 32;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] := FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] := 0;
ENDFOR
DEST[MAXVL-1:128] := 0;
Intel C/C++ Compiler Intrinsic Equivalent
VPGATHERDD: __m128i _mm_i32gather_epi32 (int const * base, __m128i index, const int scale);
VPGATHERDD: __m128i _mm_mask_i32gather_epi32 (__m128i src, int const * base, __m128i index, __m128i mask, const int scale);
VPGATHERDD: __m256i _mm256_i32gather_epi32 ( int const * base, __m256i index, const int scale);
VPGATHERDD: __m256i _mm256_mask_i32gather_epi32 (__m256i src, int const * base, __m256i index, __m256i mask, const int
scale);
VPGATHERQD: __m128i _mm_i64gather_epi32 (int const * base, __m128i index, const int scale);
VPGATHERQD: __m128i _mm_mask_i64gather_epi32 (__m128i src, int const * base, __m128i index, __m128i mask, const int scale);
VPGATHERQD: __m128i _mm256_i64gather_epi32 (int const * base, __m256i index, const int scale);
VPGATHERQD: __m128i _mm256_mask_i64gather_epi32 (__m128i src, int const * base, __m256i index, __m128i mask, const int
scale);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-27, “Type 12 Class Exception Conditions.”
VPGATHERDD/VPGATHERQD—Gather Packed Dword Values Using Signed Dword/Qword Indices
Vol. 2C
5-513
INSTRUCTION SET REFERENCE, V
VPGATHERDD/VPGATHERDQ—Gather Packed Dword, Packed Qword With Signed Dword Indices
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W0 90 /vsib
A
V/V
AVX512VL
Using signed dword indices, gather dword values from
VPGATHERDD xmm1 {k1}, vm32x
AVX512F
memory using writemask k1 for merging-masking.
EVEX.256.66.0F38.W0 90 /vsib
A
V/V
AVX512VL
Using signed dword indices, gather dword values from
VPGATHERDD ymm1 {k1}, vm32y
AVX512F
memory using writemask k1 for merging-masking.
EVEX.512.66.0F38.W0 90 /vsib
A
V/V
AVX512F
Using signed dword indices, gather dword values from
VPGATHERDD zmm1 {k1}, vm32z
memory using writemask k1 for merging-masking.
EVEX.128.66.0F38.W1 90 /vsib
A
V/V
AVX512VL
Using signed dword indices, gather quadword values from
VPGATHERDQ xmm1 {k1}, vm32x
AVX512F
memory using writemask k1 for merging-masking.
EVEX.256.66.0F38.W1 90 /vsib
A
V/V
AVX512VL
Using signed dword indices, gather quadword values from
VPGATHERDQ ymm1 {k1}, vm32x
AVX512F
memory using writemask k1 for merging-masking.
EVEX.512.66.0F38.W1 90 /vsib
A
V/V
AVX512F
Using signed dword indices, gather quadword values from
VPGATHERDQ zmm1 {k1}, vm32y
memory using writemask k1 for merging-masking.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
BaseReg (R): VSIB:base,
A
Tuple1 Scalar
ModRM:reg (w)
N/A
N/A
VectorReg(R): VSIB:index
Description
A set of 16 or 8 doubleword/quadword memory locations pointed to by base address BASE_ADDR and index vector
VINDEX with scale SCALE are gathered. The result is written into vector zmm1. The elements are specified via the
VSIB (i.e., the index register is a zmm, holding packed indices). Elements will only be loaded if their corresponding
mask bit is one. If an element’s mask bit is not set, the corresponding element of the destination register (zmm1)
is left unchanged. The entire mask register will be set to zero by this instruction unless it triggers an exception.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask register (k1) are partially updated; those elements that have been gathered are placed into
the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already
gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruc-
tion breakpoint is not re-triggered when the instruction is continued.
If the data element size is less than the index element size, the higher part of the destination register and the mask
register do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may
update these unused elements to one or both of those registers even if the instruction triggers an exception, and
even if the instruction triggers the exception before gathering any elements.
Note that:
• The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
64 memory-ordering model.
• Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements
closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
in the conventional order.
• Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
• This instruction does not perform AC checks, and so will never deliver an AC fault.
• Not valid with 16-bit effective addresses. Will deliver a #UD fault.
• These instructions do not accept zeroing-masking since the 0 values in k1 are used to determine completion.
5-514
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VPGATHERDD/VPGATHERDQ—Gather Packed Dword, Packed Qword With Signed Dword Indices
INSTRUCTION SET REFERENCE, V
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has the same disp8*N and alignment rules as for scalar instructions (Tuple 1).
The instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction
will #UD fault if the k0 mask register is specified.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are
ignored.
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a ZMM register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1 or 4 byte displacement
VPGATHERDD (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j]
THEN DEST[i+31:i] := MEM[BASE_ADDR +
SignExtend(VINDEX[i+31:i]) * SCALE + DISP]
k1[j] := 0
ELSE *DEST[i+31:i] := remains unchanged*
; Only merging masking is allowed
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
DEST[MAXVL-1:VL] := 0
VPGATHERDQ (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j]
THEN DEST[i+63:i] :=
MEM[BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP]
k1[j] := 0
ELSE *DEST[i+63:i] := remains unchanged*
; Only merging masking is allowed
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
DEST[MAXVL-1:VL] := 0
VPGATHERDD/VPGATHERDQ—Gather Packed Dword, Packed Qword With Signed Dword Indices
Vol. 2C
5-515
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPGATHERDD __m512i _mm512_i32gather_epi32( __m512i vdx, void * base, int scale);
VPGATHERDD __m512i _mm512_mask_i32gather_epi32(__m512i s, __mmask16 k, __m512i vdx, void * base, int scale);
VPGATHERDD __m256i _mm256_mmask_i32gather_epi32(__m256i s, __mmask8 k, __m256i vdx, void * base, int scale);
VPGATHERDD __m128i _mm_mmask_i32gather_epi32(__m128i s, __mmask8 k, __m128i vdx, void * base, int scale);
VPGATHERDQ __m512i _mm512_i32logather_epi64( __m256i vdx, void * base, int scale);
VPGATHERDQ __m512i _mm512_mask_i32logather_epi64(__m512i s, __mmask8 k, __m256i vdx, void * base, int scale);
VPGATHERDQ __m256i _mm256_mmask_i32logather_epi64(__m256i s, __mmask8 k, __m128i vdx, void * base, int scale);
VPGATHERDQ __m128i _mm_mmask_i32gather_epi64(__m128i s, __mmask8 k, __m128i vdx, void * base, int scale);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-61, “Type E12 Class Exception Conditions.”
5-516
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VPGATHERDD/VPGATHERDQ—Gather Packed Dword, Packed Qword With Signed Dword Indices
INSTRUCTION SET REFERENCE, V
VPGATHERDQ/VPGATHERQQ—Gather Packed Qword Values Using Signed Dword/Qword Indices
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
-bit
Feature
Mode
Flag
VEX.128.66.0F38.W1 90 /r
A
V/V
AVX2
Using dword indices specified in vm32x, gather qword val-
VPGATHERDQ xmm1, vm32x, xmm2
ues from memory conditioned on mask specified by
xmm2. Conditionally gathered elements are merged into
xmm1.
VEX.128.66.0F38.W1 91 /r
A
V/V
AVX2
Using qword indices specified in vm64x, gather qword val-
VPGATHERQQ xmm1, vm64x, xmm2
ues from memory conditioned on mask specified by
xmm2. Conditionally gathered elements are merged into
xmm1.
VEX.256.66.0F38.W1 90 /r
A
V/V
AVX2
Using dword indices specified in vm32x, gather qword val-
VPGATHERDQ ymm1, vm32x, ymm2
ues from memory conditioned on mask specified by
ymm2. Conditionally gathered elements are merged into
ymm1.
VEX.256.66.0F38.W1 91 /r
A
V/V
AVX2
Using qword indices specified in vm64y, gather qword val-
VPGATHERQQ ymm1, vm64y, ymm2
ues from memory conditioned on mask specified by
ymm2. Conditionally gathered elements are merged into
ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
A
ModRM:reg (r,w)
BaseReg (R): VSIB:base,
VEX.vvvv (r, w)
N/A
VectorReg(R): VSIB:index
Description
The instruction conditionally loads up to 2 or 4 qword values from memory addresses specified by the memory
operand (the second operand) and using qword indices. The memory operand uses the VSIB form of the SIB byte
to specify a general purpose register operand as the common base, a vector register for an array of indices relative
to the base and a constant scale factor.
The mask operand (the third operand) specifies the conditional load operation from each memory address and the
corresponding update of each data element of the destination operand (the first operand). Conditionality is speci-
fied by the most significant bit of each data element of the mask register. If an element’s mask bit is not set, the
corresponding element of the destination register is left unchanged. The width of data element in the destination
register and mask register are identical. The entire mask register will be set to zero by this instruction unless the
instruction causes an exception.
Using dword indices in the lower half of the mask register, the instruction conditionally loads up to 2 or 4 qword
values from the VSIB addressing memory operand, and updates the destination register.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask operand are partially updated; those elements that have been gathered are placed into the
destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gath-
ered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
If the data size and index size are different, part of the destination register and part of the mask register do not
correspond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both
of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception
before gathering any elements.
VEX.128 version: The instruction will gather two qword values. For dword indices, only the lower two indices in the
vector index register are used.
VEX.256 version: The instruction will gather four qword values. For dword indices, only the lower four indices in the
vector index register are used.
VPGATHERDQ/VPGATHERQQ—Gather Packed Qword Values Using Signed Dword/Qword Indices
Vol. 2C
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INSTRUCTION SET REFERENCE, V
Note that:
• If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault.
• The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
64 memory-ordering model.
• Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer
to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the
conventional order.
• Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
• This instruction does not perform AC checks, and so will never deliver an AC fault.
• This instruction will cause a #UD if the address size attribute is 16-bit.
• This instruction will cause a #UD if the memory operand is encoded without the SIB byte.
• This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does
is implementation specific, and some implementations may use loads larger than the data element size or load
elements an indeterminate number of times.
• The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-
bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address
bits are ignored.
Operation
DEST := SRC1;
BASE_ADDR: base register encoded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;
SCALE: scale factor encoded by SIB:[7:6];
DISP: optional 1, 4 byte displacement;
MASK := SRC3;
VPGATHERDQ (VEX.128 version)
MASK[MAXVL-1:128] := 0;
FOR j := 0 to 1
i := j * 64;
IF MASK[63+i] THEN
MASK[i +63:i] := FFFFFFFF_FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +63:i] := 0;
FI;
ENDFOR
FOR j := 0 to 1
k := j * 32;
i := j * 64;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX[k+31:k])*SCALE + DISP);
IF MASK[63+i] THEN
DEST[i +63:i] := FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +63:i] := 0;
ENDFOR
DEST[MAXVL-1:128] := 0;
VPGATHERQQ (VEX.128 version)
MASK[MAXVL-1:128] := 0;
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VPGATHERDQ/VPGATHERQQ—Gather Packed Qword Values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V
FOR j := 0 to 1
i := j * 64;
IF MASK[63+i] THEN
MASK[i +63:i] := FFFFFFFF_FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +63:i] := 0;
FI;
ENDFOR
FOR j := 0 to 1
i := j * 64;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP);
IF MASK[63+i] THEN
DEST[i +63:i] := FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +63:i] := 0;
ENDFOR
DEST[MAXVL-1:128] := 0;
VPGATHERQQ (VEX.256 version)
MASK[MAXVL-1:256] := 0;
FOR j := 0 to 3
i := j * 64;
IF MASK[63+i] THEN
MASK[i +63:i] := FFFFFFFF_FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +63:i] := 0;
FI;
ENDFOR
FOR j := 0 to 3
i := j * 64;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP);
IF MASK[63+i] THEN
DEST[i +63:i] := FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +63:i] := 0;
ENDFOR
DEST[MAXVL-1:256] := 0;
VPGATHERDQ (VEX.256 version)
MASK[MAXVL-1:256] := 0;
FOR j := 0 to 3
i := j * 64;
IF MASK[63+i] THEN
MASK[i +63:i] := FFFFFFFF_FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +63:i] := 0;
FI;
ENDFOR
FOR j := 0 to 3
k := j * 32;
i := j * 64;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[k+31:k])*SCALE + DISP);
IF MASK[63+i] THEN
DEST[i +63:i] := FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
VPGATHERDQ/VPGATHERQQ—Gather Packed Qword Values Using Signed Dword/Qword Indices
Vol. 2C
5-519
INSTRUCTION SET REFERENCE, V
FI;
MASK[i +63:i] := 0;
ENDFOR
DEST[MAXVL-1:256] := 0;
Intel C/C++ Compiler Intrinsic Equivalent
VPGATHERDQ: __m128i _mm_i32gather_epi64 (__int64 const * base, __m128i index, const int scale);
VPGATHERDQ: __m128i _mm_mask_i32gather_epi64 (__m128i src, __int64 const * base, __m128i index, __m128i mask, const int
scale);
VPGATHERDQ: __m256i _mm256_i32gather_epi64 (__int64 const * base, __m128i index, const int scale);
VPGATHERDQ: __m256i _mm256_mask_i32gather_epi64 (__m256i src, __int64 const * base, __m128i index, __m256i mask, const
int scale);
VPGATHERQQ: __m128i _mm_i64gather_epi64 (__int64 const * base, __m128i index, const int scale);
VPGATHERQQ: __m128i _mm_mask_i64gather_epi64 (__m128i src, __int64 const * base, __m128i index, __m128i mask, const int
scale);
VPGATHERQQ: __m256i _mm256_i64gather_epi64 __(int64 const * base, __m256i index, const int scale);
VPGATHERQQ: __m256i _mm256_mask_i64gather_epi64 (__m256i src, __int64 const * base, __m256i index, __m256i mask, const
int scale);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-27, “Type 12 Class Exception Conditions.”
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VPGATHERDQ/VPGATHERQQ—Gather Packed Qword Values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V
VPGATHERQD/VPGATHERQQ—Gather Packed Dword, Packed Qword with Signed Qword Indices
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W0 91 /vsib
A
V/V
AVX512VL
Using signed qword indices, gather dword values from
VPGATHERQD xmm1 {k1}, vm64x
AVX512F
memory using writemask k1 for merging-masking.
EVEX.256.66.0F38.W0 91 /vsib
A
V/V
AVX512VL
Using signed qword indices, gather dword values from
VPGATHERQD xmm1 {k1}, vm64y
AVX512F
memory using writemask k1 for merging-masking.
EVEX.512.66.0F38.W0 91 /vsib
A
V/V
AVX512F
Using signed qword indices, gather dword values from
VPGATHERQD ymm1 {k1}, vm64z
memory using writemask k1 for merging-masking.
EVEX.128.66.0F38.W1 91 /vsib
A
V/V
AVX512VL
Using signed qword indices, gather quadword values from
VPGATHERQQ xmm1 {k1}, vm64x
AVX512F
memory using writemask k1 for merging-masking.
EVEX.256.66.0F38.W1 91 /vsib
A
V/V
AVX512VL
Using signed qword indices, gather quadword values from
VPGATHERQQ ymm1 {k1}, vm64y
AVX512F
memory using writemask k1 for merging-masking.
EVEX.512.66.0F38.W1 91 /vsib
A
V/V
AVX512F
Using signed qword indices, gather quadword values from
VPGATHERQQ zmm1 {k1}, vm64z
memory using writemask k1 for merging-masking.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
BaseReg (R): VSIB:base,
A
Tuple1 Scalar
ModRM:reg (w)
N/A
N/A
VectorReg(R): VSIB:index
Description
A set of 8 doubleword/quadword memory locations pointed to by base address BASE_ADDR and index vector
VINDEX with scale SCALE are gathered. The result is written into a vector register. The elements are specified via
the VSIB (i.e., the index register is a vector register, holding packed indices). Elements will only be loaded if their
corresponding mask bit is one. If an element’s mask bit is not set, the corresponding element of the destination
register is left unchanged. The entire mask register will be set to zero by this instruction unless it triggers an excep-
tion.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask register (k1) are partially updated; those elements that have been gathered are placed into
the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already
gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruc-
tion breakpoint is not re-triggered when the instruction is continued.
If the data element size is less than the index element size, the higher part of the destination register and the mask
register do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may
update these unused elements to one or both of those registers even if the instruction triggers an exception, and
even if the instruction triggers the exception before gathering any elements.
Note that:
• The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
64 memory-ordering model.
• Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements
closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
in the conventional order.
• Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
VPGATHERQD/VPGATHERQQ—Gather Packed Dword, Packed Qword with Signed Qword Indices
Vol. 2C
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INSTRUCTION SET REFERENCE, V
• This instruction does not perform AC checks, and so will never deliver an AC fault.
• Not valid with 16-bit effective addresses. Will deliver a #UD fault.
• These instructions do not accept zeroing-masking since the 0 values in k1 are used to determine completion.
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has the same disp8*N and alignment rules as for scalar instructions (Tuple 1).
The instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction
will #UD fault if the k0 mask register is specified.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are
ignored.
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a ZMM register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1 or 4 byte displacement
VPGATHERQD (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
k := j * 64
IF k1[j]
THEN DEST[i+31:i] := MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP]
k1[j] := 0
ELSE *DEST[i+31:i] := remains unchanged*
; Only merging masking is allowed
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
DEST[MAXVL-1:VL/2] := 0
VPGATHERQQ (EVEX encoded version)
(KL, VL) = (2, 64), (4, 128), (8, 256)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j]
THEN DEST[i+63:i] :=
MEM[BASE_ADDR + (VINDEX[i+63:i]) * SCALE + DISP]
k1[j] := 0
ELSE *DEST[i+63:i] := remains unchanged*
; Only merging masking is allowed
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
DEST[MAXVL-1:VL] := 0
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VPGATHERQD/VPGATHERQQ—Gather Packed Dword, Packed Qword with Signed Qword Indices
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPGATHERQD __m256i _mm512_i64gather_epi32(__m512i vdx, void * base, int scale);
VPGATHERQD __m256i _mm512_mask_i64gather_epi32lo(__m256i s, __mmask8 k, __m512i vdx, void * base, int scale);
VPGATHERQD __m128i _mm256_mask_i64gather_epi32lo(__m128i s, __mmask8 k, __m256i vdx, void * base, int scale);
VPGATHERQD __m128i _mm_mask_i64gather_epi32(__m128i s, __mmask8 k, __m128i vdx, void * base, int scale);
VPGATHERQQ __m512i _mm512_i64gather_epi64( __m512i vdx, void * base, int scale);
VPGATHERQQ __m512i _mm512_mask_i64gather_epi64(__m512i s, __mmask8 k, __m512i vdx, void * base, int scale);
VPGATHERQQ __m256i _mm256_mask_i64gather_epi64(__m256i s, __mmask8 k, __m256i vdx, void * base, int scale);
VPGATHERQQ __m128i _mm_mask_i64gather_epi64(__m128i s, __mmask8 k, __m128i vdx, void * base, int scale);
SIMD Floating-Point Exceptions
None.
Other Exceptions
See Table 2-61, “Type E12 Class Exception Conditions.”
VPGATHERQD/VPGATHERQQ—Gather Packed Dword, Packed Qword with Signed Qword Indices
Vol. 2C
5-523
INSTRUCTION SET REFERENCE, V
VPLZCNTD/Q—Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W0 44 /r
A
V/V
AVX512VL
Count the number of leading zero bits in each dword
VPLZCNTD xmm1 {k1}{z},
AVX512CD
element of xmm2/m128/m32bcst using writemask k1.
xmm2/m128/m32bcst
EVEX.256.66.0F38.W0 44 /r
A
V/V
AVX512VL
Count the number of leading zero bits in each dword
VPLZCNTD ymm1 {k1}{z},
AVX512CD
element of ymm2/m256/m32bcst using writemask k1.
ymm2/m256/m32bcst
EVEX.512.66.0F38.W0 44 /r
A
V/V
AVX512CD
Count the number of leading zero bits in each dword
VPLZCNTD zmm1 {k1}{z},
element of zmm2/m512/m32bcst using writemask k1.
zmm2/m512/m32bcst
EVEX.128.66.0F38.W1 44 /r
A
V/V
AVX512VL
Count the number of leading zero bits in each qword
VPLZCNTQ xmm1 {k1}{z},
AVX512CD
element of xmm2/m128/m64bcst using writemask k1.
xmm2/m128/m64bcst
EVEX.256.66.0F38.W1 44 /r
A
V/V
AVX512VL
Count the number of leading zero bits in each qword
VPLZCNTQ ymm1 {k1}{z},
AVX512CD
element of ymm2/m256/m64bcst using writemask k1.
ymm2/m256/m64bcst
EVEX.512.66.0F38.W1 44 /r
A
V/V
AVX512CD
Count the number of leading zero bits in each qword
VPLZCNTQ zmm1 {k1}{z},
element of zmm2/m512/m64bcst using writemask k1.
zmm2/m512/m64bcst
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Counts the number of leading most significant zero bits in each dword or qword element of the source operand (the
second operand) and stores the results in the destination register (the first operand) according to the writemask.
If an element is zero, the result for that element is the operand size of the element.
EVEX.512 encoded version: The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a ZMM register, conditionally updated
using writemask k1.
EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a YMM register, conditionally updated
using writemask k1.
EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a XMM register, conditionally updated
using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
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VPLZCNTD/Q—Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values
INSTRUCTION SET REFERENCE, V
Operation
VPLZCNTD
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j*32
IF MaskBit(j) OR *no writemask*
THEN
temp := 32
DEST[i+31:i] := 0
WHILE (temp > 0) AND (SRC[i+temp-1] = 0)
DO
temp := temp - 1
DEST[i+31:i] := DEST[i+31:i] + 1
OD
ELSE
IF *merging-masking*
THEN *DEST[i+31:i] remains unchanged*
ELSE DEST[i+31:i] := 0
FI
FI
ENDFOR
DEST[MAXVL-1:VL] := 0
VPLZCNTQ
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j*64
IF MaskBit(j) OR *no writemask*
THEN
temp := 64
DEST[i+63:i] := 0
WHILE (temp > 0) AND (SRC[i+temp-1] = 0)
DO
temp := temp - 1
DEST[i+63:i] := DEST[i+63:i] + 1
OD
ELSE
IF *merging-masking*
THEN *DEST[i+63:i] remains unchanged*
ELSE DEST[i+63:i] := 0
FI
FI
ENDFOR
DEST[MAXVL-1:VL] := 0
VPLZCNTD/Q—Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values
Vol. 2C
5-525
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VPLZCNTD __m512i _mm512_lzcnt_epi32(__m512i a);
VPLZCNTD __m512i _mm512_mask_lzcnt_epi32(__m512i s, __mmask16 m, __m512i a);
VPLZCNTD __m512i _mm512_maskz_lzcnt_epi32( __mmask16 m, __m512i a);
VPLZCNTQ __m512i _mm512_lzcnt_epi64(__m512i a);
VPLZCNTQ __m512i _mm512_mask_lzcnt_epi64(__m512i s, __mmask8 m, __m512i a);
VPLZCNTQ __m512i _mm512_maskz_lzcnt_epi64(__mmask8 m, __m512i a);
VPLZCNTD __m256i _mm256_lzcnt_epi32(__m256i a);
VPLZCNTD __m256i _mm256_mask_lzcnt_epi32(__m256i s, __mmask8 m, __m256i a);
VPLZCNTD __m256i _mm256_maskz_lzcnt_epi32( __mmask8 m, __m256i a);
VPLZCNTQ __m256i _mm256_lzcnt_epi64(__m256i a);
VPLZCNTQ __m256i _mm256_mask_lzcnt_epi64(__m256i s, __mmask8 m, __m256i a);
VPLZCNTQ __m256i _mm256_maskz_lzcnt_epi64(__mmask8 m, __m256i a);
VPLZCNTD __m128i _mm_lzcnt_epi32(__m128i a);
VPLZCNTD __m128i _mm_mask_lzcnt_epi32(__m128i s, __mmask8 m, __m128i a);
VPLZCNTD __m128i _mm_maskz_lzcnt_epi32( __mmask8 m, __m128i a);
VPLZCNTQ __m128i _mm_lzcnt_epi64(__m128i a);
VPLZCNTQ __m128i _mm_mask_lzcnt_epi64(__m128i s, __mmask8 m, __m128i a);
VPLZCNTQ __m128i _mm_maskz_lzcnt_epi64(__mmask8 m, __m128i a);
SIMD Floating-Point Exceptions
None.
Other Exceptions
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions.”
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VPLZCNTD/Q—Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values