Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

INSTRUCTION SET REFERENCE, V

VFCMULCSH/VFMULCSH—Complex Multiply Scalar FP16 Values

Opcode/

Op/

64/32

CPUID Feature

Description

Instruction

bit Mode

Flag

Support

EVEX.LLIG.F2.MAP6.W0 D7 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFCMULCSH xmm1{k1}{z}, xmm2,

xmm2 and xmm3/m32, and store the result in

xmm3/m32 {er}

xmm1 subject to writemask k1. Bits 127:32 of

xmm2 are copied to xmm1[127:32].

EVEX.LLIG.F3.MAP6.W0 D7 /r

V/V

AVX512-FP16

Complex multiply a pair of FP16 values from

VFMULCSH xmm1{k1}{z}, xmm2,

xmm2 and the complex conjugate of xmm3/m32,

xmm3/m32 {er}

and store the result in xmm1 subject to

writemask k1. Bits 127:32 of xmm2 are copied to

xmm1[127:32].

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

Scalar

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

This instruction performs a complex multiply operation. There are normal and complex conjugate forms of the oper-

ation. The masking for this operation is done on 32-bit quantities representing a pair of FP16 values.

Bits 127:32 of the destination operand are copied from the corresponding bits of the first source operand. Bits

MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according

to the writemask.

Rounding is performed at every FMA (fused multiply and add) boundary. Execution occurs as if all MXCSR excep-

tions are masked. MXCSR status bits are updated to reflect exceptional conditions.

Operation

VFMULCSH dest{k1}, src1, src2 (AVX512)

KL := VL / 32

IF k1[0] or *no writemask*:

// non-conjugate version subtracts last even term

tmp.fp16[0] := src1.fp16[0] * src2.fp16[0]

tmp.fp16[1] := src1.fp16[1] * src2.fp16[0]

dest.fp16[0] := tmp.fp16[0] - src1.fp16[1] * src2.fp16[1]

dest.fp16[1] := tmp.fp16[1] + src1.fp16[0] * src2.fp16[1]

ELSE IF *zeroing*:

dest.fp16[0] := 0

dest.fp16[1] := 0

DEST[127:32] := src1[127:32] // copy upper part of src1

DEST[MAXVL-1:128] := 0

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INSTRUCTION SET REFERENCE, V

VFCMULCSH dest{k1}, src1, src2 (AVX512)

KL := VL / 32

IF k1[0] or *no writemask*:

tmp.fp16[0] := src1.fp16[0] * src2.fp16[0]

tmp.fp16[1] := src1.fp16[1] * src2.fp16[0]

// conjugate version subtracts odd final term

dest.fp16[0] := tmp.fp16[0] + src1.fp16[1] * src2.fp16[1]

dest.fp16[1] := tmp.fp16[1] - src1.fp16[0] * src2.fp16[1]

ELSE IF *zeroing*:

dest.fp16[0] := 0

dest.fp16[1] := 0

DEST[127:32] := src1[127:32] // copy upper part of src1

DEST[MAXVL-1:128] := 0

Intel C/C++ Compiler Intrinsic Equivalent

VFCMULCSH __m128h _mm_cmul_round_sch (__m128h a, __m128h b, const int rounding);

VFCMULCSH __m128h _mm_mask_cmul_round_sch (__m128h src, __mmask8 k, __m128h a, __m128h b, const int rounding);

VFCMULCSH __m128h _mm_maskz_cmul_round_sch (__mmask8 k, __m128h a, __m128h b, const int rounding);

VFCMULCSH __m128h _mm_cmul_sch (__m128h a, __m128h b);

VFCMULCSH __m128h _mm_mask_cmul_sch (__m128h src, __mmask8 k, __m128h a, __m128h b);

VFCMULCSH __m128h _mm_maskz_cmul_sch (__mmask8 k, __m128h a, __m128h b);

VFCMULCSH __m128h _mm_fcmul_round_sch (__m128h a, __m128h b, const int rounding);

VFCMULCSH __m128h _mm_mask_fcmul_round_sch (__m128h src, __mmask8 k, __m128h a, __m128h b, const int rounding);

VFCMULCSH __m128h _mm_maskz_fcmul_round_sch (__mmask8 k, __m128h a, __m128h b, const int rounding);

VFCMULCSH __m128h _mm_fcmul_sch (__m128h a, __m128h b);

VFCMULCSH __m128h _mm_mask_fcmul_sch (__m128h src, __mmask8 k, __m128h a, __m128h b);

VFCMULCSH __m128h _mm_maskz_fcmul_sch (__mmask8 k, __m128h a, __m128h b);

VFMULCSH __m128h _mm_fmul_round_sch (__m128h a, __m128h b, const int rounding);

VFMULCSH __m128h _mm_mask_fmul_round_sch (__m128h src, __mmask8 k, __m128h a, __m128h b, const int rounding);

VFMULCSH __m128h _mm_maskz_fmul_round_sch (__mmask8 k, __m128h a, __m128h b, const int rounding);

VFMULCSH __m128h _mm_fmul_sch (__m128h a, __m128h b);

VFMULCSH __m128h _mm_mask_fmul_sch (__m128h src, __mmask8 k, __m128h a, __m128h b);

VFMULCSH __m128h _mm_maskz_fmul_sch (__mmask8 k, __m128h a, __m128h b);

VFMULCSH __m128h _mm_mask_mul_round_sch (__m128h src, __mmask8 k, __m128h a, __m128h b, const int rounding);

VFMULCSH __m128h _mm_maskz_mul_round_sch (__mmask8 k, __m128h a, __m128h b, const int rounding);

VFMULCSH __m128h _mm_mul_round_sch (__m128h a, __m128h b, const int rounding);

VFMULCSH __m128h _mm_mask_mul_sch (__m128h src, __mmask8 k, __m128h a, __m128h b);

VFMULCSH __m128h _mm_maskz_mul_sch (__mmask8 k, __m128h a, __m128h b);

VFMULCSH __m128h _mm_mul_sch (__m128h a, __m128h b);

SIMD Floating-Point Exceptions

Invalid, Underflow, Overflow, Precision, Denormal

Other Exceptions

EVEX-encoded instructions, see Table 2-58, “Type E10 Class Exception Conditions.”

Additionally:

#UD

If (dest_reg == src1_reg) or (dest_reg == src2_reg).

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VFCMULCSH/VFMULCSH—Complex Multiply Scalar FP16 Values

INSTRUCTION SET REFERENCE, V

VFIXUPIMMPD—Fix Up Special Packed Float64 Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.128.66.0F3A.W1 54 /r ib

V/V

AVX512VL

Fix up special numbers in float64 vector xmm1, float64

VFIXUPIMMPD xmm1 {k1}{z}, xmm2,

AVX512F

vector xmm2 and int64 vector xmm3/m128/m64bcst

xmm3/m128/m64bcst, imm8

and store the result in xmm1, under writemask.

EVEX.256.66.0F3A.W1 54 /r ib

V/V

AVX512VL

Fix up special numbers in float64 vector ymm1, float64

VFIXUPIMMPD ymm1 {k1}{z}, ymm2,

AVX512F

vector ymm2 and int64 vector ymm3/m256/m64bcst

ymm3/m256/m64bcst, imm8

and store the result in ymm1, under writemask.

EVEX.512.66.0F3A.W1 54 /r ib

V/V

AVX512F

Fix up elements of float64 vector in zmm2 using int64

VFIXUPIMMPD zmm1 {k1}{z}, zmm2,

vector table in zmm3/m512/m64bcst, combine with

zmm3/m512/m64bcst{sae}, imm8

preserved elements from zmm1, and store the result in

zmm1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Full

ModRM:reg (r, w)

EVEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

Perform fix-up of quad-word elements encoded in double precision floating-point format in the first source operand

(the second operand) using a 32-bit, two-level look-up table specified in the corresponding quadword element of

the second source operand (the third operand) with exception reporting specifier imm8. The elements that are

fixed-up are selected by mask bits of 1 specified in the opmask k1. Mask bits of 0 in the opmask k1 or table

response action of 0000b preserves the corresponding element of the first operand. The fixed-up elements from

the first source operand and the preserved element in the first operand are combined as the final results in the

destination operand (the first operand).

The destination and the first source operands are ZMM/YMM/XMM registers. The second source operand can be a

ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-

bit memory location.

The two-level look-up table perform a fix-up of each double precision floating-point input data in the first source

operand by decoding the input data encoding into 8 token types. A response table is defined for each token type

that converts the input encoding in the first source operand with one of 16 response actions.

This instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one source

so that they match the spec, although it is generally useful for fixing up the results of multiple-instruction

sequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF

according to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incor-

rect result. To deal with this, VFIXUPIMMPD can be used after the N-R reciprocal sequence to set the result to the

correct value (i.e., INF when the input is 0).

If MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and

do not trigger any fixup nor fault reporting.

Imm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below).

MXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8

bits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.

This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1

are computed and stored into zmm1. Elements in the destination with the corresponding bit clear in k1 retain their

previous values or are set to 0.

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INSTRUCTION SET REFERENCE, V

Operation

enum TOKEN_TYPE

{

QNAN_TOKEN := 0,

SNAN_TOKEN := 1,

ZERO_VALUE_TOKEN := 2,

POS_ONE_VALUE_TOKEN := 3,

NEG_INF_TOKEN := 4,

POS_INF_TOKEN := 5,

NEG_VALUE_TOKEN := 6,

POS_VALUE_TOKEN := 7

}

FIXUPIMM_DP (dest[63:0], src1[63:0],tbl3[63:0], imm8 [7:0]){

tsrc[63:0] := ((src1[62:52] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[63:0]

CASE(tsrc[63:0] of TOKEN_TYPE) {

QNAN_TOKEN: j := 0;

SNAN_TOKEN: j := 1;

ZERO_VALUE_TOKEN: j := 2;

POS_ONE_VALUE_TOKEN: j := 3;

NEG_INF_TOKEN: j := 4;

POS_INF_TOKEN: j := 5;

NEG_VALUE_TOKEN: j := 6;

POS_VALUE_TOKEN: j := 7;

}

; end source special CASE(tsrc…)

; The required response from src3 table is extracted

token_response[3:0] = tbl3[3+4*j:4*j];

CASE(token_response[3:0]) {

0000: dest[63:0] := dest[63:0];

; preserve content of DEST

0001: dest[63:0] := tsrc[63:0];

; pass through src1 normal input value, denormal as zero

0010: dest[63:0] := QNaN(tsrc[63:0]);

0011: dest[63:0] := QNAN_Indefinite;

0100: dest[63:0] := -INF;

0101: dest[63:0] := +INF;

0110: dest[63:0] := tsrc.sign? -INF : +INF;

0111: dest[63:0] := -0;

1000: dest[63:0] := +0;

1001: dest[63:0] := -1;

1010: dest[63:0] := +1;

1011: dest[63:0] := ½;

1100: dest[63:0] := 90.0;

1101: dest[63:0] := PI/2;

1110: dest[63:0] := MAX_FLOAT;

1111: dest[63:0] := -MAX_FLOAT;

}

; end of token_response CASE

; The required fault reporting from imm8 is extracted

; TOKENs are mutually exclusive and TOKENs priority defines the order.

; Multiple faults related to a single token can occur simultaneously.

IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE;

IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;

IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE;

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INSTRUCTION SET REFERENCE, V

IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE;

IF (tsrc[63:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;

IF (tsrc[63:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;

IF (tsrc[63:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE;

IF (tsrc[63:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;

; end fault reporting

return dest[63:0];

}

; end of FIXUPIMM_DP()

VFIXUPIMMPD

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN

DEST[i+63:i] := FIXUPIMM_DP(DEST[i+63:i], SRC1[i+63:i], SRC2[63:0], imm8 [7:0])

ELSE

DEST[i+63:i] := FIXUPIMM_DP(DEST[i+63:i], SRC1[i+63:i], SRC2[i+63:i], imm8 [7:0])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE DEST[i+63:i] := 0

; zeroing-masking

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

Immediate Control Description:

+ INF ˘

#IE

- VE ˘

#IE

- INF ˘

#IE

SNaN ˘

#IE

ONE ˘

#IE

ONE ˘

#ZE

ZERO ˘

#IE

ZERO ˘

#ZE

Figure 5-9. VFIXUPIMMPD Immediate Control Description

VFIXUPIMMPD—Fix Up Special Packed Float64 Values

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INSTRUCTION SET REFERENCE, V

Intel C/C++ Compiler Intrinsic Equivalent

VFIXUPIMMPD __m512d _mm512_fixupimm_pd( __m512d a, __m512i tbl, int imm);

VFIXUPIMMPD __m512d _mm512_mask_fixupimm_pd(__m512d s, __mmask8 k, __m512d a, __m512i tbl, int imm);

VFIXUPIMMPD __m512d _mm512_maskz_fixupimm_pd( __mmask8 k, __m512d a, __m512i tbl, int imm);

VFIXUPIMMPD __m512d _mm512_fixupimm_round_pd( __m512d a, __m512i tbl, int imm, int sae);

VFIXUPIMMPD __m512d _mm512_mask_fixupimm_round_pd(__m512d s, __mmask8 k, __m512d a, __m512i tbl, int imm, int sae);

VFIXUPIMMPD __m512d _mm512_maskz_fixupimm_round_pd( __mmask8 k, __m512d a, __m512i tbl, int imm, int sae);

VFIXUPIMMPD __m256d _mm256_fixupimm_pd( __m256d a, m256d b, __m256i c, int imm8);

VFIXUPIMMPD __m256d _mm256_mask_fixupimm_pd(__m256d a, __mmask8 k, __m256d b, __m256i c, int imm8);

VFIXUPIMMPD __m256d _mm256_maskz_fixupimm_pd( __mmask8 k, __m256d a, __m256d b, __m256i c, int imm8);

VFIXUPIMMPD __m128d _mm_fixupimm_pd( __m128d a, __m128d b, __m128i c, int imm8);

VFIXUPIMMPD __m128d _mm_mask_fixupimm_pd(__m128d a, __mmask8 k, __m128d b, __m128i c, int imm8);

VFIXUPIMMPD __m128d _mm_maskz_fixupimm_pd( __mmask8 k, __m128d a, __m128d b, 128ic, int imm8);

SIMD Floating-Point Exceptions

Zero, Invalid

Other Exceptions

See Table 2-46, “Type E2 Class Exception Conditions.”

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INSTRUCTION SET REFERENCE, V

VFIXUPIMMPS—Fix Up Special Packed Float32 Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.128.66.0F3A.W0 54 /r

V/V

AVX512VL

Fix up special numbers in float32 vector xmm1, float32

VFIXUPIMMPS xmm1 {k1}{z}, xmm2,

AVX512F

vector xmm2 and int32 vector xmm3/m128/m32bcst

xmm3/m128/m32bcst, imm8

and store the result in xmm1, under writemask.

EVEX.256.66.0F3A.W0 54 /r

V/V

AVX512VL

Fix up special numbers in float32 vector ymm1, float32

VFIXUPIMMPS ymm1 {k1}{z}, ymm2,

AVX512F

vector ymm2 and int32 vector ymm3/m256/m32bcst

ymm3/m256/m32bcst, imm8

and store the result in ymm1, under writemask.

EVEX.512.66.0F3A.W0 54 /r ib

V/V

AVX512F

Fix up elements of float32 vector in zmm2 using int32

VFIXUPIMMPS zmm1 {k1}{z}, zmm2,

vector table in zmm3/m512/m32bcst, combine with

zmm3/m512/m32bcst{sae}, imm8

preserved elements from zmm1, and store the result in

zmm1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Full

ModRM:reg (r, w)

EVEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

Perform fix-up of doubleword elements encoded in single precision floating-point format in the first source operand

(the second operand) using a 32-bit, two-level look-up table specified in the corresponding doubleword element of

the second source operand (the third operand) with exception reporting specifier imm8. The elements that are

fixed-up are selected by mask bits of 1 specified in the opmask k1. Mask bits of 0 in the opmask k1 or table

response action of 0000b preserves the corresponding element of the first operand. The fixed-up elements from

the first source operand and the preserved element in the first operand are combined as the final results in the

destination operand (the first operand).

The destination and the first source operands are ZMM/YMM/XMM registers. The second source operand can be a

ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-

bit memory location.

The two-level look-up table perform a fix-up of each single precision floating-point input data in the first source

operand by decoding the input data encoding into 8 token types. A response table is defined for each token type

that converts the input encoding in the first source operand with one of 16 response actions.

This instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one source

so that they match the spec, although it is generally useful for fixing up the results of multiple-instruction

sequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF

according to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incor-

rect result. To deal with this, VFIXUPIMMPS can be used after the N-R reciprocal sequence to set the result to the

correct value (i.e., INF when the input is 0).

If MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and

do not trigger any fixup nor fault reporting.

Imm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below).

MXCSR.DAZ is used and refer to zmm2 only (i.e., zmm1 is not considered as zero in case MXCSR.DAZ is set).

MXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8

bits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.

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INSTRUCTION SET REFERENCE, V

Operation

enum TOKEN_TYPE

{

QNAN_TOKEN := 0,

SNAN_TOKEN := 1,

ZERO_VALUE_TOKEN := 2,

POS_ONE_VALUE_TOKEN := 3,

NEG_INF_TOKEN := 4,

POS_INF_TOKEN := 5,

NEG_VALUE_TOKEN := 6,

POS_VALUE_TOKEN := 7

}

FIXUPIMM_SP ( dest[31:0], src1[31:0],tbl3[31:0], imm8 [7:0]){

tsrc[31:0] := ((src1[30:23] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[31:0]

CASE(tsrc[31:0] of TOKEN_TYPE) {

QNAN_TOKEN: j := 0;

SNAN_TOKEN: j := 1;

ZERO_VALUE_TOKEN: j := 2;

POS_ONE_VALUE_TOKEN: j := 3;

NEG_INF_TOKEN: j := 4;

POS_INF_TOKEN: j := 5;

NEG_VALUE_TOKEN: j := 6;

POS_VALUE_TOKEN: j := 7;

}

; end source special CASE(tsrc…)

; The required response from src3 table is extracted

token_response[3:0] = tbl3[3+4*j:4*j];

CASE(token_response[3:0]) {

0000: dest[31:0] := dest[31:0];

; preserve content of DEST

0001: dest[31:0] := tsrc[31:0];

; pass through src1 normal input value, denormal as zero

0010: dest[31:0] := QNaN(tsrc[31:0]);

0011: dest[31:0] := QNAN_Indefinite;

0100: dest[31:0] := -INF;

0101: dest[31:0] := +INF;

0110: dest[31:0] := tsrc.sign? -INF : +INF;

0111: dest[31:0] := -0;

1000: dest[31:0] := +0;

1001: dest[31:0] := -1;

1010: dest[31:0] := +1;

1011: dest[31:0] := ½;

1100: dest[31:0] := 90.0;

1101: dest[31:0] := PI/2;

1110: dest[31:0] := MAX_FLOAT;

1111: dest[31:0] := -MAX_FLOAT;

}

; end of token_response CASE

; The required fault reporting from imm8 is extracted

; TOKENs are mutually exclusive and TOKENs priority defines the order.

; Multiple faults related to a single token can occur simultaneously.

IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE;

IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;

IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE;

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VFIXUPIMMPS—Fix Up Special Packed Float32 Values

INSTRUCTION SET REFERENCE, V

IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE;

IF (tsrc[31:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;

IF (tsrc[31:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;

IF (tsrc[31:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE;

IF (tsrc[31:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;

; end fault reporting

return dest[31:0];

}

; end of FIXUPIMM_SP()

VFIXUPIMMPS (EVEX)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN

DEST[i+31:i] := FIXUPIMM_SP(DEST[i+31:i], SRC1[i+31:i], SRC2[31:0], imm8 [7:0])

ELSE

DEST[i+31:i] := FIXUPIMM_SP(DEST[i+31:i], SRC1[i+31:i], SRC2[i+31:i], imm8 [7:0])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE DEST[i+31:i] := 0

; zeroing-masking

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

Immediate Control Description:

+ INF ˘

#IE

- VE ˘

#IE

- INF ˘

#IE

SNaN ˘

#IE

ONE ˘

#IE

ONE ˘

#ZE

ZERO ˘

#IE

ZERO ˘

#ZE

Figure 5-10. VFIXUPIMMPS Immediate Control Description

VFIXUPIMMPS—Fix Up Special Packed Float32 Values

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INSTRUCTION SET REFERENCE, V

Intel C/C++ Compiler Intrinsic Equivalent

VFIXUPIMMPS __m512 _mm512_fixupimm_ps( __m512 a, __m512i tbl, int imm);

VFIXUPIMMPS __m512 _mm512_mask_fixupimm_ps(__m512 s, __mmask16 k, __m512 a, __m512i tbl, int imm);

VFIXUPIMMPS __m512 _mm512_maskz_fixupimm_ps( __mmask16 k, __m512 a, __m512i tbl, int imm);

VFIXUPIMMPS __m512 _mm512_fixupimm_round_ps( __m512 a, __m512i tbl, int imm, int sae);

VFIXUPIMMPS __m512 _mm512_mask_fixupimm_round_ps(__m512 s, __mmask16 k, __m512 a, __m512i tbl, int imm, int sae);

VFIXUPIMMPS __m512 _mm512_maskz_fixupimm_round_ps( __mmask16 k, __m512 a, __m512i tbl, int imm, int sae);

VFIXUPIMMPS __m256 _mm256_fixupimm_ps( __m256 a, __m256 b, __m256i c, int imm8);

VFIXUPIMMPS __m256 _mm256_mask_fixupimm_ps(__m256 a, __mmask8 k, __m256 b, __m256i c, int imm8);

VFIXUPIMMPS __m256 _mm256_maskz_fixupimm_ps( __mmask8 k, __m256 a, __m256b, __m256i c, int imm8);

VFIXUPIMMPS __m128 _mm_fixupimm_ps( __m128 a, __m128 b, 128i c, int imm8);

VFIXUPIMMPS __m128 _mm_mask_fixupimm_ps(__m128 a, __mmask8 k, __m128 b, __m128i c, int imm8);

VFIXUPIMMPS __m128 _mm_maskz_fixupimm_ps( __mmask8 k, __m128 a, __m128 b, __m128i c, int imm8);

SIMD Floating-Point Exceptions

Zero, Invalid

Other Exceptions

See Table 2-46, “Type E2 Class Exception Conditions.”

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VFIXUPIMMPS—Fix Up Special Packed Float32 Values

INSTRUCTION SET REFERENCE, V

VFIXUPIMMSD—Fix Up Special Scalar Float64 Value

Opcode/

Op /

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

EVEX.LLIG.66.0F3A.W1 55 /r ib

V/V

AVX512F

Fix up a float64 number in the low quadword element of

VFIXUPIMMSD xmm1 {k1}{z},

xmm2 using scalar int32 table in xmm3/m64 and store the

xmm2, xmm3/m64{sae}, imm8

result in xmm1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

Tuple1 Scalar

ModRM:reg (r, w)

EVEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

Perform a fix-up of the low quadword element encoded in double precision floating-point format in the first source

operand (the second operand) using a 32-bit, two-level look-up table specified in the low quadword element of the

second source operand (the third operand) with exception reporting specifier imm8. The element that is fixed-up

is selected by mask bit of 1 specified in the opmask k1. Mask bit of 0 in the opmask k1 or table response action of

0000b preserves the corresponding element of the first operand. The fixed-up element from the first source

operand or the preserved element in the first operand becomes the low quadword element of the destination

operand (the first operand). Bits 127:64 of the destination operand is copied from the corresponding bits of the

first source operand. The destination and first source operands are XMM registers. The second source operand can

be a XMM register or a 64- bit memory location.