Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 94
INSTRUCTION SET REFERENCE, V
VCVTQQ2PD (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[63:0])
ELSE
DEST[i+63:i] :=
Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTQQ2PD __m512d _mm512_cvtepi64_pd( __m512i a);
VCVTQQ2PD __m512d _mm512_mask_cvtepi64_pd( __m512d s, __mmask16 k, __m512i a);
VCVTQQ2PD __m512d _mm512_maskz_cvtepi64_pd( __mmask16 k, __m512i a);
VCVTQQ2PD __m512d _mm512_cvt_roundepi64_pd( __m512i a, int r);
VCVTQQ2PD __m512d _mm512_mask_cvt_roundepi64_pd( __m512d s, __mmask8 k, __m512i a, int r);
VCVTQQ2PD __m512d _mm512_maskz_cvt_roundepi64_pd( __mmask8 k, __m512i a, int r);
VCVTQQ2PD __m256d _mm256_mask_cvtepi64_pd( __m256d s, __mmask8 k, __m256i a);
VCVTQQ2PD __m256d _mm256_maskz_cvtepi64_pd( __mmask8 k, __m256i a);
VCVTQQ2PD __m128d _mm_mask_cvtepi64_pd( __m128d s, __mmask8 k, __m128i a);
VCVTQQ2PD __m128d _mm_maskz_cvtepi64_pd( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTQQ2PD—Convert Packed Quadword Integers to Packed Double Precision Floating-Point Values
Vol. 2C
5-77
INSTRUCTION SET REFERENCE, V
VCVTQQ2PH—Convert Packed Signed Quadword Integers to Packed FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.NP.MAP5.W1 5B /r
A
V/V
AVX512-FP16
Convert two packed signed quadword integers in
VCVTQQ2PH xmm1{k1}{z}, xmm2/
AVX512VL
xmm2/m128/m64bcst to packed FP16 values,
m128/m64bcst
and store the result in xmm1 subject to
writemask k1.
EVEX.256.NP.MAP5.W1 5B /r
A
V/V
AVX512-FP16
Convert four packed signed quadword integers in
VCVTQQ2PH xmm1{k1}{z}, ymm2/
AVX512VL
ymm2/m256/m64bcst to packed FP16 values,
m256/m64bcst
and store the result in xmm1 subject to
writemask k1.
EVEX.512.NP.MAP5.W1 5B /r
A
V/V
AVX512-FP16
Convert eight packed signed quadword integers in
VCVTQQ2PH xmm1{k1}{z}, zmm2/
zmm2/m512/m64bcst to packed FP16 values,
m512/m64bcst {er}
and store the result in xmm1 subject to
writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed signed quadword integers in the source operand to packed FP16 values in the desti-
nation operand. The destination elements are updated according to the writemask.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
If the result of the convert operation is overflow and MXCSR.OM=0 then a SIMD exception will be raised with OE=1,
PE=1.
Operation
VCVTQQ2PH dest, src
VL = 128, 256 or 512
KL := VL / 64
IF *SRC is a register* and (VL = 512) AND (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.qword[0]
ELSE
tsrc := SRC.qword[j]
DEST.fp16[j] := Convert_integer64_to_fp16(tsrc)
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL/4] := 0
5-78
Vol. 2C
VCVTQQ2PH—Convert Packed Signed Quadword Integers to Packed FP16 Values
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VCVTQQ2PH __m128h _mm512_cvt_roundepi64_ph (__m512i a, int rounding);
VCVTQQ2PH __m128h _mm512_mask_cvt_roundepi64_ph (__m128h src, __mmask8 k, __m512i a, int rounding);
VCVTQQ2PH __m128h _mm512_maskz_cvt_roundepi64_ph (__mmask8 k, __m512i a, int rounding);
VCVTQQ2PH __m128h _mm_cvtepi64_ph (__m128i a);
VCVTQQ2PH __m128h _mm_mask_cvtepi64_ph (__m128h src, __mmask8 k, __m128i a);
VCVTQQ2PH __m128h _mm_maskz_cvtepi64_ph (__mmask8 k, __m128i a);
VCVTQQ2PH __m128h _mm256_cvtepi64_ph (__m256i a);
VCVTQQ2PH __m128h _mm256_mask_cvtepi64_ph (__m128h src, __mmask8 k, __m256i a);
VCVTQQ2PH __m128h _mm256_maskz_cvtepi64_ph (__mmask8 k, __m256i a);
VCVTQQ2PH __m128h _mm512_cvtepi64_ph (__m512i a);
VCVTQQ2PH __m128h _mm512_mask_cvtepi64_ph (__m128h src, __mmask8 k, __m512i a);
VCVTQQ2PH __m128h _mm512_maskz_cvtepi64_ph (__mmask8 k, __m512i a);
SIMD Floating-Point Exceptions
Overflow, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
VCVTQQ2PH—Convert Packed Signed Quadword Integers to Packed FP16 Values
Vol. 2C
5-79
INSTRUCTION SET REFERENCE, V
VCVTQQ2PS—Convert Packed Quadword Integers to Packed Single Precision Floating-Point
Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.0F.W1 5B /r
A
V/V
AVX512VL
Convert two packed quadword integers from xmm2/mem to
VCVTQQ2PS xmm1 {k1}{z},
AVX512DQ
packed single precision floating-point values in xmm1 with
xmm2/m128/m64bcst
writemask k1.
EVEX.256.0F.W1 5B /r
A
V/V
AVX512VL
Convert four packed quadword integers from ymm2/mem to
VCVTQQ2PS xmm1 {k1}{z},
AVX512DQ
packed single precision floating-point values in xmm1 with
ymm2/m256/m64bcst
writemask k1.
EVEX.512.0F.W1 5B /r
A
V/V
AVX512DQ
Convert eight packed quadword integers from zmm2/mem to
VCVTQQ2PS ymm1 {k1}{z},
eight packed single precision floating-point values in ymm1 with
zmm2/m512/m64bcst{er}
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts packed quadword integers in the source operand (second operand) to packed single precision floating-
point values in the destination operand (first operand).
The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation
is a YMM/XMM/XMM (lower 64 bits) register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTQQ2PS (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN DEST[k+31:k] :=
Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[k+31:k] remains unchanged*
ELSE
; zeroing-masking
DEST[k+31:k] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0
5-80
Vol. 2C
VCVTQQ2PS—Convert Packed Quadword Integers to Packed Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V
VCVTQQ2PS (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[k+31:k] :=
Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[63:0])
ELSE
DEST[k+31:k] :=
Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[k+31:k] remains unchanged*
ELSE
; zeroing-masking
DEST[k+31:k] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTQQ2PS __m256 _mm512_cvtepi64_ps( __m512i a);
VCVTQQ2PS __m256 _mm512_mask_cvtepi64_ps( __m256 s, __mmask16 k, __m512i a);
VCVTQQ2PS __m256 _mm512_maskz_cvtepi64_ps( __mmask16 k, __m512i a);
VCVTQQ2PS __m256 _mm512_cvt_roundepi64_ps( __m512i a, int r);
VCVTQQ2PS __m256 _mm512_mask_cvt_roundepi_ps( __m256 s, __mmask8 k, __m512i a, int r);
VCVTQQ2PS __m256 _mm512_maskz_cvt_roundepi64_ps( __mmask8 k, __m512i a, int r);
VCVTQQ2PS __m128 _mm256_cvtepi64_ps( __m256i a);
VCVTQQ2PS __m128 _mm256_mask_cvtepi64_ps( __m128 s, __mmask8 k, __m256i a);
VCVTQQ2PS __m128 _mm256_maskz_cvtepi64_ps( __mmask8 k, __m256i a);
VCVTQQ2PS __m128 _mm_cvtepi64_ps( __m128i a);
VCVTQQ2PS __m128 _mm_mask_cvtepi64_ps( __m128 s, __mmask8 k, __m128i a);
VCVTQQ2PS __m128 _mm_maskz_cvtepi64_ps( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTQQ2PS—Convert Packed Quadword Integers to Packed Single Precision Floating-Point Values
Vol. 2C
5-81
INSTRUCTION SET REFERENCE, V
VCVTSD2SH—Convert Low FP64 Value to an FP16 Value
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.F2.MAP5.W1 5A /r
A
V/V
AVX512-FP16
Convert the low FP64 value in xmm3/m64 to an
VCVTSD2SH xmm1{k1}{z}, xmm2,
FP16 value and store the result in the low
xmm3/m64 {er}
element of xmm1 subject to writemask k1. Bits
127:16 of xmm2 are copied to xmm1[127:16].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction converts the low FP64 value in the second source operand to an FP16 value, and stores the result in
the low element of the destination operand.
When the conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register.
Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits
MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according
to the writemask.
Operation
VCVTSD2SH dest, src1, src2
IF *SRC2 is a register* and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
IF k1[0] OR *no writemask*:
DEST.fp16[0] := Convert_fp64_to_fp16(SRC2.fp64[0])
ELSE IF *zeroing*:
DEST.fp16[0] := 0
// else dest.fp16[0] remains unchanged
DEST[127:16] := SRC1[127:16]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSD2SH __m128h _mm_cvt_roundsd_sh (__m128h a, __m128d b, const int rounding);
VCVTSD2SH __m128h _mm_mask_cvt_roundsd_sh (__m128h src, __mmask8 k, __m128h a, __m128d b, const int rounding);
VCVTSD2SH __m128h _mm_maskz_cvt_roundsd_sh (__mmask8 k, __m128h a, __m128d b, const int rounding);
VCVTSD2SH __m128h _mm_cvtsd_sh (__m128h a, __m128d b);
VCVTSD2SH __m128h _mm_mask_cvtsd_sh (__m128h src, __mmask8 k, __m128h a, __m128d b);
VCVTSD2SH __m128h _mm_maskz_cvtsd_sh (__mmask8 k, __m128h a, __m128d b);
SIMD Floating-Point Exceptions
Invalid, Underflow, Overflow, Precision, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”
5-82
Vol. 2C
VCVTSD2SH—Convert Low FP64 Value to an FP16 Value
INSTRUCTION SET REFERENCE, V
VCVTSD2USI—Convert Scalar Double Precision Floating-Point Value to Unsigned Doubleword
Integer
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.LLIG.F2.0F.W0 79 /r
A
V/V
AVX512F
Convert one double precision floating-point value from
VCVTSD2USI r32, xmm1/m64{er}
xmm1/m64 to one unsigned doubleword integer r32.
EVEX.LLIG.F2.0F.W1 79 /r
A
V/N.E.1
AVX512F
Convert one double precision floating-point value from
VCVTSD2USI r64, xmm1/m64{er}
xmm1/m64 to one unsigned quadword integer zero-
extended into r64.
NOTES:
1. EVEX.W1 in non-64 bit is ignored; the instruction behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Fixed
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts a double precision floating-point value in the source operand (the second operand) to an unsigned
doubleword integer in the destination operand (the first operand). The source operand can be an XMM register or
a 64-bit memory location. The destination operand is a general-purpose register. When the source operand is an
XMM register, the double precision floating-point value is contained in the low quadword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is
returned, where w represents the number of bits in the destination format.
Operation
VCVTSD2USI (EVEX encoded version)
IF (SRC *is register*) AND (EVEX.b = 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
IF 64-Bit Mode and OperandSize = 64
THEN DEST[63:0] := Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]);
ELSE
DEST[31:0] := Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]);
FI
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSD2USI unsigned int _mm_cvtsd_u32(__m128d);
VCVTSD2USI unsigned int _mm_cvt_roundsd_u32(__m128d, int r);
VCVTSD2USI unsigned __int64 _mm_cvtsd_u64(__m128d);
VCVTSD2USI unsigned __int64 _mm_cvt_roundsd_u64(__m128d, int r);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”
VCVTSD2USI—Convert Scalar Double Precision Floating-Point Value to Unsigned Doubleword Integer
Vol. 2C
5-83
INSTRUCTION SET REFERENCE, V
VCVTSH2SD—Convert Low FP16 Value to an FP64 Value
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 5A /r
A
V/V
AVX512-FP16
Convert the low FP16 value in xmm3/m16 to an
VCVTSH2SD xmm1{k1}{z}, xmm2,
FP64 value and store the result in the low
xmm3/m16 {sae}
element of xmm1 subject to writemask k1. Bits
127:64 of xmm2 are copied to xmm1[127:64].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction converts the low FP16 element in the second source operand to a FP64 element in the low element
of the destination operand.
Bits 127:64 of the destination operand are copied from the corresponding bits of the first source operand. Bits
MAXVL-1:128 of the destination operand are zeroed. The low FP64 element of the destination is updated according
to the writemask.
Operation
VCVTSH2SD dest, src1, src2
IF k1[0] OR *no writemask*:
DEST.fp64[0] := Convert_fp16_to_fp64(SRC2.fp16[0])
ELSE IF *zeroing*:
DEST.fp64[0] := 0
// else dest.fp64[0] remains unchanged
DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSH2SD __m128d _mm_cvt_roundsh_sd (__m128d a, __m128h b, const int sae);
VCVTSH2SD __m128d _mm_mask_cvt_roundsh_sd (__m128d src, __mmask8 k, __m128d a, __m128h b, const int sae);
VCVTSH2SD __m128d _mm_maskz_cvt_roundsh_sd (__mmask8 k, __m128d a, __m128h b, const int sae);
VCVTSH2SD __m128d _mm_cvtsh_sd (__m128d a, __m128h b);
VCVTSH2SD __m128d _mm_mask_cvtsh_sd (__m128d src, __mmask8 k, __m128d a, __m128h b);
VCVTSH2SD __m128d _mm_maskz_cvtsh_sd (__mmask8 k, __m128d a, __m128h b);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”
5-84
Vol. 2C
VCVTSH2SD—Convert Low FP16 Value to an FP64 Value
INSTRUCTION SET REFERENCE, V
VCVTSH2SI—Convert Low FP16 Value to Signed Integer
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 2D /r
A
V/V1
AVX512-FP16
Convert the low FP16 element in xmm1/m16 to a
VCVTSH2SI r32, xmm1/m16 {er}
signed integer and store the result in r32.
EVEX.LLIG.F3.MAP5.W1 2D /r
A
V/N.E.
AVX512-FP16
Convert the low FP16 element in xmm1/m16 to a
VCVTSH2SI r64, xmm1/m16 {er}
signed integer and store the result in r64.
NOTES:
1. Outside of 64b mode, the EVEX.W field is ignored. The instruction behaves as if W=0 was used.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts the low FP16 element in the source operand to a signed integer in the destination general
purpose register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer indefinite value is
returned.
Operation
VCVTSH2SI dest, src
IF *SRC is a register* and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
IF 64-mode and OperandSize == 64:
DEST.qword := Convert_fp16_to_integer64(SRC.fp16[0])
ELSE:
DEST.dword := Convert_fp16_to_integer32(SRC.fp16[0])
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSH2SI int _mm_cvt_roundsh_i32 (__m128h a, int rounding);
VCVTSH2SI __int64 _mm_cvt_roundsh_i64 (__m128h a, int rounding);
VCVTSH2SI int _mm_cvtsh_i32 (__m128h a);
VCVTSH2SI __int64 _mm_cvtsh_i64 (__m128h a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”
VCVTSH2SI—Convert Low FP16 Value to Signed Integer
Vol. 2C
5-85
INSTRUCTION SET REFERENCE, V
VCVTSH2SS—Convert Low FP16 Value to FP32 Value
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.NP.MAP6.W0 13 /r
A
V/V
AVX512-FP16
Convert the low FP16 element in xmm3/m16 to
VCVTSH2SS xmm1{k1}{z}, xmm2,
an FP32 value and store in the low element of
xmm3/m16 {sae}
xmm1 subject to writemask k1. Bits 127:32 of
xmm2 are copied to xmm1[127:32].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction converts the low FP16 element in the second source operand to the low FP32 element of the desti-
nation operand.
Bits 127:32 of the destination operand are copied from the corresponding bits of the first source operand. Bits
MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according
to the writemask.
Operation
VCVTSH2SS dest, src1, src2
IF k1[0] OR *no writemask*:
DEST.fp32[0] := Convert_fp16_to_fp32(SRC2.fp16[0])
ELSE IF *zeroing*:
DEST.fp32[0] := 0
// else dest.fp32[0] remains unchanged
DEST[127:32] := SRC1[127:32]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSH2SS __m128 _mm_cvt_roundsh_ss (__m128 a, __m128h b, const int sae);
VCVTSH2SS __m128 _mm_mask_cvt_roundsh_ss (__m128 src, __mmask8 k, __m128 a, __m128h b, const int sae);
VCVTSH2SS __m128 _mm_maskz_cvt_roundsh_ss (__mmask8 k, __m128 a, __m128h b, const int sae);
VCVTSH2SS __m128 _mm_cvtsh_ss (__m128 a, __m128h b);
VCVTSH2SS __m128 _mm_mask_cvtsh_ss (__m128 src, __mmask8 k, __m128 a, __m128h b);
VCVTSH2SS __m128 _mm_maskz_cvtsh_ss (__mmask8 k, __m128 a, __m128h b);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”
5-86
Vol. 2C
VCVTSH2SS—Convert Low FP16 Value to FP32 Value
INSTRUCTION SET REFERENCE, V
VCVTSH2USI—Convert Low FP16 Value to Unsigned Integer
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 79 /r
A
V/V1
AVX512-FP16
Convert the low FP16 element in xmm1/m16 to
VCVTSH2USI r32, xmm1/m16 {er}
an unsigned integer and store the result in r32.
EVEX.LLIG.F3.MAP5.W1 79 /r
A
V/N.E.
AVX512-FP16
Convert the low FP16 element in xmm1/m16 to
VCVTSH2USI r64, xmm1/m16 {er}
an unsigned integer and store the result in r64.
NOTES:
1. Outside of 64b mode, the EVEX.W field is ignored. The instruction behaves as if W=0 was used.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts the low FP16 element in the source operand to an unsigned integer in the destination
general purpose register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer indefinite value is
returned.
Operation
VCVTSH2USI dest, src
// SET_RM() sets the rounding mode used for this instruction.
IF *SRC is a register* and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
IF 64-mode and OperandSize == 64:
DEST.qword := Convert_fp16_to_unsigned_integer64(SRC.fp16[0])
ELSE:
DEST.dword := Convert_fp16_to_unsigned_integer32(SRC.fp16[0])
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSH2USI unsigned int _mm_cvt_roundsh_u32 (__m128h a, int sae);
VCVTSH2USI unsigned __int64 _mm_cvt_roundsh_u64 (__m128h a, int rounding);
VCVTSH2USI unsigned int _mm_cvtsh_u32 (__m128h a);
VCVTSH2USI unsigned __int64 _mm_cvtsh_u64 (__m128h a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”
VCVTSH2USI—Convert Low FP16 Value to Unsigned Integer
Vol. 2C
5-87
INSTRUCTION SET REFERENCE, V
VCVTSI2SH—Convert a Signed Doubleword/Quadword Integer to an FP16 Value
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 2A /r
A
V/V1
AVX512-FP16
Convert the signed doubleword integer in r32/
VCVTSI2SH xmm1, xmm2, r32/m32
m32 to an FP16 value and store the result in
{er}
xmm1. Bits 127:16 of xmm2 are copied to
xmm1[127:16].
EVEX.LLIG.F3.MAP5.W1 2A /r
A
V/N.E.
AVX512-FP16
Convert the signed quadword integer in r64/m64
VCVTSI2SH xmm1, xmm2, r64/m64
to an FP16 value and store the result in xmm1.
{er}
Bits 127:16 of xmm2 are copied to
xmm1[127:16].
NOTES:
1. Outside of 64b mode, the EVEX.W field is ignored. The instruction behaves as if W=0 was used.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction converts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the
second source operand to an FP16 value in the destination operand. The result is stored in the low word of the desti-
nation operand. When conversion is inexact, the value returned is rounded according to the rounding control bits in
the MXCSR register or embedded rounding controls.
The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and
destination operands are XMM registers. Bits 127:16 of the XMM register destination are copied from corresponding
bits in the first source operand. Bits MAXVL-1:128 of the destination register are zeroed.
If the result of the convert operation is overflow and MXCSR.OM=0 then a SIMD exception will be raised with OE=1,
PE=1.
Operation
VCVTSI2SH dest, src1, src2
IF *SRC2 is a register* and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
IF 64-mode and OperandSize == 64:
DEST.fp16[0] := Convert_integer64_to_fp16(SRC2.qword)
ELSE:
DEST.fp16[0] := Convert_integer32_to_fp16(SRC2.dword)
DEST[127:16] := SRC1[127:16]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSI2SH __m128h _mm_cvt_roundi32_sh (__m128h a, int b, int rounding);
VCVTSI2SH __m128h _mm_cvt_roundi64_sh (__m128h a, __int64 b, int rounding);
VCVTSI2SH __m128h _mm_cvti32_sh (__m128h a, int b);
VCVTSI2SH __m128h _mm_cvti64_sh (__m128h a, __int64 b);
5-88
Vol. 2C
VCVTSI2SH—Convert a Signed Doubleword/Quadword Integer to an FP16 Value
INSTRUCTION SET REFERENCE, V
SIMD Floating-Point Exceptions
Overflow, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”
VCVTSI2SH—Convert a Signed Doubleword/Quadword Integer to an FP16 Value
Vol. 2C
5-89
INSTRUCTION SET REFERENCE, V
VCVTSS2SH—Convert Low FP32 Value to an FP16 Value
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.NP.MAP5.W0 1D /r
A
V/V
AVX512-FP16
Convert low FP32 value in xmm3/m32 to an
VCVTSS2SH xmm1{k1}{z}, xmm2,
FP16 value and store in the low element of
xmm3/m32 {er}
xmm1 subject to writemask k1. Bits 127:16 from
xmm2 are copied to xmm1[127:16].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction converts the low FP32 value in the second source operand to a FP16 value in the low element of the
destination operand.
When the conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register.
Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits
MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according
to the writemask.
Operation
VCVTSS2SH dest, src1, src2
IF *SRC2 is a register* and (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
IF k1[0] OR *no writemask*:
DEST.fp16[0] := Convert_fp32_to_fp16(SRC2.fp32[0])
ELSE IF *zeroing*:
DEST.fp16[0] := 0
// else dest.fp16[0] remains unchanged
DEST[127:16] := SRC1[127:16]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSS2SH __m128h _mm_cvt_roundss_sh (__m128h a, __m128 b, const int rounding);
VCVTSS2SH __m128h _mm_mask_cvt_roundss_sh (__m128h src, __mmask8 k, __m128h a, __m128 b, const int rounding);
VCVTSS2SH __m128h _mm_maskz_cvt_roundss_sh (__mmask8 k, __m128h a, __m128 b, const int rounding);
VCVTSS2SH __m128h _mm_cvtss_sh (__m128h a, __m128 b);
VCVTSS2SH __m128h _mm_mask_cvtss_sh (__m128h src, __mmask8 k, __m128h a, __m128 b);
VCVTSS2SH __m128h _mm_maskz_cvtss_sh (__mmask8 k, __m128h a, __m128 b);
SIMD Floating-Point Exceptions
Invalid, Underflow, Overflow, Precision, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”
5-90
Vol. 2C
VCVTSS2SH—Convert Low FP32 Value to an FP16 Value
INSTRUCTION SET REFERENCE, V
VCVTSS2USI—Convert Scalar Single Precision Floating-Point Value to Unsigned Doubleword
Integer
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.LLIG.F3.0F.W0 79 /r
A
V/V
AVX512F
Convert one single precision floating-point value from
VCVTSS2USI r32, xmm1/m32{er}
xmm1/m32 to one unsigned doubleword integer in r32.
EVEX.LLIG.F3.0F.W1 79 /r
A
V/N.E.1
AVX512F
Convert one single precision floating-point value from
VCVTSS2USI r64, xmm1/m32{er}
xmm1/m32 to one unsigned quadword integer in r64.
NOTES:
1. EVEX.W1 in non-64 bit is ignored; the instruction behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Fixed
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts a single precision floating-point value in the source operand (the second operand) to an unsigned double-
word integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand (the first
operand). The source operand can be an XMM register or a memory location. The destination operand is a general-
purpose register. When the source operand is an XMM register, the single precision floating-point value is contained
in the low doubleword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is
returned, where w represents the number of bits in the destination format.
VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTSS2USI (EVEX encoded version)
IF (SRC *is register*) AND (EVEX.b = 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
IF 64-bit Mode and OperandSize = 64
THEN
DEST[63:0] := Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0]);
ELSE
DEST[31:0] := Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0]);
FI;
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSS2USI unsigned _mm_cvtss_u32( __m128 a);
VCVTSS2USI unsigned _mm_cvt_roundss_u32( __m128 a, int r);
VCVTSS2USI unsigned __int64 _mm_cvtss_u64( __m128 a);
VCVTSS2USI unsigned __int64 _mm_cvt_roundss_u64( __m128 a, int r);
VCVTSS2USI—Convert Scalar Single Precision Floating-Point Value to Unsigned Doubleword Integer
Vol. 2C
5-91
INSTRUCTION SET REFERENCE, V
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”
5-92
Vol. 2C
VCVTSS2USI—Convert Scalar Single Precision Floating-Point Value to Unsigned Doubleword Integer
INSTRUCTION SET REFERENCE, V
VCVTTPD2QQ—Convert With Truncation Packed Double Precision Floating-Point Values to
Packed Quadword Integers
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F.W1 7A /r
A
V/V
AVX512VL
Convert two packed double precision floating-point values from
VCVTTPD2QQ xmm1 {k1}{z},
AVX512DQ
zmm2/m128/m64bcst to two packed quadword integers in
xmm2/m128/m64bcst
zmm1 using truncation with writemask k1.
EVEX.256.66.0F.W1 7A /r
A
V/V
AVX512VL
Convert four packed double precision floating-point values from
VCVTTPD2QQ ymm1 {k1}{z},
AVX512DQ
ymm2/m256/m64bcst to four packed quadword integers in
ymm2/m256/m64bcst
ymm1 using truncation with writemask k1.
EVEX.512.66.0F.W1 7A /r
A
V/V
AVX512DQ
Convert eight packed double precision floating-point values
VCVTTPD2QQ zmm1 {k1}{z},
from zmm2/m512 to eight packed quadword integers in zmm1
zmm2/m512/m64bcst{sae}
using truncation with writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts with truncation packed double precision floating-point values in the source operand (second operand) to
packed quadword integers in the destination operand (first operand).
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the indefinite integer value (2w-1, where w represents the number of bits in the destination format) is returned.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTTPD2QQ (EVEX encoded version) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTTPD2QQ—Convert With Truncation Packed Double Precision Floating-Point Values to Packed Quadword Integers
Vol. 2C
5-93
INSTRUCTION SET REFERENCE, V
VCVTTPD2QQ (EVEX encoded version) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[63:0])
ELSE
DEST[i+63:i] := Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPD2QQ __m512i _mm512_cvttpd_epi64( __m512d a);
VCVTTPD2QQ __m512i _mm512_mask_cvttpd_epi64( __m512i s, __mmask8 k, __m512d a);
VCVTTPD2QQ __m512i _mm512_maskz_cvttpd_epi64( __mmask8 k, __m512d a);
VCVTTPD2QQ __m512i _mm512_cvtt_roundpd_epi64( __m512d a, int sae);
VCVTTPD2QQ __m512i _mm512_mask_cvtt_roundpd_epi64( __m512i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2QQ __m512i _mm512_maskz_cvtt_roundpd_epi64( __mmask8 k, __m512d a, int sae);
VCVTTPD2QQ __m256i _mm256_mask_cvttpd_epi64( __m256i s, __mmask8 k, __m256d a);
VCVTTPD2QQ __m256i _mm256_maskz_cvttpd_epi64( __mmask8 k, __m256d a);
VCVTTPD2QQ __m128i _mm_mask_cvttpd_epi64( __m128i s, __mmask8 k, __m128d a);
VCVTTPD2QQ __m128i _mm_maskz_cvttpd_epi64( __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
5-94
Vol. 2C
VCVTTPD2QQ—Convert With Truncation Packed Double Precision Floating-Point Values to Packed Quadword Integers
INSTRUCTION SET REFERENCE, V
VCVTTPD2UDQ—Convert With Truncation Packed Double Precision Floating-Point Values to
Packed Unsigned Doubleword Integers
Opcode
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.0F.W1 78 /r
A
V/V
AVX512VL
Convert two packed double precision floating-point values
VCVTTPD2UDQ xmm1 {k1}{z},
AVX512F
in xmm2/m128/m64bcst to two unsigned doubleword
xmm2/m128/m64bcst
integers in xmm1 using truncation subject to writemask
k1.
EVEX.256.0F.W1 78 02 /r
A
V/V
AVX512VL
Convert four packed double precision floating-point
VCVTTPD2UDQ xmm1 {k1}{z},
AVX512F
values in ymm2/m256/m64bcst to four unsigned
ymm2/m256/m64bcst
doubleword integers in xmm1 using truncation subject to
writemask k1.
EVEX.512.0F.W1 78 /r
A
V/V
AVX512F
Convert eight packed double precision floating-point
VCVTTPD2UDQ ymm1 {k1}{z},
values in zmm2/m512/m64bcst to eight unsigned
zmm2/m512/m64bcst{sae}
doubleword integers in ymm1 using truncation subject to
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts with truncation packed double precision floating-point values in the source operand (the second operand)
to packed unsigned doubleword integers in the destination operand (the first operand).
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer value 2w - 1 is returned, where w represents the number of bits in the destination format.
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a YMM/XMM/XMM (low 64 bits) register
conditionally updated with writemask k1. The upper bits (MAXVL-1:256) of the corresponding destination are
zeroed.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTTPD2UDQ (EVEX encoded versions) when src2 operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
k := j * 64
IF k1[j] OR *no writemask*
THEN
DEST[i+31:i] :=
Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[k+63:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
VCVTTPD2UDQ—Convert With Truncation Packed Double Precision Floating-Point Values to Packed Unsigned Doubleword Integers
Vol. 2C
5-95
INSTRUCTION SET REFERENCE, V
DEST[MAXVL-1:VL/2] := 0
VCVTTPD2UDQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256),(8, 512)
FOR j := 0 TO KL-1
i := j * 32
k := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] :=
Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0])
ELSE
DEST[i+31:i] :=
Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[k+63:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL/2] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPD2UDQ __m256i _mm512_cvttpd_epu32( __m512d a);
VCVTTPD2UDQ __m256i _mm512_mask_cvttpd_epu32( __m256i s, __mmask8 k, __m512d a);
VCVTTPD2UDQ __m256i _mm512_maskz_cvttpd_epu32( __mmask8 k, __m512d a);
VCVTTPD2UDQ __m256i _mm512_cvtt_roundpd_epu32( __m512d a, int sae);
VCVTTPD2UDQ __m256i _mm512_mask_cvtt_roundpd_epu32( __m256i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2UDQ __m256i _mm512_maskz_cvtt_roundpd_epu32( __mmask8 k, __m512d a, int sae);
VCVTTPD2UDQ __m128i _mm256_mask_cvttpd_epu32( __m128i s, __mmask8 k, __m256d a);
VCVTTPD2UDQ __m128i _mm256_maskz_cvttpd_epu32( __mmask8 k, __m256d a);
VCVTTPD2UDQ __m128i _mm_mask_cvttpd_epu32( __m128i s, __mmask8 k, __m128d a);
VCVTTPD2UDQ __m128i _mm_maskz_cvttpd_epu32( __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTTPD2UDQ—Convert With Truncation Packed Double Precision Floating-Point Values to Packed Unsigned Doubleword Integers
5-96
Vol. 2C
INSTRUCTION SET REFERENCE, V
VCVTTPD2UQQ—Convert With Truncation Packed Double Precision Floating-Point Values to
Packed Unsigned Quadword Integers
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F.W1 78 /r
A
V/V
AVX512VL
Convert two packed double precision floating-point values
VCVTTPD2UQQ xmm1 {k1}{z},
AVX512DQ
from xmm2/m128/m64bcst to two packed unsigned
xmm2/m128/m64bcst
quadword integers in xmm1 using truncation with
writemask k1.
EVEX.256.66.0F.W1 78 /r
A
V/V
AVX512VL
Convert four packed double precision floating-point values
VCVTTPD2UQQ ymm1 {k1}{z},
AVX512DQ
from ymm2/m256/m64bcst to four packed unsigned
ymm2/m256/m64bcst
quadword integers in ymm1 using truncation with
writemask k1.
EVEX.512.66.0F.W1 78 /r
A
V/V
AVX512DQ
Convert eight packed double precision floating-point values
VCVTTPD2UQQ zmm1 {k1}{z},
from zmm2/mem to eight packed unsigned quadword
zmm2/m512/m64bcst{sae}
integers in zmm1 using truncation with writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts with truncation packed double precision floating-point values in the source operand (second operand) to
packed unsigned quadword integers in the destination operand (first operand).
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer value 2w - 1 is returned, where w represents the number of bits in the destination format.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTTPD2UQQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[i+63:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTTPD2UQQ—Convert With Truncation Packed Double Precision Floating-Point Values to Packed Unsigned Quadword Integers
Vol. 2C
5-97
INSTRUCTION SET REFERENCE, V
VCVTTPD2UQQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[63:0])
ELSE
DEST[i+63:i] :=
Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPD2UQQ _mm<size>[_mask[z]]_cvtt[_round]pd_epu64
VCVTTPD2UQQ __m512i _mm512_cvttpd_epu64( __m512d a);
VCVTTPD2UQQ __m512i _mm512_mask_cvttpd_epu64( __m512i s, __mmask8 k, __m512d a);
VCVTTPD2UQQ __m512i _mm512_maskz_cvttpd_epu64( __mmask8 k, __m512d a);
VCVTTPD2UQQ __m512i _mm512_cvtt_roundpd_epu64( __m512d a, int sae);
VCVTTPD2UQQ __m512i _mm512_mask_cvtt_roundpd_epu64( __m512i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2UQQ __m512i _mm512_maskz_cvtt_roundpd_epu64( __mmask8 k, __m512d a, int sae);
VCVTTPD2UQQ __m256i _mm256_mask_cvttpd_epu64( __m256i s, __mmask8 k, __m256d a);
VCVTTPD2UQQ __m256i _mm256_maskz_cvttpd_epu64( __mmask8 k, __m256d a);
VCVTTPD2UQQ __m128i _mm_mask_cvttpd_epu64( __m128i s, __mmask8 k, __m128d a);
VCVTTPD2UQQ __m128i _mm_maskz_cvttpd_epu64( __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTTPD2UQQ—Convert With Truncation Packed Double Precision Floating-Point Values to Packed Unsigned Quadword Integers
5-98
Vol. 2C
INSTRUCTION SET REFERENCE, V
VCVTTPH2DQ—Convert with Truncation Packed FP16 Values to Signed Doubleword Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.F3.MAP5.W0 5B /r
A
V/V
AVX512-FP16
Convert four packed FP16 values in xmm2/m64/
VCVTTPH2DQ xmm1{k1}{z}, xmm2/
AVX512VL
m16bcst to four signed doubleword integers, and
m64/m16bcst
store the result in xmm1 using truncation subject
to writemask k1.
EVEX.256.F3.MAP5.W0 5B /r
A
V/V
AVX512-FP16
Convert eight packed FP16 values in xmm2/
VCVTTPH2DQ ymm1{k1}{z}, xmm2/
AVX512VL
m128/m16bcst to eight signed doubleword
m128/m16bcst
integers, and store the result in ymm1 using
truncation subject to writemask k1.
EVEX.512.F3.MAP5.W0 5B /r
A
V/V
AVX512-FP16
Convert sixteen packed FP16 values in ymm2/
VCVTTPH2DQ zmm1{k1}{z}, ymm2/
m256/m16bcst to sixteen signed doubleword
m256/m16bcst {sae}
integers, and store the result in zmm1 using
truncation subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to signed doubleword integers in destination
operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than
the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is
masked, the indefinite integer value is returned.
The destination elements are updated according to the writemask.
Operation
VCVTTPH2DQ dest, src
VL = 128, 256 or 512
KL := VL / 32
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.fp32[j] := Convert_fp16_to_integer32_truncate(tsrc)
ELSE IF *zeroing*:
DEST.fp32[j] := 0
// else dest.fp32[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTTPH2DQ—Convert with Truncation Packed FP16 Values to Signed Doubleword Integers
Vol. 2C
5-99
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2DQ __m512i _mm512_cvtt_roundph_epi32 (__m256h a, int sae);
VCVTTPH2DQ __m512i _mm512_mask_cvtt_roundph_epi32 (__m512i src, __mmask16 k, __m256h a, int sae);
VCVTTPH2DQ __m512i _mm512_maskz_cvtt_roundph_epi32 (__mmask16 k, __m256h a, int sae);
VCVTTPH2DQ __m128i _mm_cvttph_epi32 (__m128h a);
VCVTTPH2DQ __m128i _mm_mask_cvttph_epi32 (__m128i src, __mmask8 k, __m128h a);
VCVTTPH2DQ __m128i _mm_maskz_cvttph_epi32 (__mmask8 k, __m128h a);
VCVTTPH2DQ __m256i _mm256_cvttph_epi32 (__m128h a);
VCVTTPH2DQ __m256i _mm256_mask_cvttph_epi32 (__m256i src, __mmask8 k, __m128h a);
VCVTTPH2DQ __m256i _mm256_maskz_cvttph_epi32 (__mmask8 k, __m128h a);
VCVTTPH2DQ __m512i _mm512_cvttph_epi32 (__m256h a);
VCVTTPH2DQ __m512i _mm512_mask_cvttph_epi32 (__m512i src, __mmask16 k, __m256h a);
VCVTTPH2DQ __m512i _mm512_maskz_cvttph_epi32 (__mmask16 k, __m256h a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-100
Vol. 2C
VCVTTPH2DQ—Convert with Truncation Packed FP16 Values to Signed Doubleword Integers
INSTRUCTION SET REFERENCE, V
VCVTTPH2QQ—Convert with Truncation Packed FP16 Values to Signed Quadword Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.MAP5.W0 7A /r
A
V/V
AVX512-FP16
Convert two packed FP16 values in xmm2/m32/
VCVTTPH2QQ xmm1{k1}{z}, xmm2/
AVX512VL
m16bcst to two signed quadword integers, and
m32/m16bcst
store the result in xmm1 using truncation subject
to writemask k1.
EVEX.256.66.MAP5.W0 7A /r
A
V/V
AVX512-FP16
Convert four packed FP16 values in xmm2/m64/
VCVTTPH2QQ ymm1{k1}{z}, xmm2/
AVX512VL
m16bcst to four signed quadword integers, and
m64/m16bcst
store the result in ymm1 using truncation subject
to writemask k1.
EVEX.512.66.MAP5.W0 7A /r
A
V/V
AVX512-FP16
Convert eight packed FP16 values in xmm2/
VCVTTPH2QQ zmm1{k1}{z}, xmm2/
m128/m16bcst to eight signed quadword
m128/m16bcst {sae}
integers, and store the result in zmm1 using
truncation subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Quarter
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to signed quadword integers in the destination
operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the indefinite integer value is returned.
The destination elements are updated according to the writemask.
Operation
VCVTTPH2QQ dest, src
VL = 128, 256 or 512
KL := VL / 64
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.qword[j] := Convert_fp16_to_integer64_truncate(tsrc)
ELSE IF *zeroing*:
DEST.qword[j] := 0
// else dest.qword[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTTPH2QQ—Convert with Truncation Packed FP16 Values to Signed Quadword Integers
Vol. 2C
5-101
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2QQ __m512i _mm512_cvtt_roundph_epi64 (__m128h a, int sae);
VCVTTPH2QQ __m512i _mm512_mask_cvtt_roundph_epi64 (__m512i src, __mmask8 k, __m128h a, int sae);
VCVTTPH2QQ __m512i _mm512_maskz_cvtt_roundph_epi64 (__mmask8 k, __m128h a, int sae);
VCVTTPH2QQ __m128i _mm_cvttph_epi64 (__m128h a);
VCVTTPH2QQ __m128i _mm_mask_cvttph_epi64 (__m128i src, __mmask8 k, __m128h a);
VCVTTPH2QQ __m128i _mm_maskz_cvttph_epi64 (__mmask8 k, __m128h a);
VCVTTPH2QQ __m256i _mm256_cvttph_epi64 (__m128h a);
VCVTTPH2QQ __m256i _mm256_mask_cvttph_epi64 (__m256i src, __mmask8 k, __m128h a);
VCVTTPH2QQ __m256i _mm256_maskz_cvttph_epi64 (__mmask8 k, __m128h a);
VCVTTPH2QQ __m512i _mm512_cvttph_epi64 (__m128h a);
VCVTTPH2QQ __m512i _mm512_mask_cvttph_epi64 (__m512i src, __mmask8 k, __m128h a);
VCVTTPH2QQ __m512i _mm512_maskz_cvttph_epi64 (__mmask8 k, __m128h a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-102
Vol. 2C
VCVTTPH2QQ—Convert with Truncation Packed FP16 Values to Signed Quadword Integers
INSTRUCTION SET REFERENCE, V
VCVTTPH2UDQ—Convert with Truncation Packed FP16 Values to Unsigned Doubleword
Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 78 /r
A
V/V
AVX512-FP16
Convert four packed FP16 values in xmm2/m64/
VCVTTPH2UDQ xmm1{k1}{z}, xmm2/
AVX512VL
m16bcst to four unsigned doubleword integers,
m64/m16bcst
and store the result in xmm1 using truncation
subject to writemask k1.
EVEX.256.NP.MAP5.W0 78 /r
A
V/V
AVX512-FP16
Convert eight packed FP16 values in xmm2/
VCVTTPH2UDQ ymm1{k1}{z}, xmm2/
AVX512VL
m128/m16bcst to eight unsigned doubleword
m128/m16bcst
integers, and store the result in ymm1 using
truncation subject to writemask k1.
EVEX.512.NP.MAP5.W0 78 /r
A
V/V
AVX512-FP16
Convert sixteen packed FP16 values in ymm2/
VCVTTPH2UDQ zmm1{k1}{z}, ymm2/
m256/m16bcst to sixteen unsigned doubleword
m256/m16bcst {sae}
integers, and store the result in zmm1 using
truncation subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to unsigned doubleword integers in the destina-
tion operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer indefinite value is returned.
The destination elements are updated according to the writemask.
Operation
VCVTTPH2UDQ dest, src
VL = 128, 256 or 512
KL := VL / 32
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.dword[j] := Convert_fp16_to_unsigned_integer32_truncate(tsrc)
ELSE IF *zeroing*:
DEST.dword[j] := 0
// else dest.dword[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTTPH2UDQ—Convert with Truncation Packed FP16 Values to Unsigned Doubleword Integers
Vol. 2C
5-103
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2UDQ __m512i _mm512_cvtt_roundph_epu32 (__m256h a, int sae);
VCVTTPH2UDQ __m512i _mm512_mask_cvtt_roundph_epu32 (__m512i src, __mmask16 k, __m256h a, int sae);
VCVTTPH2UDQ __m512i _mm512_maskz_cvtt_roundph_epu32 (__mmask16 k, __m256h a, int sae);
VCVTTPH2UDQ __m128i _mm_cvttph_epu32 (__m128h a);
VCVTTPH2UDQ __m128i _mm_mask_cvttph_epu32 (__m128i src, __mmask8 k, __m128h a);
VCVTTPH2UDQ __m128i _mm_maskz_cvttph_epu32 (__mmask8 k, __m128h a);
VCVTTPH2UDQ __m256i _mm256_cvttph_epu32 (__m128h a);
VCVTTPH2UDQ __m256i _mm256_mask_cvttph_epu32 (__m256i src, __mmask8 k, __m128h a);
VCVTTPH2UDQ __m256i _mm256_maskz_cvttph_epu32 (__mmask8 k, __m128h a);
VCVTTPH2UDQ __m512i _mm512_cvttph_epu32 (__m256h a);
VCVTTPH2UDQ __m512i _mm512_mask_cvttph_epu32 (__m512i src, __mmask16 k, __m256h a);
VCVTTPH2UDQ __m512i _mm512_maskz_cvttph_epu32 (__mmask16 k, __m256h a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-104
Vol. 2C
VCVTTPH2UDQ—Convert with Truncation Packed FP16 Values to Unsigned Doubleword Integers
INSTRUCTION SET REFERENCE, V
VCVTTPH2UQQ—Convert with Truncation Packed FP16 Values to Unsigned Quadword Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.MAP5.W0 78 /r
A
V/V
AVX512-FP16
Convert two packed FP16 values in xmm2/m32/
VCVTTPH2UQQ xmm1{k1}{z},
AVX512VL
m16bcst to two unsigned quadword integers,
xmm2/m32/m16bcst
and store the result in xmm1 using truncation
subject to writemask k1.
EVEX.256.66.MAP5.W0 78 /r
A
V/V
AVX512-FP16
Convert four packed FP16 values in xmm2/m64/
VCVTTPH2UQQ ymm1{k1}{z},
AVX512VL
m16bcst to four unsigned quadword integers,
xmm2/m64/m16bcst
and store the result in ymm1 using truncation
subject to writemask k1.
EVEX.512.66.MAP5.W0 78 /r
A
V/V
AVX512-FP16
Convert eight packed FP16 values in xmm2/
VCVTTPH2UQQ zmm1{k1}{z}, xmm2/
m128/m16bcst to eight unsigned quadword
m128/m16bcst {sae}
integers, and store the result in zmm1 using
truncation subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Quarter
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to unsigned quadword integers in the destina-
tion operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer indefinite value is returned.
The destination elements are updated according to the writemask.
Operation
VCVTTPH2UQQ dest, src
VL = 128, 256 or 512
KL := VL / 64
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.qword[j] := Convert_fp16_to_unsigned_integer64_truncate(tsrc)
ELSE IF *zeroing*:
DEST.qword[j] := 0
// else dest.qword[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTTPH2UQQ—Convert with Truncation Packed FP16 Values to Unsigned Quadword Integers
Vol. 2C
5-105
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2UQQ __m512i _mm512_cvtt_roundph_epu64 (__m128h a, int sae);
VCVTTPH2UQQ __m512i _mm512_mask_cvtt_roundph_epu64 (__m512i src, __mmask8 k, __m128h a, int sae);
VCVTTPH2UQQ __m512i _mm512_maskz_cvtt_roundph_epu64 (__mmask8 k, __m128h a, int sae);
VCVTTPH2UQQ __m128i _mm_cvttph_epu64 (__m128h a);
VCVTTPH2UQQ __m128i _mm_mask_cvttph_epu64 (__m128i src, __mmask8 k, __m128h a);
VCVTTPH2UQQ __m128i _mm_maskz_cvttph_epu64 (__mmask8 k, __m128h a);
VCVTTPH2UQQ __m256i _mm256_cvttph_epu64 (__m128h a);
VCVTTPH2UQQ __m256i _mm256_mask_cvttph_epu64 (__m256i src, __mmask8 k, __m128h a);
VCVTTPH2UQQ __m256i _mm256_maskz_cvttph_epu64 (__mmask8 k, __m128h a);
VCVTTPH2UQQ __m512i _mm512_cvttph_epu64 (__m128h a);
VCVTTPH2UQQ __m512i _mm512_mask_cvttph_epu64 (__m512i src, __mmask8 k, __m128h a);
VCVTTPH2UQQ __m512i _mm512_maskz_cvttph_epu64 (__mmask8 k, __m128h a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-106
Vol. 2C
VCVTTPH2UQQ—Convert with Truncation Packed FP16 Values to Unsigned Quadword Integers
INSTRUCTION SET REFERENCE, V
VCVTTPH2UW—Convert Packed FP16 Values to Unsigned Word Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.NP.MAP5.W0 7C /r
A
V/V
AVX512-FP16
Convert eight packed FP16 values in xmm2/
VCVTTPH2UW xmm1{k1}{z}, xmm2/
AVX512VL
m128/m16bcst to eight unsigned word integers,
m128/m16bcst
and store the result in xmm1 using truncation
subject to writemask k1.
EVEX.256.NP.MAP5.W0 7C /r
A
V/V
AVX512-FP16
Convert sixteen packed FP16 values in ymm2/
VCVTTPH2UW ymm1{k1}{z}, ymm2/
AVX512VL
m256/m16bcst to sixteen unsigned word
m256/m16bcst
integers, and store the result in ymm1 using
truncation subject to writemask k1.
EVEX.512.NP.MAP5.W0 7C /r
A
V/V
AVX512-FP16
Convert thirty-two packed FP16 values in zmm2/
VCVTTPH2UW zmm1{k1}{z}, zmm2/
m512/m16bcst to thirty-two unsigned word
m512/m16bcst {sae}
integers, and store the result in zmm1 using
truncation subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to unsigned word integers in the destination
operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer indefinite value is returned.
The destination elements are updated according to the writemask.
Operation
VCVTTPH2UW dest, src
VL = 128, 256 or 512
KL := VL / 16
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.word[j] := Convert_fp16_to_unsigned_integer16_truncate(tsrc)
ELSE IF *zeroing*:
DEST.word[j] := 0
// else dest.word[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTTPH2UW—Convert Packed FP16 Values to Unsigned Word Integers
Vol. 2C
5-107
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2UW __m512i _mm512_cvtt_roundph_epu16 (__m512h a, int sae);
VCVTTPH2UW __m512i _mm512_mask_cvtt_roundph_epu16 (__m512i src, __mmask32 k, __m512h a, int sae);
VCVTTPH2UW __m512i _mm512_maskz_cvtt_roundph_epu16 (__mmask32 k, __m512h a, int sae);
VCVTTPH2UW __m128i _mm_cvttph_epu16 (__m128h a);
VCVTTPH2UW __m128i _mm_mask_cvttph_epu16 (__m128i src, __mmask8 k, __m128h a);
VCVTTPH2UW __m128i _mm_maskz_cvttph_epu16 (__mmask8 k, __m128h a);
VCVTTPH2UW __m256i _mm256_cvttph_epu16 (__m256h a);
VCVTTPH2UW __m256i _mm256_mask_cvttph_epu16 (__m256i src, __mmask16 k, __m256h a);
VCVTTPH2UW __m256i _mm256_maskz_cvttph_epu16 (__mmask16 k, __m256h a);
VCVTTPH2UW __m512i _mm512_cvttph_epu16 (__m512h a);
VCVTTPH2UW __m512i _mm512_mask_cvttph_epu16 (__m512i src, __mmask32 k, __m512h a);
VCVTTPH2UW __m512i _mm512_maskz_cvttph_epu16 (__mmask32 k, __m512h a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-108
Vol. 2C
VCVTTPH2UW—Convert Packed FP16 Values to Unsigned Word Integers
INSTRUCTION SET REFERENCE, V
VCVTTPH2W—Convert Packed FP16 Values to Signed Word Integers
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.MAP5.W0 7C /r
A
V/V
AVX512-FP16
Convert eight packed FP16 values in xmm2/
VCVTTPH2W xmm1{k1}{z}, xmm2/
AVX512VL
m128/m16bcst to eight signed word integers,
m128/m16bcst
and store the result in xmm1 using truncation
subject to writemask k1.
EVEX.256.66.MAP5.W0 7C /r
A
V/V
AVX512-FP16
Convert sixteen packed FP16 values in ymm2/
VCVTTPH2W ymm1{k1}{z}, ymm2/
AVX512VL
m256/m16bcst to sixteen signed word integers,
m256/m16bcst
and store the result in ymm1 using truncation
subject to writemask k1.
EVEX.512.66.MAP5.W0 7C /r
A
V/V
AVX512-FP16
Convert thirty-two packed FP16 values in zmm2/
VCVTTPH2W zmm1{k1}{z}, zmm2/
m512/m16bcst to thirty-two signed word
m512/m16bcst {sae}
integers, and store the result in zmm1 using
truncation subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed FP16 values in the source operand to signed word integers in the destination
operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer indefinite value is returned.
The destination elements are updated according to the writemask.
Operation
VCVTTPH2W dest, src
VL = 128, 256 or 512
KL := VL / 16
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.fp16[0]
ELSE
tsrc := SRC.fp16[j]
DEST.word[j] := Convert_fp16_to_integer16_truncate(tsrc)
ELSE IF *zeroing*:
DEST.word[j] := 0
// else dest.word[j] remains unchanged
DEST[MAXVL-1:VL] := 0
VCVTTPH2W—Convert Packed FP16 Values to Signed Word Integers
Vol. 2C
5-109
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPH2W __m512i _mm512_cvtt_roundph_epi16 (__m512h a, int sae);
VCVTTPH2W __m512i _mm512_mask_cvtt_roundph_epi16 (__m512i src, __mmask32 k, __m512h a, int sae);
VCVTTPH2W __m512i _mm512_maskz_cvtt_roundph_epi16 (__mmask32 k, __m512h a, int sae);
VCVTTPH2W __m128i _mm_cvttph_epi16 (__m128h a);
VCVTTPH2W __m128i _mm_mask_cvttph_epi16 (__m128i src, __mmask8 k, __m128h a);
VCVTTPH2W __m128i _mm_maskz_cvttph_epi16 (__mmask8 k, __m128h a);
VCVTTPH2W __m256i _mm256_cvttph_epi16 (__m256h a);
VCVTTPH2W __m256i _mm256_mask_cvttph_epi16 (__m256i src, __mmask16 k, __m256h a);
VCVTTPH2W __m256i _mm256_maskz_cvttph_epi16 (__mmask16 k, __m256h a);
VCVTTPH2W __m512i _mm512_cvttph_epi16 (__m512h a);
VCVTTPH2W __m512i _mm512_mask_cvttph_epi16 (__m512i src, __mmask32 k, __m512h a);
VCVTTPH2W __m512i _mm512_maskz_cvttph_epi16 (__mmask32 k, __m512h a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-110
Vol. 2C
VCVTTPH2W—Convert Packed FP16 Values to Signed Word Integers
INSTRUCTION SET REFERENCE, V
VCVTTPS2UDQ—Convert With Truncation Packed Single Precision Floating-Point Values to
Packed Unsigned Doubleword Integer Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.0F.W0 78 /r
A
V/V
AVX512VL
Convert four packed single precision floating-point
VCVTTPS2UDQ xmm1 {k1}{z},
AVX512F
values from xmm2/m128/m32bcst to four packed
xmm2/m128/m32bcst
unsigned doubleword values in xmm1 using
truncation subject to writemask k1.
EVEX.256.0F.W0 78 /r
A
V/V
AVX512VL
Convert eight packed single precision floating-point
VCVTTPS2UDQ ymm1 {k1}{z},
AVX512F
values from ymm2/m256/m32bcst to eight packed
ymm2/m256/m32bcst
unsigned doubleword values in ymm1 using
truncation subject to writemask k1.
EVEX.512.0F.W0 78 /r
A
V/V
AVX512F
Convert sixteen packed single precision floating-
VCVTTPS2UDQ zmm1 {k1}{z},
point values from zmm2/m512/m32bcst to sixteen
zmm2/m512/m32bcst{sae}
packed unsigned doubleword values in zmm1 using
truncation subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts with truncation packed single precision floating-point values in the source operand to sixteen unsigned
doubleword integers in the destination operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer value 2w - 1 is returned, where w represents the number of bits in the destination format.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or
a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTTPS2UDQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] :=
Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTTPS2UDQ—Convert With Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Doubleword Integer Val-
Vol. 2C
5-111
INSTRUCTION SET REFERENCE, V
VCVTTPS2UDQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] :=
Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0])
ELSE
DEST[i+31:i] :=
Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPS2UDQ __m512i _mm512_cvttps_epu32( __m512 a);
VCVTTPS2UDQ __m512i _mm512_mask_cvttps_epu32( __m512i s, __mmask16 k, __m512 a);
VCVTTPS2UDQ __m512i _mm512_maskz_cvttps_epu32( __mmask16 k, __m512 a);
VCVTTPS2UDQ __m512i _mm512_cvtt_roundps_epu32( __m512 a, int sae);
VCVTTPS2UDQ __m512i _mm512_mask_cvtt_roundps_epu32( __m512i s, __mmask16 k, __m512 a, int sae);
VCVTTPS2UDQ __m512i _mm512_maskz_cvtt_roundps_epu32( __mmask16 k, __m512 a, int sae);
VCVTTPS2UDQ __m256i _mm256_mask_cvttps_epu32( __m256i s, __mmask8 k, __m256 a);
VCVTTPS2UDQ __m256i _mm256_maskz_cvttps_epu32( __mmask8 k, __m256 a);
VCVTTPS2UDQ __m128i _mm_mask_cvttps_epu32( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2UDQ __m128i _mm_maskz_cvttps_epu32( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTTPS2UDQ—Convert With Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Doubleword Integer Val-
5-112
Vol. 2C
INSTRUCTION SET REFERENCE, V
VCVTTPS2QQ—Convert With Truncation Packed Single Precision Floating-Point Values to
Packed Signed Quadword Integer Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F.W0 7A /r
A
V/V
AVX512VL
Convert two packed single precision floating-point values from
VCVTTPS2QQ xmm1 {k1}{z},
AVX512DQ
xmm2/m64/m32bcst to two packed signed quadword values in
xmm2/m64/m32bcst
xmm1 using truncation subject to writemask k1.
EVEX.256.66.0F.W0 7A /r
A
V/V
AVX512VL
Convert four packed single precision floating-point values from
VCVTTPS2QQ ymm1 {k1}{z},
AVX512DQ
xmm2/m128/m32bcst to four packed signed quadword values
xmm2/m128/m32bcst
in ymm1 using truncation subject to writemask k1.
EVEX.512.66.0F.W0 7A /r
A
V/V
AVX512DQ
Convert eight packed single precision floating-point values from
VCVTTPS2QQ zmm1 {k1}{z},
ymm2/m256/m32bcst to eight packed signed quadword values
ymm2/m256/m32bcst{sae}
in zmm1 using truncation subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts with truncation packed single precision floating-point values in the source operand to eight signed quad-
word integers in the destination operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the indefinite integer value (2w-1, where w represents the number of bits in the destination format) is returned.
EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64 bits) register or a 256/128/64-bit
memory location. The destination operation is a vector register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTTPS2QQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_Single_Precision_To_QuadInteger_Truncate(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTTPS2QQ—Convert With Truncation Packed Single Precision Floating-Point Values to Packed Signed Quadword Integer Values
Vol. 2C
5-113
INSTRUCTION SET REFERENCE, V
VCVTTPS2QQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_Single_Precision_To_QuadInteger_Truncate(SRC[31:0])
ELSE
DEST[i+63:i] :=
Convert_Single_Precision_To_QuadInteger_Truncate(SRC[k+31:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPS2QQ __m512i _mm512_cvttps_epi64( __m256 a);
VCVTTPS2QQ __m512i _mm512_mask_cvttps_epi64( __m512i s, __mmask16 k, __m256 a);
VCVTTPS2QQ __m512i _mm512_maskz_cvttps_epi64( __mmask16 k, __m256 a);
VCVTTPS2QQ __m512i _mm512_cvtt_roundps_epi64( __m256 a, int sae);
VCVTTPS2QQ __m512i _mm512_mask_cvtt_roundps_epi64( __m512i s, __mmask16 k, __m256 a, int sae);
VCVTTPS2QQ __m512i _mm512_maskz_cvtt_roundps_epi64( __mmask16 k, __m256 a, int sae);
VCVTTPS2QQ __m256i _mm256_mask_cvttps_epi64( __m256i s, __mmask8 k, __m128 a);
VCVTTPS2QQ __m256i _mm256_maskz_cvttps_epi64( __mmask8 k, __m128 a);
VCVTTPS2QQ __m128i _mm_mask_cvttps_epi64( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2QQ __m128i _mm_maskz_cvttps_epi64( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTTPS2QQ—Convert With Truncation Packed Single Precision Floating-Point Values to Packed Signed Quadword Integer Values
5-114
Vol. 2C
INSTRUCTION SET REFERENCE, V
VCVTTPS2UQQ—Convert With Truncation Packed Single Precision Floating-Point Values to
Packed Unsigned Quadword Integer Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F.W0 78 /r
A
V/V
AVX512VL
Convert two packed single precision floating-point values
VCVTTPS2UQQ xmm1 {k1}{z},
AVX512DQ
from xmm2/m64/m32bcst to two packed unsigned quadword
xmm2/m64/m32bcst
values in xmm1 using truncation subject to writemask k1.
EVEX.256.66.0F.W0 78 /r
A
V/V
AVX512VL
Convert four packed single precision floating-point values
VCVTTPS2UQQ ymm1 {k1}{z},
AVX512DQ
from xmm2/m128/m32bcst to four packed unsigned
xmm2/m128/m32bcst
quadword values in ymm1 using truncation subject to
writemask k1.
EVEX.512.66.0F.W0 78 /r
A
V/V
AVX512DQ
Convert eight packed single precision floating-point values
VCVTTPS2UQQ zmm1 {k1}{z},
from ymm2/m256/m32bcst to eight packed unsigned
ymm2/m256/m32bcst{sae}
quadword values in zmm1 using truncation subject to
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts with truncation up to eight packed single precision floating-point values in the source operand to
unsigned quadword integers in the destination operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer value 2w - 1 is returned, where w represents the number of bits in the destination format.
EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64 bits) register or a 256/128/64-bit
memory location. The destination operation is a vector register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
VCVTTPS2UQQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTTPS2UQQ—Convert With Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
Vol. 2C
5-115
INSTRUCTION SET REFERENCE, V
VCVTTPS2UQQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1)
THEN
DEST[i+63:i] :=
Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[31:0])
ELSE
DEST[i+63:i] :=
Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[k+31:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPS2UQQ _mm<size>[_mask[z]]_cvtt[_round]ps_epu64
VCVTTPS2UQQ __m512i _mm512_cvttps_epu64( __m256 a);
VCVTTPS2UQQ __m512i _mm512_mask_cvttps_epu64( __m512i s, __mmask16 k, __m256 a);
VCVTTPS2UQQ __m512i _mm512_maskz_cvttps_epu64( __mmask16 k, __m256 a);
VCVTTPS2UQQ __m512i _mm512_cvtt_roundps_epu64( __m256 a, int sae);
VCVTTPS2UQQ __m512i _mm512_mask_cvtt_roundps_epu64( __m512i s, __mmask16 k, __m256 a, int sae);
VCVTTPS2UQQ __m512i _mm512_maskz_cvtt_roundps_epu64( __mmask16 k, __m256 a, int sae);
VCVTTPS2UQQ __m256i _mm256_mask_cvttps_epu64( __m256i s, __mmask8 k, __m128 a);
VCVTTPS2UQQ __m256i _mm256_maskz_cvttps_epu64( __mmask8 k, __m128 a);
VCVTTPS2UQQ __m128i _mm_mask_cvttps_epu64( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2UQQ __m128i _mm_maskz_cvttps_epu64( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VCVTTPS2UQQ—Convert With Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values
5-116
Vol. 2C
INSTRUCTION SET REFERENCE, V
VCVTTSD2USI—Convert With Truncation Scalar Double Precision Floating-Point Value to
Unsigned Integer
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.LLIG.F2.0F.W0 78 /r
A
V/V
AVX512F
Convert one double precision floating-point value from
VCVTTSD2USI r32, xmm1/m64{sae}
xmm1/m64 to one unsigned doubleword integer r32
using truncation.
EVEX.LLIG.F2.0F.W1 78 /r
A
V/N.E.1
AVX512F
Convert one double precision floating-point value from
VCVTTSD2USI r64, xmm1/m64{sae}
xmm1/m64 to one unsigned quadword integer zero-
extended into r64 using truncation.
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instruction behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Fixed
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts with truncation a double precision floating-point value in the source operand (the second operand) to an
unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand
(the first operand). The source operand can be an XMM register or a 64-bit memory location. The destination
operand is a general-purpose register. When the source operand is an XMM register, the double precision floating-
point value is contained in the low quadword of the register.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer value 2w - 1 is returned, where w represents the number of bits in the destination format.
EVEX.W1 version: promotes the instruction to produce 64-bit data in 64-bit mode.
Operation
VCVTTSD2USI (EVEX encoded version)
IF 64-Bit Mode and OperandSize = 64
THEN DEST[63:0] := Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0]);
ELSE
DEST[31:0] := Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0]);
FI
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSD2USI unsigned int _mm_cvttsd_u32(__m128d);
VCVTTSD2USI unsigned int _mm_cvtt_roundsd_u32(__m128d, int sae);
VCVTTSD2USI unsigned __int64 _mm_cvttsd_u64(__m128d);
VCVTTSD2USI unsigned __int64 _mm_cvtt_roundsd_u64(__m128d, int sae);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”
VCVTTSD2USI—Convert With Truncation Scalar Double Precision Floating-Point Value to Unsigned Integer
Vol. 2C
5-117
INSTRUCTION SET REFERENCE, V
VCVTTSH2SI—Convert with Truncation Low FP16 Value to a Signed Integer
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 2C /r
A
V/V1
AVX512-FP16
Convert FP16 value in the low element of xmm1/
VCVTTSH2SI r32, xmm1/m16 {sae}
m16 to a signed integer and store the result in
r32 using truncation.
EVEX.LLIG.F3.MAP5.W1 2C /r
A
V/N.E.
AVX512-FP16
Convert FP16 value in the low element of xmm1/
VCVTTSH2SI r64, xmm1/m16 {sae}
m16 to a signed integer and store the result in
r64 using truncation.
NOTES:
1. Outside of 64b mode, the EVEX.W field is ignored. The instruction behaves as if W=0 was used.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts the low FP16 element in the source operand to a signed integer in the destination general
purpose register.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer indefinite value is returned.
Operation
VCVTTSH2SI dest, src
IF 64-mode and OperandSize == 64:
DEST.qword := Convert_fp16_to_integer64_truncate(SRC.fp16[0])
ELSE:
DEST.dword := Convert_fp16_to_integer32_truncate(SRC.fp16[0])
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSH2SI int _mm_cvtt_roundsh_i32 (__m128h a, int sae);
VCVTTSH2SI __int64 _mm_cvtt_roundsh_i64 (__m128h a, int sae);
VCVTTSH2SI int _mm_cvttsh_i32 (__m128h a);
VCVTTSH2SI __int64 _mm_cvttsh_i64 (__m128h a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”
5-118
Vol. 2C
VCVTTSH2SI—Convert with Truncation Low FP16 Value to a Signed Integer
INSTRUCTION SET REFERENCE, V
VCVTTSH2USI—Convert with Truncation Low FP16 Value to an Unsigned Integer
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.F3.MAP5.W0 78 /r
A
V/V1
AVX512-FP16
Convert FP16 value in the low element of xmm1/
VCVTTSH2USI r32, xmm1/m16 {sae}
m16 to an unsigned integer and store the result
in r32 using truncation.
EVEX.LLIG.F3.MAP5.W1 78 /r
A
V/N.E.
AVX512-FP16
Convert FP16 value in the low element of xmm1/
VCVTTSH2USI r64, xmm1/m16 {sae}
m16 to an unsigned integer and store the result
in r64 using truncation.
NOTES:
1. Outside of 64b mode, the EVEX.W field is ignored. The instruction behaves as if W=0 was used.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts the low FP16 element in the source operand to an unsigned integer in the destination
general purpose register.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer indefinite value is returned.
Operation
VCVTTSH2USI dest, src
IF 64-mode and OperandSize == 64:
DEST.qword := Convert_fp16_to_unsigned_integer64_truncate(SRC.fp16[0])
ELSE:
DEST.dword := Convert_fp16_to_unsigned_integer32_truncate(SRC.fp16[0])
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSH2USI unsigned int _mm_cvtt_roundsh_u32 (__m128h a, int sae);
VCVTTSH2USI unsigned __int64 _mm_cvtt_roundsh_u64 (__m128h a, int sae);
VCVTTSH2USI unsigned int _mm_cvttsh_u32 (__m128h a);
VCVTTSH2USI unsigned __int64 _mm_cvttsh_u64 (__m128h a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”
VCVTTSH2USI—Convert with Truncation Low FP16 Value to an Unsigned Integer
Vol. 2C
5-119
INSTRUCTION SET REFERENCE, V
VCVTTSS2USI—Convert With Truncation Scalar Single Precision Floating-Point Value to
Unsigned Integer
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.LLIG.F3.0F.W0 78 /r
A
V/V
AVX512F
Convert one single precision floating-point value from
VCVTTSS2USI r32, xmm1/m32{sae}
xmm1/m32 to one unsigned doubleword integer in
r32 using truncation.
EVEX.LLIG.F3.0F.W1 78 /r
A
V/N.E.1
AVX512F
Convert one single precision floating-point value from
VCVTTSS2USI r64, xmm1/m32{sae}
xmm1/m32 to one unsigned quadword integer in r64
using truncation.
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instruction behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Fixed
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts with truncation a single precision floating-point value in the source operand (the second operand) to an
unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand
(the first operand). The source operand can be an XMM register or a memory location. The destination operand is
a general-purpose register. When the source operand is an XMM register, the single precision floating-point value is
contained in the low doubleword of the register.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result cannot be
represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked,
the integer value 2w - 1 is returned, where w represents the number of bits in the destination format.
EVEX.W1 version: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTTSS2USI (EVEX encoded version)
IF 64-bit Mode and OperandSize = 64
THEN
DEST[63:0] := Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0]);
ELSE
DEST[31:0] := Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0]);
FI;
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSS2USI unsigned int _mm_cvttss_u32( __m128 a);
VCVTTSS2USI unsigned int _mm_cvtt_roundss_u32( __m128 a, int sae);
VCVTTSS2USI unsigned __int64 _mm_cvttss_u64( __m128 a);
VCVTTSS2USI unsigned __int64 _mm_cvtt_roundss_u64( __m128 a, int sae);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”
5-120
Vol. 2C
VCVTTSS2USI—Convert With Truncation Scalar Single Precision Floating-Point Value to Unsigned Integer
INSTRUCTION SET REFERENCE, V
VCVTUDQ2PD—Convert Packed Unsigned Doubleword Integers to Packed Double Precision
Floating-Point Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.F3.0F.W0 7A /r
A
V/V
AVX512VL
Convert two packed unsigned doubleword integers
VCVTUDQ2PD xmm1 {k1}{z},
AVX512F
from ymm2/m64/m32bcst to packed double precision
xmm2/m64/m32bcst
floating-point values in zmm1 with writemask k1.
EVEX.256.F3.0F.W0 7A /r
A
V/V
AVX512VL
Convert four packed unsigned doubleword integers
VCVTUDQ2PD ymm1 {k1}{z},
AVX512F
from xmm2/m128/m32bcst to packed double precision
xmm2/m128/m32bcst
floating-point values in zmm1 with writemask k1.
EVEX.512.F3.0F.W0 7A /r
A
V/V
AVX512F
Convert eight packed unsigned doubleword integers
VCVTUDQ2PD zmm1 {k1}{z},
from ymm2/m256/m32bcst to eight packed double
ymm2/m256/m32bcst
precision floating-point values in zmm1 with
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Half
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts packed unsigned doubleword integers in the source operand (second operand) to packed double precision
floating-point values in the destination operand (first operand).
The source operand is a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit memory location or a
256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM
register conditionally updated with writemask k1.
Attempt to encode this instruction with EVEX embedded rounding is ignored.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTUDQ2PD (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] :=
Convert_UInteger_To_Double_Precision_Floating_Point(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTUDQ2PD—Convert Packed Unsigned Doubleword Integers to Packed Double Precision Floating-Point Values
Vol. 2C
5-121
INSTRUCTION SET REFERENCE, V
VCVTUDQ2PD (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i] :=
Convert_UInteger_To_Double_Precision_Floating_Point(SRC[31:0])
ELSE
DEST[i+63:i] :=
Convert_UInteger_To_Double_Precision_Floating_Point(SRC[k+31:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUDQ2PD __m512d _mm512_cvtepu32_pd( __m256i a);
VCVTUDQ2PD __m512d _mm512_mask_cvtepu32_pd( __m512d s, __mmask8 k, __m256i a);
VCVTUDQ2PD __m512d _mm512_maskz_cvtepu32_pd( __mmask8 k, __m256i a);
VCVTUDQ2PD __m256d _mm256_cvtepu32_pd( __m128i a);
VCVTUDQ2PD __m256d _mm256_mask_cvtepu32_pd( __m256d s, __mmask8 k, __m128i a);
VCVTUDQ2PD __m256d _mm256_maskz_cvtepu32_pd( __mmask8 k, __m128i a);
VCVTUDQ2PD __m128d _mm_cvtepu32_pd( __m128i a);
VCVTUDQ2PD __m128d _mm_mask_cvtepu32_pd( __m128d s, __mmask8 k, __m128i a);
VCVTUDQ2PD __m128d _mm_maskz_cvtepu32_pd( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instructions, see Table 2-51, “Type E5 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
5-122
Vol. 2C
VCVTUDQ2PD—Convert Packed Unsigned Doubleword Integers to Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V
VCVTUDQ2PH—Convert Packed Unsigned Doubleword Integers to Packed FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.F2.MAP5.W0 7A /r
A
V/V
AVX512-FP16
Convert four packed unsigned doubleword
VCVTUDQ2PH xmm1{k1}{z}, xmm2/
AVX512VL
integers from xmm2/m128/m32bcst to packed
m128/m32bcst
FP16 values, and store the result in xmm1
subject to writemask k1.
EVEX.256.F2.MAP5.W0 7A /r
A
V/V
AVX512-FP16
Convert eight packed unsigned doubleword
VCVTUDQ2PH xmm1{k1}{z}, ymm2/
AVX512VL
integers from ymm2/m256/m32bcst to packed
m256/m32bcst
FP16 values, and store the result in xmm1
subject to writemask k1.
EVEX.512.F2.MAP5.W0 7A /r
A
V/V
AVX512-FP16
Convert sixteen packed unsigned doubleword
VCVTUDQ2PH ymm1{k1}{z}, zmm2/
integers from zmm2/m512/m32bcst to packed
m512/m32bcst {er}
FP16 values, and store the result in ymm1
subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction converts packed unsigned doubleword integers in the source operand to packed FP16 values in the
destination operand. The destination elements are updated according to the writemask.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
If the result of the convert operation is overflow and MXCSR.OM=0 then a SIMD exception will be raised with OE=1,
PE=1.
Operation
VCVTUDQ2PH dest, src
VL = 128, 256 or 512
KL := VL / 32
IF *SRC is a register* and (VL = 512) AND (EVEX.b = 1):
SET_RM(EVEX.RC)
ELSE:
SET_RM(MXCSR.RC)
FOR j := 0 TO KL-1:
IF k1[j] OR *no writemask*:
IF *SRC is memory* and EVEX.b = 1:
tsrc := SRC.dword[0]
ELSE
tsrc := SRC.dword[j]
DEST.fp16[j] := Convert_unsigned_integer32_to_fp16(tsrc)
ELSE IF *zeroing*:
DEST.fp16[j] := 0
// else dest.fp16[j] remains unchanged
DEST[MAXVL-1:VL/2] := 0
VCVTUDQ2PH—Convert Packed Unsigned Doubleword Integers to Packed FP16 Values
Vol. 2C
5-123
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUDQ2PH __m256h _mm512_cvt_roundepu32_ph (__m512i a, int rounding);
VCVTUDQ2PH __m256h _mm512_mask_cvt_roundepu32_ph (__m256h src, __mmask16 k, __m512i a, int rounding);
VCVTUDQ2PH __m256h _mm512_maskz_cvt_roundepu32_ph (__mmask16 k, __m512i a, int rounding);
VCVTUDQ2PH __m128h _mm_cvtepu32_ph (__m128i a);
VCVTUDQ2PH __m128h _mm_mask_cvtepu32_ph (__m128h src, __mmask8 k, __m128i a);
VCVTUDQ2PH __m128h _mm_maskz_cvtepu32_ph (__mmask8 k, __m128i a);
VCVTUDQ2PH __m128h _mm256_cvtepu32_ph (__m256i a);
VCVTUDQ2PH __m128h _mm256_mask_cvtepu32_ph (__m128h src, __mmask8 k, __m256i a);
VCVTUDQ2PH __m128h _mm256_maskz_cvtepu32_ph (__mmask8 k, __m256i a);
VCVTUDQ2PH __m256h _mm512_cvtepu32_ph (__m512i a);
VCVTUDQ2PH __m256h _mm512_mask_cvtepu32_ph (__m256h src, __mmask16 k, __m512i a);
VCVTUDQ2PH __m256h _mm512_maskz_cvtepu32_ph (__mmask16 k, __m512i a);
SIMD Floating-Point Exceptions
Overflow, Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-124
Vol. 2C
VCVTUDQ2PH—Convert Packed Unsigned Doubleword Integers to Packed FP16 Values
INSTRUCTION SET REFERENCE, V
VCVTUDQ2PS—Convert Packed Unsigned Doubleword Integers to Packed Single Precision
Floating-Point Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.F2.0F.W0 7A /r
A
V/V
AVX512VL
Convert four packed unsigned doubleword integers from
VCVTUDQ2PS xmm1 {k1}{z},
AVX512F
xmm2/m128/m32bcst to packed single precision
xmm2/m128/m32bcst
floating-point values in xmm1 with writemask k1.
EVEX.256.F2.0F.W0 7A /r
A
V/V
AVX512VL
Convert eight packed unsigned doubleword integers
VCVTUDQ2PS ymm1 {k1}{z},
AVX512F
from ymm2/m256/m32bcst to packed single precision
ymm2/m256/m32bcst
floating-point values in zmm1 with writemask k1.
EVEX.512.F2.0F.W0 7A /r
A
V/V
AVX512F
Convert sixteen packed unsigned doubleword integers
VCVTUDQ2PS zmm1 {k1}{z},
from zmm2/m512/m32bcst to sixteen packed single
zmm2/m512/m32bcst{er}
precision floating-point values in zmm1 with writemask
k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Converts packed unsigned doubleword integers in the source operand (second operand) to single precision
floating-point values in the destination operand (first operand).
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
VCVTUDQ2PS (EVEX encoded version) when src operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] :=
Convert_UInteger_To_Single_Precision_Floating_Point(SRC[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VCVTUDQ2PS—Convert Packed Unsigned Doubleword Integers to Packed Single Precision Floating-Point Values
Vol. 2C
5-125
INSTRUCTION SET REFERENCE, V
VCVTUDQ2PS (EVEX encoded version) when src operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] :=
Convert_UInteger_To_Single_Precision_Floating_Point(SRC[31:0])
ELSE
DEST[i+31:i] :=
Convert_UInteger_To_Single_Precision_Floating_Point(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VCVTUDQ2PS __m512 _mm512_cvtepu32_ps( __m512i a);
VCVTUDQ2PS __m512 _mm512_mask_cvtepu32_ps( __m512 s, __mmask16 k, __m512i a);
VCVTUDQ2PS __m512 _mm512_maskz_cvtepu32_ps( __mmask16 k, __m512i a);
VCVTUDQ2PS __m512 _mm512_cvt_roundepu32_ps( __m512i a, int r);
VCVTUDQ2PS __m512 _mm512_mask_cvt_roundepu32_ps( __m512 s, __mmask16 k, __m512i a, int r);
VCVTUDQ2PS __m512 _mm512_maskz_cvt_roundepu32_ps( __mmask16 k, __m512i a, int r);
VCVTUDQ2PS __m256 _mm256_cvtepu32_ps( __m256i a);
VCVTUDQ2PS __m256 _mm256_mask_cvtepu32_ps( __m256 s, __mmask8 k, __m256i a);
VCVTUDQ2PS __m256 _mm256_maskz_cvtepu32_ps( __mmask8 k, __m256i a);
VCVTUDQ2PS __m128 _mm_cvtepu32_ps( __m128i a);
VCVTUDQ2PS __m128 _mm_mask_cvtepu32_ps( __m128 s, __mmask8 k, __m128i a);
VCVTUDQ2PS __m128 _mm_maskz_cvtepu32_ps( __mmask8 k, __m128i a);
SIMD Floating-Point Exceptions
Precision
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
5-126
Vol. 2C
VCVTUDQ2PS—Convert Packed Unsigned Doubleword Integers to Packed Single Precision Floating-Point Values