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FANUC I/O Unit-MODEL A. CONNECTION AND MAINTENANCE MANUAL (B-61813E/04) - page 4

B-61813E/04

CONNECTION

6.ANALOG INPUT MODULE

6.2.3

Connecting with Analog Input Module

Analog input module (AAD04B)

I0+

①

I1+

250Ω

②

Voltage input (channel0)

③

Voltage

+

V1+

supply

④

-

V0-

GND

⑤

V1-

Multi

⑥

processor

COM0

⑦

Note

COM1

Note

4-2

⑧

AD

4-1

FG0

converter

⑨

FG1

⑩

I2+

250Ω

Note 2

⑪

I3+

⑫

V2+

Current input (channel 2)

⑬

Current

+

V3+

supply

⑭

-

V2-

GND

⑮

V3-

⑯

COM2

⑰

COM3

Note

Note

⑱

4-1

4-2

FG2

⑲

FG3

⑳

NOTE

1 Though the example above shows the connection of channels 0 and 2, it is just the

same with the channel 1 (I1+, V1+, V1-, COM1 and FG1) and the channel 3 (I3+, V3+,

V3-, COM3 and FG3).

2 Either voltage input or current input can be specified for each channel. When current

input is specified, make sure to short-circuit in + and Vn+ (n: 0 to 3).

3 Use shielded cables of twisted pair for connecting.

4 Fix a reference voltage by connecting the COMn (where n is 0, 1, 2, or 3) terminal of

this module to the common line (GND) of the voltage or current source to be used as

shown above (Note 4-1). If the voltage or current source has a terminal shared by the

external output (terminal OUT-) and ground (GND), the Vn- and COMn (where n is 0,

1, 2, or 3) of this module can be connected to each other as shown above (Note 4-2).

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B-61813E/04

CONNECTION

7.ANALOG OUTPUT MODULE

7.1

12-BIT ANALOG OUTPUT MODULE (ADA02A)

7.1.1

Specification

Item

Specification

Number of output

2 channels/module

channels

Digital input

12-bit binary (2's complement representation)

Analog output

-10VDC to +10VDC(external load resistance: 10KΩ or

more) ^{(Note 1)}

0mADC to +20mADC(external load resistance: 400Ω or

less)

Input/output

correspondence

Digital input

Analog output

+2000

+10V

+1000

+5V or +20mA

0

0V or 0mA

-1000

-5V

-2000

-10V

Resolution

5mV or 20µA

Comprehensive

Voltage output: ±0.5% (For the full scale)

accuracy

Current output: ±1% (For the full scale)

Converting time

1msec or less ^{(Note 2)}

Insulation

Photocoupler insulation (between output signal and

base).

However, non-insulation between output channels.

External connection

At removable terminal block (20 terminals, M3.5 screw

terminals)

Number of occupied

32 points

output points

NOTE

1 Which method to use, voltage input or current input,

can be selected by connecting the corresponding

input to the terminal block.

2 The converting time is the one only inside the

module. The actual response time is added a scan

time that is determined by the system.

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7.ANALOG OUTPUT MODULE

CONNECTION

B-61813E/04

7.1.2

Correspondence between Output Signals and Addresses in a

Module

In the analog output module ADA02A, a 12-bit digital value is written

into each of the following addresses to output the desired

voltage/current to its corresponding analog output.

Address

Bits

in module

7

6

5

4

3

2

1

0

0

D07-0

D06-0

D05-0

D04-0

D03-0

D02-0

D01-0

D00-0

Channel 0

1

-

-

-

-

D11-0

D10-0

D09-0

D08-0

2

D07-1

D06-1

D05-1

D04-1

D03-1

D02-1

D01-1

D00-1

Channel 1

3

-

-

-

-

D11-1

D10-1

D09-1

D08-1

D00-n corresponds to the 2⁰ weight, while D11-n corresponds to the 2¹¹

weight.

However, D11-n corresponds to the code bit

2's complement

representation.

NOTE

1 When setting an I/O module address, this module

initial address must be assigned to an even address.

To write a value that is to be converted from digital to

analog into a PMC program, be sure to write it in

words (16 bits).

2 Note that on the PMC-N, -NA, and -QA (PMC for the

Series 15 and F-D Mate), the high-order one byte

and low-order one byte of a word (16 bits) are

interchanged with each other as described below.

Addresses for word-unit operation in the PMC-N, NA, and QA

PMC → 12-bit analog output module

Module in

address

High-order byte

Low-order byte

Channel 0

0

D07-0 to D00-0

D11-0 to D08-0

Channel 1

+2

D07-1 to D00-1

D11-1 to D08-1

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B-61813E/04

CONNECTION

7.ANALOG OUTPUT MODULE

7.1.3

Connection to Analog Output Module

NOTE

1 Use a 2-core twisted shielded cable as the

connection cable

2 Ground the cable shield on the load side.

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7.ANALOG OUTPUT MODULE

CONNECTION

B-61813E/04

7.2

14-BIT ANALOG OUTPUT MODULE (ADA02B)

7.2.1

Specification

Item

Specification

Number of output

2 channels/module

channels

Digital input

14-bit binary (2's complement representation)

Analog output

•Voltage output

-10 VDC to +10 VDC (external load resistance of 10

kΩ or higher) ^{(Note 1)}

•Current output

0 mADC to +20 mADC (external load resistance of

400Ω or lower)

Input/output

correspondence

Analog output

Digital input

Voltage output

Current output

+8000

+10V

+20mA

+4000

+5V

+10mA

0

0

0

-4000

-5V

-

-8000

-10V

-

Resolution

Voltage output: 1.25 mV

Current output: 2.5 µA

Overall precision

Voltage output: ±0.5% (of the full scale)

Current output: ±1% (of the full scale)

Converting time

1 msec or shorter ^{(Note 2)}

Insulation

Photocoupler-based insulation between output signal

and base, but no insulation between output channels

External connection

Removable terminal block (20 terminals, M3.5 screw

terminal)

Number of occupied

32 points

output points

NOTE

1 Which method to use, voltage input or current input,

can be selected by connecting the corresponding

input to the terminal block.

2 The converting time is that inside the module. The

actual response time is added the scan time that is

determined by the system.

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B-61813E/04

CONNECTION

7.ANALOG OUTPUT MODULE

7.2.2

Correspondence between Output Signals and Addresses in

the Module

In the ADA02B analog output module, a 14-bit digital value is written

to each of the following address to output the desired voltage/current

from its corresponding analog output.

Address

Bits

in module

7

6

5

4

3

2

1

0

0

D07-0

D06-0

D05-0

D04-0

D03-0

D02-0

D01-0

D00-0

Channel 0

1

-

-

D13-0

D12-0

D11-0

D10-0

D9-0

D8-0

2

D07-1

D06-1

D05-1

D04-1

D03-1

D02-1

D01-1

D00-1

Channel 1

3

-

-

D13-1

D12-1

D11-1

D10-1

D9-1

D8-1

D00-n (where n is 0 or 1) corresponds to a weight of 2⁰, and D13-n to a

weight of 2¹³. However, D13-n corresponds to the sign bit of a two's

complement representation.

NOTE

1 When setting an I/O module address, this module

initial address must be assigned to an even address.

To write a value that is to be converted from digital to

analog into a PMC program, be sure to write it in

words (16 bits).

2 Note that on the PMC-N, -NA, and -QA (PMC for the

Series 15 and F-D Mate), the high-order one byte

and low-order one byte of a word (16 bits) are

interchanged with each other as described below.

Addresses for word-unit operation in the PMC-N, NA, and QA

PMC → 14-bit analog putput module

Module

inaddress

High-order byte

Low-order byte

Channel 0

0

D07-0 to D00-0

D13-0 to D08-0

Channel 1

+2

D07-1 to D00-1

D13-1 to D08-1

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7.ANALOG OUTPUT MODULE

CONNECTION

B-61813E/04

7.2.3

Connection between the Analog Output Module and Load

ADA02B

NOTE

1 Use a shielded 2-conductor twisted pair cable for the

connection between the analog output module and

load.

2 Ground the cable shielding on the load side.

- 96 -

8.HIGH-SPEED COUNTER MODULE CONNECTION

B-61813E/04

8.1

OUTLINE OF HIGH-SPEED COUNTER MODULE

The high-speed counter module consists of a counter which counts the

pulses sent from a pulse generator such as a position detector in the

machine tool and comparison registers for comparing preset values with

counter data. The module can read the counter data and output the

results of comparison to the machine.

The high-speed counter module can run in two different modes, mode A

and mode B. These two modes differ in the way data is compared.

Shown below are configuration diagrams, briefing either mode.

A. Mode A

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B-61813E/04

CONNECTION 8.HIGH-SPEED COUNTER MODULE

B. Mode B

to

to

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8.HIGH-SPEED COUNTER MODULE CONNECTION

B-61813E/04

8.2

SPECIFICATIONS OF HIGH-SPEED COUNTER MODULE

8.2.1

Pulse Counter

(1) Binary up/down counter (1)

(2) Counter capacity

0 to 8,388,607

(3) Counter data

The pulse counter can preset data and read count data.

8.2.2

Comparison Function

(1) Mode A

A. Comparison register (23 bits)

Comparison registers A, B, and C are provided. The values to

be compared are preset in the comparison registers.

B. Comparison output

The results (CMPA, CMPB, and CMPC) of comparing the

count data in the pulse counter with the data set in the

comparison registers are output.

C. Comparison output values

The comparison output values are set as listed in the table

below. The values depend on the states of CMA, CMB, and

CMC, the comparison mode signals from the PMC.

Counter value

Counter value

≤ comparison register value

> comparison register value

CMA=0

CMPA=0

CMPA=1

CMB=0

CMPB=0

CMPB=1

CMC=0

CMPC=0

CMPC=1

CMA=1

CMPA=1

CMPA=0

CMB=1

CMPB=1

CMPB=0

CMC=1

CMPC=1

CMPC=0

(2) Mode B

A. Comparison register (23 bits)

There are 16 comparison registers #0,#1, ...,#15. The values

to be compared are preset in the comparison registers. The

preset value in a comparison register having a larger register

number should be larger than that in a comparison register

having a smaller register number, as follows:

Value in register #0 < value in register #1< ... < value in

register #14 < value in register 15

B. Comparison output

The results (OUT0 to OUT7) of comparing the count data in

the pulse counter with the data set in the comparison registers

are output.

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B-61813E/04

CONNECTION 8.HIGH-SPEED COUNTER MODULE

C. Comparison output values

The count data in the pulse counter is compared with the

values in the comparison registers in sequential order from

register 0 until the count data is equal to or less than the value

in a comparison register. This enables a partition to be made

which includes the count data. Then the output data for the

partition (which is previously preset) is output. Eight output

points (OUT0 to OUT7) are provided.

If the count data is equal to the value in a comparison register,

the data in the partition having the same number as the

register number is output.

Assume that, when count data is in partition #n, the data to be

output is set to respective values in hexadecimal as listed below.

Output data from partition #0 = 0H

Output data from partition #1 = 1H

Output data from partition #2 = 2H

Output data from partition #3 = 3H

Output data from partition #4 = 4H

Output data from partition #5 = 5H

Output data from partition #6 = 6H

Output data from partition #7 = 7H

Output data from partition #8 = 8H

Output data from partition #9 = 9H

Output data from partition #10 = 10H

Output data from partition #11 = 11H

Output data from partition #12 = 12H

Output data from partition #13 = 13H

Output data from partition #14 = 20H

Output data from partition #15 = 21H

Output data from partition #16 = FFH

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8.HIGH-SPEED COUNTER MODULE CONNECTION

B-61813E/04

The output data is set as listed in the table below, depending on the

counter values in c to i above.

OUT

Partition

7

6

5

4

3

2

1

0

HEX value

①

0≤Counter value≤100

0

0

0

0

0

0

0

0

0h

②

100<Counter value≤200

0

0

0

0

0

0

0

1

1h

③

0

0

0

0

0

0

1

0

2h

200<Counter value≤300

④

0

0

0

0

0

0

1

0

2h

⑤

Comparison value in partition 14<Counter value≤1400

0

0

1

0

0

0

0

0

20h

⑥

1400<Counter value≤1500

0

0

1

0

0

0

0

1

21h

⑦

1500<Counter value≤8,388,607

1

1

1

1

1

1

1

1

FFh

NOTE

Preset an increasingly larger value in each of the

compare registers (#0, #1, ..., #15) as the register

number becomes larger.

Unless this condition is satisfied, it is likely that no

normal compensation may take place, leading to an

abnormal compare output.

8.2.3

Pulse Interface

The following three types of pulses are entered in the high-speed

counter module.

A. Phase A/B pulses: The phase difference between

these detection pulses is 90°

B.

+/- pulses: These detection pulses are separated

in the positive and negative directions.

Select either type of the detection pulse.

C. Marker signal: Used to preset data in the pulse counter.

(1)

Phase A/B pulse interface

The phase A/B pulses are selected when the PSEL signal is open.

A. Interface IC

The signal of the pulse generator connected to the high-speed

counter module is equivalent to that of the line driver

SN75113. It also equivalent to that of the AM26LS31. The

signals involved are the equilibrium transmission signals

shown below.

Voh

PA

Vol

Voh

*PA

Vol

(The PB and MKS signals are the same, respectively, as PA

and *PB. The *MKS signal is the same as *PA.)

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B-61813E/04

CONNECTION 8.HIGH-SPEED COUNTER MODULE

The voltage ratings of the receiver in this module are: Voh =

2.4 V or higher and Vol = 0.45 V or lower. Be sure to use a

pulse generator having a driver that satisfies these voltage

requirements.

If you want to use a commercial rotary encoder as the pulse

generator, select "line driver type output" that meets the

above voltage requirements. It is impossible to use any

output type (such as open-collector output or voltage output

type) having a higher output rating.

B. Maximum frequency

Tmin.

=8µS

(minimum period)

TDmin. =1.2µS (minimum time between edges)

C. Count and direction

A counter multiplied by four compared to phase A and B

pulses is provided. It counts positive when phase A advances

before phase B and it counts negative when phase B advances

before phase A.

Positive count

Advance of phase A before phase B

Negative count

Advance of phase B before phase A

- 103 -

8.HIGH-SPEED COUNTER MODULE CONNECTION

B-61813E/04

(2) Positive/negative pulse interface

Positive and negative pulses are selected when the PSEL signal is

connected to 0 VDC.

A. Interface IC

See Paragraph A, "Interface IC", in Item (1), "Phase A/B

pulse interface".

B. Maximum frequency

Tmin.

= 2µS

(minimum period)

TDmin. = 0.5µS

(minimum pulse width)

(3) Marker signal

A. Interface IC

Use differential drivers

(SN75113 or equivalent) at the

output ports of the pulse generator.

B. Minimum pulse width

- 104 -

8.HIGH-SPEED COUNTER MODULE CONNECTION

B-61813E/04

8.2.6

Marker Processing

(1)

Mode A

A. Synchronization with marker

The counter value is set to the data in the counter preset

register at the rising edge of the first marker signal with the

MS signal output from the PMC set to 1 and the contact of the

marker enable signal input (ME) from the machine closed.

B. Marker hold

The MH signal is set to 1 at the rising edge of the first marker

signal with the MS signal output from the PMC set to 1 and

the contact of the marker enable signal input (ME) from the

machine closed. The MH signal is reset when the marker

hold reset (MHR), an output signal from the PMC, is set to 1

or the MS signal output from the PMC is set to 0.

(2)

Mode B

A. Synchronization with marker

When the MS signal output from the PMC is 1 and the

contact of the marker enable (ME) signal input from the

machine is closed, the counter is set to the data in the counter

preset register at the rising edge of the first marker signal.

B. Maker hold

When the MS signal output from the PMC is 1 and the

contact of the marker enable (ME) signal input from the

machine is closed, the MH signal is set to 1 at the rising edge

of the marker signal. The MH signal is reset when the MS

signal output from the PMC is set to 0.

(3)

Pin treatment when no marker signal is used

If you use

(that is, preset) no marker signal, treat the

corresponding pin as shown below. Otherwise, a broken-wire

alarm will be raised. The counter keeps running even after a

broken-wire alarm is raised, though.

Counter module

Cable

If the treatment shown above cannot prevent a broken-wire alarm

from being raised, make sure that the GND terminal of the pulse

generator is connected to the LGND

(0V) pin of the JA9

connector.

- 106 -

8.HIGH-SPEED COUNTER MODULE CONNECTION

B-61813E/04

(7) Comparison result output indicators (OUT0, OUT1, OUT2, OUT3,

OUT4, OUT5, OUT6, and OUT7)

A. Mode A

The indicators OUT0, OUT1, and OUT2 correspond to the

signals CMPA, CMPB, and CMPC. OUT1 goes on when

CMPA goes on, OUT2 goes on when CMPB goes on, and

OUT3 goes on when CMPC goes on.

B. Mode B

The indicators OUT0 - OUT7 go on corresponding to when

the output data OUT0 - OUT7resulting from the comparisons

between the count data and comparison resisters are set to 1.

LED indicator panel

OK

ALM0

ALM1

Explanation of alarm

Disconnection alarm

: On

Self-diagnosis alarm, RAM error

: Off

Self-diagnosis alarm, ROM error

Watch dog alarm

Normal operation

The state of the OK, ALM0, or ALM1 is not held.

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B-61813E/04

CONNECTION 8.HIGH-SPEED COUNTER MODULE

8.3

PMC INTERFACE

8.3.1

Mode A

(1) PMC I/O area

In mode A, four input bytes and four output bytes are used as the

I/O area. The bytes in the I/O area have the following names. The

input and output directions are specified on the basis of the PMC.

The operation mode is set to mode A at power-on.

(a) Output data (sent from PMC to high-speed counter module)

0

CTRL (control)

+1

DTOH (higher 8-bit data)

+2

DTOM (middle 8-bit data)

+3

DTOL (lower 8-bit data)

(b) Input data (entered from high-speed counter module to PMC)

0

CNTS (counter H and status)

+1

CNTM (middle 8 bits of counter)

+2

CNTL (lower 8 bits of counter)

+3

STTS (status)

(2) PMC outputs (entered from PMC to high-speed counter module)

The PMC outputs are separated into control output CTRL and data

outputs DTOH, DTOM, and DTOL. As with normal DOs, the

control outputs of bit 3 to bit 7 are controlled independently. The

control outputs of bit0 to bit2 constitute the SELECT indicating

the target data specified by DTOH, DTOM, and DTOL.

(a) Control output

CTRL

7

6

5

4

3

2

1

0

MHR

MS

CE

PRS

SELECT

PRS

: Preset

CE

: Count enable

MS

: Marker synchronization

MHR : Marker hold reset

(b) Details of DTOH, DTOM, and DTOL

The SELECT bits indicate the target data.

SELECT

0

CCTR (comparison control)

1

Counter preset data

2

Comparison register A

3

Comparison register B

4

Comparison register C

7

Change to mode B

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8.HIGH-SPEED COUNTER MODULE CONNECTION

B-61813E/04

NOTE

1 Change to mode B: See Section 8.3.2, "Mode B".

2 Detail of CCTR

DTOH

7

6

5

4

3

2

1

0

CMC

CMB

CMA

The DTOM and DTOL are ignored.

(3) PMC inputs (entered from high-speed counter module to PMC)

The inputs to the PMC include the status and counter data. The

data is shown below.

0

CNTS (counter H and status)

+1

CNTM (middle 8 bits of counter)

+2

CNTL (lower 8 bits of counter)

+3

STTS (status)

NOTE

1 Details of CNTS

7

6

5

4

3

2

1

0

TRA

Counter H (most significant 7 bits)

TRA

: Transfer A

NOTE

2 Details of STTS

7

6

5

4

3

2

1

0

TRB

ALM

CSP

ME

MH

CMPC

CMPB

CMPA

CMPA : Comparison output A

CMPB : Comparison output B

CMPC : Comparison output C

MH

: Marker hold

ME

: Marker enable

CSP

: Count stop

ALM : Alarm (disconnection or watch dog alarm)

TRB

: Transfer B

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B-61813E/04

CONNECTION 8.HIGH-SPEED COUNTER MODULE

8.3.2

Mode B

Change to mode B

The operation mode is set to mode A at power-on. The following data is

output to the counter module and the mode changes from A to B. The

mode cannot change from B to A.

0

CTRL

:

0FH (SELECT = 7, PRS = 1)

+1

DTOH

:

01H

+2

DTOM

:

00H

+3

DTOL

:

00H

(1) PMC I/O area

In mode B, eight input bytes and four output bytes are used as the

I/O area. The bytes in the I/O area have the following names. The

input and output directions are specified on the basis of the PMC.

(a) Output data (sent from PMC to high-speed counter module)

0

CTRL (control)

+1

DTOH (higher 8-bit data)

+2

DTOM (middle 8-bit data)

+3

DTOL (lower 8-bit data)

(b) Input data (entered from high-speed counter module to PMC)

0

CNTS (counter H and status)

+1

CNTM (middle 8 bits of counter)

+2

CNTL (lower 8 bits of counter)

+3

STTS (status)

+4

OUTD

+5

MODD

+6

Unused

+7

Unused

(2) PMC outputs (outputs from PMC)

The PMC outputs are separated into control output CTRL and data

outputs DTOH, DTOM, and DTOL. As with normal DOs, the

control outputs of bit 5 to bit 7 are controlled independently. The

control outputs of bit 0 to bit 4 constitute SELECT indicating the

target data specified by DTOH, DTOM, and DTOL.

(a) Control outputs

CTRL

7

6

5

4

3

2

1

0

MS

CE

PRS

SELECT

PRS

: Preset

CE

: Count enable

MS

: Marker synchronization

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8.HIGH-SPEED COUNTER MODULE CONNECTION

B-61813E/04

(b) Details of DTOH, DTOM, and DTOL

Enter the comparison value and preset value (24 bits) to the

DTOH, DTOM, and DTOL.

Enter a comparison result (8 bits) output for each partition,

respectively, to the DTOH, DTOM, and DTOL.

SELECT

Target data

0

Comparison data : Specify a comparison value (24 bits) for partition #0.

1

Comparison data : Specify a comparison value (24 bits) for partition #1.

2

Comparison data : Specify a comparison value (24 bits) for partition #2.

3

Comparison data : Specify a comparison value (24 bits) for partition #3.

4

Comparison data : Specify a comparison value (24 bits) for partition #4.

5

Comparison data : Specify a comparison value (24 bits) for partition #5.

6

Comparison data : Specify a comparison value (24 bits) for partition #6.

7

Comparison data : Specify a comparison value (24 bits) for partition #7.

8

Comparison data : Specify a comparison value (24 bits) for partition #8.

9

Comparison data : Specify a comparison value (24 bits) for partition #9.

10

Comparison data : Specify a comparison value (24 bits) for partition #10.

11

Comparison data : Specify a comparison value (24 bits) for partition #11.

12

Comparison data : Specify a comparison value (24 bits) for partition #12.

13

Comparison data : Specify a comparison value (24 bits) for partition #13.

14

Comparison data : Specify a comparison value (24 bits) for partition #14.

15

Comparison data : Specify a comparison value (24 bits) for partition #15.

16

Comparison output data (8 bits) for partition #0 to #2

Partition #0: DTOH

Partition #1: DTOM

Partition #2: DTOL

17

Comparison output data (8 bits) for partition #3 to #5

Partition #3: DTOH

Partition #4: DTOM

Partition #5: DTOL

18

Comparison output data (8 bits) for partition #6 to #8

Partition #6: DTOH

Partition #7: DTOM

Partition #8: DTOL

19

Comparison output data (8 bits) for partition #9 to #11

Partition #9: DTOH

Partition #10: DTOM

Partition #11: DTOL

20

Comparison output data (8 bits) for partition #12 to #14

Partition #12: DTOH

Partition #13: DTOM

Partition #14: DTOL

21

Comparison output data (8 bits) for partition #15 and #16

Partition #15: DTOH

Partition #16: DTOM

22

Counter preset data (24 bits)

(The numbers of DTOH, DTOM, and DTOL indicate the output data

for the partitions specified by the numbers.)

- 112 -

B-61813E/04

CONNECTION 8.HIGH-SPEED COUNTER MODULE

(c) PMC inputs (inputs to PMC)

The inputs to the PMC include the status and counter data.

The data is shown below.

0

CNTS (counter H and status)

+1

CNTM (middle 8 bits of counter)

+2

CNTL (lower 8 bits of counter)

+3

STTS (status)

+4

OUTD

+5

MODD

+6

Not used

+7

Not used

NOTE

1 Detail of CNTS

7

6

5

4

3

2

1

0

TRA

Counter H (most significant 7 bits)

TRA

: Transfer A

NOTE

2 Details of STTS

7

6

5

4

3

2

1

0

TRB

ALM

CSP

ME

MH

MH

: Marker hold

ME

: Marker enable

CSP

: Count stop

ALM : Alarm (disconnection or watch dog alarm)

TRB

: Transfer B

NOTE

3 Detail of OUTD

7

6

5

4

3

2

1

0

OUT7

OUT6

OUT5

OUT4

OUT3

OUT2

OUT1

OUT0

OUT0 : Bit 0 of comparison output

OUT1 : Bit 1 of comparison output

OUT2 : Bit 2 of comparison output

OUT3 : Bit 3 of comparison output

OUT4 : Bit 4 of comparison output

OUT5 : Bit 5 of comparison output

OUT6 : Bit 6 of comparison output

OUT7 : Bit 7 of comparison output

- 113 -

8.HIGH-SPEED COUNTER MODULE CONNECTION

B-61813E/04

NOTE

4 Detail of MODD

7

6

5

4

3

2

1

0

MOD0

MOD0 : Set to 1 after the mode changes to B.

8.3.3

Details of PMC Interface Signals

(1)

PMC inputs (inputs from PMC)

(a)

TRA and TRB

The counter data is valid when TRA is equal to TRB and

invalid when TRA is not equal to TRB.

(b)

CMPA, CMPB, and CMPC (comparison output signals A, B,

and C, only in mode A)

The CMPA, CMPB, and CMPC signals are output signals

resulting from the comparison between the comparison

registers A, B, and C and the counter data, respectively. The

output levels of CMPA, CMPB, and CMPC are determined

by the comparison mode signals CMA, CMB, and CMC.

When CMA, CMB, and CMC are 0, and the counter data is

larger than the values in comparison registers A, B, and C,

CMPA, CMPB, and CMPC are set to 1.

When CMA, CMB, and CMC are 1, and the counter data is

equal to or less than the values in comparison registers A, B,

and C, CMPA, CMPB, and CMPC are set to 1.

(c)

OUT0 to OUT 7 (comparison output signal 0 to comparison

output signal 7, only in mode B)

OUT0 - OUT7 correspond to bit 0 to bit 7 in the comparison

result output of a single byte.

(d)

MH (marker hold signal)

The marker hold signal MH is set to 1 at the rising edge of the

marker signal when the marker enable signal is 1. The marker

hold signal is reset when MHR=1 or MS=0. (In mode B, the

marker hold signal MH is reset only when MS=0.)

(e)

ME (marker enable signal)

The marker enable signal ME enables the marker signal as

follows:

ME=1: Marker signal enabled

ME=0: Marker signal disabled

(f)

CSP (count stop signal)

The counter stops counting when the contact for the external

input signal CSP is closed.

- 114 -

B-61813E/04

CONNECTION 8.HIGH-SPEED COUNTER MODULE

8.4

TOTAL CONNECTION OF HIGH-SPEED COUNTER

MODULE

8.4.1

Connection Diagram

HONDA TSUSHIN (PCR-E20FA)

JA9

Detection pulse generator

C49

Machine (power magnetics

HIROSE ELECTRIC

cabinet)

(HIF-3BA-20D-2.54R)

A63L-0001-0472#S20

High-speed counter module

8.4.2

Connector Signal List

JA9

10

20

+5V

9

+5V

19

8

PSEL

18

+5V

7

LGND

17

6

*MKS

16

LGND

5

MKS

18

4

*PBS

14

LGND

3

PBS

13

2

*PAS

12

LGND

1

PAS

11

PAS : Phase A pulse input signal (Negative pulse input signal)

(positive)

*PAS

: Phase A pulse input signal (Negative pulse input signal)

(negative)

PBS

: Phase B pulse input signal

(Positive pulse input signal)

(positive)

*PBS

: Phase B pulse input signal

(Positive pulse input signal)

(negative)

MKS : Marker signal (positive)

*MKS : Marker signal (negative)

PSEL : Pulse select signal

+5V

:

5V (output from this module)

LGND : 0V

- 117 -

8.HIGH-SPEED COUNTER MODULE CONNECTION

B-61813E/04

8.4.2.1

C49 signal (for mode A)

C49

A

B

01

ME

02

CSP

03

COM1

04

05

06

CMP A

07

CMP B

08

CMP C

09

10

COM2

ME

: Marker enable signal input

CSP

: Counter stop signal input

CMP A : Comparison result output

CMP B : Comparison result output

CMP C : Comparison result output

COM1

: Common signal for ME and CSP

COM2

: Common signal for comparison result output CMP A to

comparison result output CMP C

8.4.2.2

C49 signal (for mode B)

C49

A

B

01

ME

02

CSP

03

COM1

04

05

06

OUT0

OUT4

07

OUT1

OUT5

08

OUT2

OUT6

09

OUT3

OUT7

10

COM2

COM3

ME

:

Marker enable signal input

CSP

:

Counter stop signal input

OUT0 :

Comparison result output

OUT1 :

Comparison result output

OUT2 :

Comparison result output

OUT3 :

Comparison result output

OUT4 :

Comparison result output

OUT5 :

Comparison result output

OUT6 :

Comparison result output

OUT7 :

Comparison result output

COM1 :

Common signal for ME and CSP

COM2 :

Common signal for comparison result output 0 to comparison

result output 3

COM3 :

Common signal for comparison result output 4 to comparison

result output 7

- 118 -

B-61813E/04

CONNECTION 8.HIGH-SPEED COUNTER MODULE

8.5

CONNECTION WITH PULSE GENERATOR

8.5.1

Use of Phase A and B Pulses

High-speed counter module

Pulse generator

Phase A

pulse signal

input

Phase B

pulse signal

input

Marker

signal input

Line receiver SN75115

Line receiver SN75113

Use these

lines together.

Use these

lines together.

Shield

Grounding plate

(*) The maximum current rating for each 5-V output is 300 mA.

Recommended cable

A66L-0001-0286 (#20AWG×7, #24AWG×3 Pairs)

- 119 -

8.HIGH-SPEED COUNTER MODULE CONNECTION

B-61813E/04

8.5.2

Use of Positive/Negative Pulses

Pulse generator

High-speed counter module

Negative

pulse signal

input

Positive

pulse signal

input

Marker

signal input

Line receiver SN75115

Line receiver SN75113

Use these

lines together.

Use these

lines together.

Shield

Grounding plate

(*) The maximum current rating for each 5-V output is 300 mA.

Recommended cable

A66L-0001-0286 (#20AWG×8, #24AWG×3 Pairs)

- 120 -

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