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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 130

 

 

MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
C31H
3121
MSR_B0_PMON_CTR0
Package
Uncore B-box 0 perfmon counter MSR.
C32H
3122
MSR_B0_PMON_EVNT_SEL1
Package
Uncore B-box 0 perfmon event select MSR.
C33H
3123
MSR_B0_PMON_CTR1
Package
Uncore B-box 0 perfmon counter MSR.
C34H
3124
MSR_B0_PMON_EVNT_SEL2
Package
Uncore B-box 0 perfmon event select MSR.
C35H
3125
MSR_B0_PMON_CTR2
Package
Uncore B-box 0 perfmon counter MSR.
C36H
3126
MSR_B0_PMON_EVNT_SEL3
Package
Uncore B-box 0 perfmon event select MSR.
C37H
3127
MSR_B0_PMON_CTR3
Package
Uncore B-box 0 perfmon counter MSR.
C40H
3136
MSR_S0_PMON_BOX_CTRL
Package
Uncore S-box 0 perfmon local box control MSR.
C41H
3137
MSR_S0_PMON_BOX_STATUS
Package
Uncore S-box 0 perfmon local box status MSR.
C42H
3138
MSR_S0_PMON_BOX_OVF_CTRL
Package
Uncore S-box 0 perfmon local box overflow control
MSR.
C50H
3152
MSR_S0_PMON_EVNT_SEL0
Package
Uncore S-box 0 perfmon event select MSR.
C51H
3153
MSR_S0_PMON_CTR0
Package
Uncore S-box 0 perfmon counter MSR.
C52H
3154
MSR_S0_PMON_EVNT_SEL1
Package
Uncore S-box 0 perfmon event select MSR.
C53H
3155
MSR_S0_PMON_CTR1
Package
Uncore S-box 0 perfmon counter MSR.
C54H
3156
MSR_S0_PMON_EVNT_SEL2
Package
Uncore S-box 0 perfmon event select MSR.
C55H
3157
MSR_S0_PMON_CTR2
Package
Uncore S-box 0 perfmon counter MSR.
C56H
3158
MSR_S0_PMON_EVNT_SEL3
Package
Uncore S-box 0 perfmon event select MSR.
C57H
3159
MSR_S0_PMON_CTR3
Package
Uncore S-box 0 perfmon counter MSR.
C60H
3168
MSR_B1_PMON_BOX_CTRL
Package
Uncore B-box 1 perfmon local box control MSR.
C61H
3169
MSR_B1_PMON_BOX_STATUS
Package
Uncore B-box 1 perfmon local box status MSR.
C62H
3170
MSR_B1_PMON_BOX_OVF_CTRL
Package
Uncore B-box 1 perfmon local box overflow control
MSR.
C70H
3184
MSR_B1_PMON_EVNT_SEL0
Package
Uncore B-box 1 perfmon event select MSR.
C71H
3185
MSR_B1_PMON_CTR0
Package
Uncore B-box 1 perfmon counter MSR.
C72H
3186
MSR_B1_PMON_EVNT_SEL1
Package
Uncore B-box 1 perfmon event select MSR.
C73H
3187
MSR_B1_PMON_CTR1
Package
Uncore B-box 1 perfmon counter MSR.
Vol. 4
2-165
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
C74H
3188
MSR_B1_PMON_EVNT_SEL2
Package
Uncore B-box 1 perfmon event select MSR.
C75H
3189
MSR_B1_PMON_CTR2
Package
Uncore B-box 1 perfmon counter MSR.
C76H
3190
MSR_B1_PMON_EVNT_SEL3
Package
Uncore B-box 1vperfmon event select MSR.
C77H
3191
MSR_B1_PMON_CTR3
Package
Uncore B-box 1 perfmon counter MSR.
C80H
3120
MSR_W_PMON_BOX_CTRL
Package
Uncore W-box perfmon local box control MSR.
C81H
3121
MSR_W_PMON_BOX_STATUS
Package
Uncore W-box perfmon local box status MSR.
C82H
3122
MSR_W_PMON_BOX_OVF_CTRL
Package
Uncore W-box perfmon local box overflow control
MSR.
C90H
3136
MSR_W_PMON_EVNT_SEL0
Package
Uncore W-box perfmon event select MSR.
C91H
3137
MSR_W_PMON_CTR0
Package
Uncore W-box perfmon counter MSR.
C92H
3138
MSR_W_PMON_EVNT_SEL1
Package
Uncore W-box perfmon event select MSR.
C93H
3139
MSR_W_PMON_CTR1
Package
Uncore W-box perfmon counter MSR.
C94H
3140
MSR_W_PMON_EVNT_SEL2
Package
Uncore W-box perfmon event select MSR.
C95H
3141
MSR_W_PMON_CTR2
Package
Uncore W-box perfmon counter MSR.
C96H
3142
MSR_W_PMON_EVNT_SEL3
Package
Uncore W-box perfmon event select MSR.
C97H
3143
MSR_W_PMON_CTR3
Package
Uncore W-box perfmon counter MSR.
CA0H
3232
MSR_M0_PMON_BOX_CTRL
Package
Uncore M-box 0 perfmon local box control MSR.
CA1H
3233
MSR_M0_PMON_BOX_STATUS
Package
Uncore M-box 0 perfmon local box status MSR.
CA2H
3234
MSR_M0_PMON_BOX_OVF_CTRL
Package
Uncore M-box 0 perfmon local box overflow control
MSR.
CA4H
3236
MSR_M0_PMON_TIMESTAMP
Package
Uncore M-box 0 perfmon time stamp unit select
MSR.
CA5H
3237
MSR_M0_PMON_DSP
Package
Uncore M-box 0 perfmon DSP unit select MSR.
CA6H
3238
MSR_M0_PMON_ISS
Package
Uncore M-box 0 perfmon ISS unit select MSR.
CA7H
3239
MSR_M0_PMON_MAP
Package
Uncore M-box 0 perfmon MAP unit select MSR.
CA8H
3240
MSR_M0_PMON_MSC_THR
Package
Uncore M-box 0 perfmon MIC THR select MSR.
CA9H
3241
MSR_M0_PMON_PGT
Package
Uncore M-box 0 perfmon PGT unit select MSR.
CAAH
3242
MSR_M0_PMON_PLD
Package
Uncore M-box 0 perfmon PLD unit select MSR.
CABH
3243
MSR_M0_PMON_ZDP
Package
Uncore M-box 0 perfmon ZDP unit select MSR.
CB0H
3248
MSR_M0_PMON_EVNT_SEL0
Package
Uncore M-box 0 perfmon event select MSR.
CB1H
3249
MSR_M0_PMON_CTR0
Package
Uncore M-box 0 perfmon counter MSR.
2-166 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
CB2H
3250
MSR_M0_PMON_EVNT_SEL1
Package
Uncore M-box 0 perfmon event select MSR.
CB3H
3251
MSR_M0_PMON_CTR1
Package
Uncore M-box 0 perfmon counter MSR.
CB4H
3252
MSR_M0_PMON_EVNT_SEL2
Package
Uncore M-box 0 perfmon event select MSR.
CB5H
3253
MSR_M0_PMON_CTR2
Package
Uncore M-box 0 perfmon counter MSR.
CB6H
3254
MSR_M0_PMON_EVNT_SEL3
Package
Uncore M-box 0 perfmon event select MSR.
CB7H
3255
MSR_M0_PMON_CTR3
Package
Uncore M-box 0 perfmon counter MSR.
CB8H
3256
MSR_M0_PMON_EVNT_SEL4
Package
Uncore M-box 0 perfmon event select MSR.
CB9H
3257
MSR_M0_PMON_CTR4
Package
Uncore M-box 0 perfmon counter MSR.
CBAH
3258
MSR_M0_PMON_EVNT_SEL5
Package
Uncore M-box 0 perfmon event select MSR.
CBBH
3259
MSR_M0_PMON_CTR5
Package
Uncore M-box 0 perfmon counter MSR.
CC0H
3264
MSR_S1_PMON_BOX_CTRL
Package
Uncore S-box 1 perfmon local box control MSR.
CC1H
3265
MSR_S1_PMON_BOX_STATUS
Package
Uncore S-box 1 perfmon local box status MSR.
CC2H
3266
MSR_S1_PMON_BOX_OVF_CTRL
Package
Uncore S-box 1 perfmon local box overflow control
MSR.
CD0H
3280
MSR_S1_PMON_EVNT_SEL0
Package
Uncore S-box 1 perfmon event select MSR.
CD1H
3281
MSR_S1_PMON_CTR0
Package
Uncore S-box 1 perfmon counter MSR.
CD2H
3282
MSR_S1_PMON_EVNT_SEL1
Package
Uncore S-box 1 perfmon event select MSR.
CD3H
3283
MSR_S1_PMON_CTR1
Package
Uncore S-box 1 perfmon counter MSR.
CD4H
3284
MSR_S1_PMON_EVNT_SEL2
Package
Uncore S-box 1 perfmon event select MSR.
CD5H
3285
MSR_S1_PMON_CTR2
Package
Uncore S-box 1 perfmon counter MSR.
CD6H
3286
MSR_S1_PMON_EVNT_SEL3
Package
Uncore S-box 1 perfmon event select MSR.
CD7H
3287
MSR_S1_PMON_CTR3
Package
Uncore S-box 1 perfmon counter MSR.
CE0H
3296
MSR_M1_PMON_BOX_CTRL
Package
Uncore M-box 1 perfmon local box control MSR.
CE1H
3297
MSR_M1_PMON_BOX_STATUS
Package
Uncore M-box 1 perfmon local box status MSR.
CE2H
3298
MSR_M1_PMON_BOX_OVF_CTRL
Package
Uncore M-box 1 perfmon local box overflow control
MSR.
CE4H
3300
MSR_M1_PMON_TIMESTAMP
Package
Uncore M-box 1 perfmon time stamp unit select
MSR.
CE5H
3301
MSR_M1_PMON_DSP
Package
Uncore M-box 1 perfmon DSP unit select MSR.
Vol. 4
2-167
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
CE6H
3302
MSR_M1_PMON_ISS
Package
Uncore M-box 1 perfmon ISS unit select MSR.
CE7H
3303
MSR_M1_PMON_MAP
Package
Uncore M-box 1 perfmon MAP unit select MSR.
CE8H
3304
MSR_M1_PMON_MSC_THR
Package
Uncore M-box 1 perfmon MIC THR select MSR.
CE9H
3305
MSR_M1_PMON_PGT
Package
Uncore M-box 1 perfmon PGT unit select MSR.
CEAH
3306
MSR_M1_PMON_PLD
Package
Uncore M-box 1 perfmon PLD unit select MSR.
CEBH
3307
MSR_M1_PMON_ZDP
Package
Uncore M-box 1 perfmon ZDP unit select MSR.
CF0H
3312
MSR_M1_PMON_EVNT_SEL0
Package
Uncore M-box 1 perfmon event select MSR.
CF1H
3313
MSR_M1_PMON_CTR0
Package
Uncore M-box 1 perfmon counter MSR.
CF2H
3314
MSR_M1_PMON_EVNT_SEL1
Package
Uncore M-box 1 perfmon event select MSR.
CF3H
3315
MSR_M1_PMON_CTR1
Package
Uncore M-box 1 perfmon counter MSR.
CF4H
3316
MSR_M1_PMON_EVNT_SEL2
Package
Uncore M-box 1 perfmon event select MSR.
CF5H
3317
MSR_M1_PMON_CTR2
Package
Uncore M-box 1 perfmon counter MSR.
CF6H
3318
MSR_M1_PMON_EVNT_SEL3
Package
Uncore M-box 1 perfmon event select MSR.
CF7H
3319
MSR_M1_PMON_CTR3
Package
Uncore M-box 1 perfmon counter MSR.
CF8H
3320
MSR_M1_PMON_EVNT_SEL4
Package
Uncore M-box 1 perfmon event select MSR.
CF9H
3321
MSR_M1_PMON_CTR4
Package
Uncore M-box 1 perfmon counter MSR.
CFAH
3322
MSR_M1_PMON_EVNT_SEL5
Package
Uncore M-box 1 perfmon event select MSR.
CFBH
3323
MSR_M1_PMON_CTR5
Package
Uncore M-box 1 perfmon counter MSR.
D00H
3328
MSR_C0_PMON_BOX_CTRL
Package
Uncore C-box 0 perfmon local box control MSR.
D01H
3329
MSR_C0_PMON_BOX_STATUS
Package
Uncore C-box 0 perfmon local box status MSR.
D02H
3330
MSR_C0_PMON_BOX_OVF_CTRL
Package
Uncore C-box 0 perfmon local box overflow control
MSR.
D10H
3344
MSR_C0_PMON_EVNT_SEL0
Package
Uncore C-box 0 perfmon event select MSR.
D11H
3345
MSR_C0_PMON_CTR0
Package
Uncore C-box 0 perfmon counter MSR.
D12H
3346
MSR_C0_PMON_EVNT_SEL1
Package
Uncore C-box 0 perfmon event select MSR.
D13H
3347
MSR_C0_PMON_CTR1
Package
Uncore C-box 0 perfmon counter MSR.
D14H
3348
MSR_C0_PMON_EVNT_SEL2
Package
Uncore C-box 0 perfmon event select MSR.
D15H
3349
MSR_C0_PMON_CTR2
Package
Uncore C-box 0 perfmon counter MSR.
2-168 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
D16H
3350
MSR_C0_PMON_EVNT_SEL3
Package
Uncore C-box 0 perfmon event select MSR.
D17H
3351
MSR_C0_PMON_CTR3
Package
Uncore C-box 0 perfmon counter MSR.
D18H
3352
MSR_C0_PMON_EVNT_SEL4
Package
Uncore C-box 0 perfmon event select MSR.
D19H
3353
MSR_C0_PMON_CTR4
Package
Uncore C-box 0 perfmon counter MSR.
D1AH
3354
MSR_C0_PMON_EVNT_SEL5
Package
Uncore C-box 0 perfmon event select MSR.
D1BH
3355
MSR_C0_PMON_CTR5
Package
Uncore C-box 0 perfmon counter MSR.
D20H
3360
MSR_C4_PMON_BOX_CTRL
Package
Uncore C-box 4 perfmon local box control MSR.
D21H
3361
MSR_C4_PMON_BOX_STATUS
Package
Uncore C-box 4 perfmon local box status MSR.
D22H
3362
MSR_C4_PMON_BOX_OVF_CTRL
Package
Uncore C-box 4 perfmon local box overflow control
MSR.
D30H
3376
MSR_C4_PMON_EVNT_SEL0
Package
Uncore C-box 4 perfmon event select MSR.
D31H
3377
MSR_C4_PMON_CTR0
Package
Uncore C-box 4 perfmon counter MSR.
D32H
3378
MSR_C4_PMON_EVNT_SEL1
Package
Uncore C-box 4 perfmon event select MSR.
D33H
3379
MSR_C4_PMON_CTR1
Package
Uncore C-box 4 perfmon counter MSR.
D34H
3380
MSR_C4_PMON_EVNT_SEL2
Package
Uncore C-box 4 perfmon event select MSR.
D35H
3381
MSR_C4_PMON_CTR2
Package
Uncore C-box 4 perfmon counter MSR.
D36H
3382
MSR_C4_PMON_EVNT_SEL3
Package
Uncore C-box 4 perfmon event select MSR.
D37H
3383
MSR_C4_PMON_CTR3
Package
Uncore C-box 4 perfmon counter MSR.
D38H
3384
MSR_C4_PMON_EVNT_SEL4
Package
Uncore C-box 4 perfmon event select MSR.
D39H
3385
MSR_C4_PMON_CTR4
Package
Uncore C-box 4 perfmon counter MSR.
D3AH
3386
MSR_C4_PMON_EVNT_SEL5
Package
Uncore C-box 4 perfmon event select MSR.
D3BH
3387
MSR_C4_PMON_CTR5
Package
Uncore C-box 4 perfmon counter MSR.
D40H
3392
MSR_C2_PMON_BOX_CTRL
Package
Uncore C-box 2 perfmon local box control MSR.
D41H
3393
MSR_C2_PMON_BOX_STATUS
Package
Uncore C-box 2 perfmon local box status MSR.
D42H
3394
MSR_C2_PMON_BOX_OVF_CTRL
Package
Uncore C-box 2 perfmon local box overflow control
MSR.
D50H
3408
MSR_C2_PMON_EVNT_SEL0
Package
Uncore C-box 2 perfmon event select MSR.
D51H
3409
MSR_C2_PMON_CTR0
Package
Uncore C-box 2 perfmon counter MSR.
Vol. 4
2-169
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
D52H
3410
MSR_C2_PMON_EVNT_SEL1
Package
Uncore C-box 2 perfmon event select MSR.
D53H
3411
MSR_C2_PMON_CTR1
Package
Uncore C-box 2 perfmon counter MSR.
D54H
3412
MSR_C2_PMON_EVNT_SEL2
Package
Uncore C-box 2 perfmon event select MSR.
D55H
3413
MSR_C2_PMON_CTR2
Package
Uncore C-box 2 perfmon counter MSR.
D56H
3414
MSR_C2_PMON_EVNT_SEL3
Package
Uncore C-box 2 perfmon event select MSR.
D57H
3415
MSR_C2_PMON_CTR3
Package
Uncore C-box 2 perfmon counter MSR.
D58H
3416
MSR_C2_PMON_EVNT_SEL4
Package
Uncore C-box 2 perfmon event select MSR.
D59H
3417
MSR_C2_PMON_CTR4
Package
Uncore C-box 2 perfmon counter MSR.
D5AH
3418
MSR_C2_PMON_EVNT_SEL5
Package
Uncore C-box 2 perfmon event select MSR.
D5BH
3419
MSR_C2_PMON_CTR5
Package
Uncore C-box 2 perfmon counter MSR.
D60H
3424
MSR_C6_PMON_BOX_CTRL
Package
Uncore C-box 6 perfmon local box control MSR.
D61H
3425
MSR_C6_PMON_BOX_STATUS
Package
Uncore C-box 6 perfmon local box status MSR.
D62H
3426
MSR_C6_PMON_BOX_OVF_CTRL
Package
Uncore C-box 6 perfmon local box overflow control
MSR.
D70H
3440
MSR_C6_PMON_EVNT_SEL0
Package
Uncore C-box 6 perfmon event select MSR.
D71H
3441
MSR_C6_PMON_CTR0
Package
Uncore C-box 6 perfmon counter MSR.
D72H
3442
MSR_C6_PMON_EVNT_SEL1
Package
Uncore C-box 6 perfmon event select MSR.
D73H
3443
MSR_C6_PMON_CTR1
Package
Uncore C-box 6 perfmon counter MSR.
D74H
3444
MSR_C6_PMON_EVNT_SEL2
Package
Uncore C-box 6 perfmon event select MSR.
D75H
3445
MSR_C6_PMON_CTR2
Package
Uncore C-box 6 perfmon counter MSR.
D76H
3446
MSR_C6_PMON_EVNT_SEL3
Package
Uncore C-box 6 perfmon event select MSR.
D77H
3447
MSR_C6_PMON_CTR3
Package
Uncore C-box 6 perfmon counter MSR.
D78H
3448
MSR_C6_PMON_EVNT_SEL4
Package
Uncore C-box 6 perfmon event select MSR.
D79H
3449
MSR_C6_PMON_CTR4
Package
Uncore C-box 6 perfmon counter MSR.
D7AH
3450
MSR_C6_PMON_EVNT_SEL5
Package
Uncore C-box 6 perfmon event select MSR.
D7BH
3451
MSR_C6_PMON_CTR5
Package
Uncore C-box 6 perfmon counter MSR.
2-170 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
D80H
3456
MSR_C1_PMON_BOX_CTRL
Package
Uncore C-box 1 perfmon local box control MSR.
D81H
3457
MSR_C1_PMON_BOX_STATUS
Package
Uncore C-box 1 perfmon local box status MSR.
D82H
3458
MSR_C1_PMON_BOX_OVF_CTRL
Package
Uncore C-box 1 perfmon local box overflow control
MSR.
D90H
3472
MSR_C1_PMON_EVNT_SEL0
Package
Uncore C-box 1 perfmon event select MSR.
D91H
3473
MSR_C1_PMON_CTR0
Package
Uncore C-box 1 perfmon counter MSR.
D92H
3474
MSR_C1_PMON_EVNT_SEL1
Package
Uncore C-box 1 perfmon event select MSR.
D93H
3475
MSR_C1_PMON_CTR1
Package
Uncore C-box 1 perfmon counter MSR.
D94H
3476
MSR_C1_PMON_EVNT_SEL2
Package
Uncore C-box 1 perfmon event select MSR.
D95H
3477
MSR_C1_PMON_CTR2
Package
Uncore C-box 1 perfmon counter MSR.
D96H
3478
MSR_C1_PMON_EVNT_SEL3
Package
Uncore C-box 1 perfmon event select MSR.
D97H
3479
MSR_C1_PMON_CTR3
Package
Uncore C-box 1 perfmon counter MSR.
D98H
3480
MSR_C1_PMON_EVNT_SEL4
Package
Uncore C-box 1 perfmon event select MSR.
D99H
3481
MSR_C1_PMON_CTR4
Package
Uncore C-box 1 perfmon counter MSR.
D9AH
3482
MSR_C1_PMON_EVNT_SEL5
Package
Uncore C-box 1 perfmon event select MSR.
D9BH
3483
MSR_C1_PMON_CTR5
Package
Uncore C-box 1 perfmon counter MSR.
DA0H
3488
MSR_C5_PMON_BOX_CTRL
Package
Uncore C-box 5 perfmon local box control MSR.
DA1H
3489
MSR_C5_PMON_BOX_STATUS
Package
Uncore C-box 5 perfmon local box status MSR.
DA2H
3490
MSR_C5_PMON_BOX_OVF_CTRL
Package
Uncore C-box 5 perfmon local box overflow control
MSR.
DB0H
3504
MSR_C5_PMON_EVNT_SEL0
Package
Uncore C-box 5 perfmon event select MSR.
DB1H
3505
MSR_C5_PMON_CTR0
Package
Uncore C-box 5 perfmon counter MSR.
DB2H
3506
MSR_C5_PMON_EVNT_SEL1
Package
Uncore C-box 5 perfmon event select MSR.
DB3H
3507
MSR_C5_PMON_CTR1
Package
Uncore C-box 5 perfmon counter MSR.
DB4H
3508
MSR_C5_PMON_EVNT_SEL2
Package
Uncore C-box 5 perfmon event select MSR.
DB5H
3509
MSR_C5_PMON_CTR2
Package
Uncore C-box 5 perfmon counter MSR.
DB6H
3510
MSR_C5_PMON_EVNT_SEL3
Package
Uncore C-box 5 perfmon event select MSR.
DB7H
3511
MSR_C5_PMON_CTR3
Package
Uncore C-box 5 perfmon counter MSR.
Vol. 4
2-171
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
DB8H
3512
MSR_C5_PMON_EVNT_SEL4
Package
Uncore C-box 5 perfmon event select MSR.
DB9H
3513
MSR_C5_PMON_CTR4
Package
Uncore C-box 5 perfmon counter MSR.
DBAH
3514
MSR_C5_PMON_EVNT_SEL5
Package
Uncore C-box 5 perfmon event select MSR.
DBBH
3515
MSR_C5_PMON_CTR5
Package
Uncore C-box 5 perfmon counter MSR.
DC0H
3520
MSR_C3_PMON_BOX_CTRL
Package
Uncore C-box 3 perfmon local box control MSR.
DC1H
3521
MSR_C3_PMON_BOX_STATUS
Package
Uncore C-box 3 perfmon local box status MSR.
DC2H
3522
MSR_C3_PMON_BOX_OVF_CTRL
Package
Uncore C-box 3 perfmon local box overflow control
MSR.
DD0H
3536
MSR_C3_PMON_EVNT_SEL0
Package
Uncore C-box 3 perfmon event select MSR.
DD1H
3537
MSR_C3_PMON_CTR0
Package
Uncore C-box 3 perfmon counter MSR.
DD2H
3538
MSR_C3_PMON_EVNT_SEL1
Package
Uncore C-box 3 perfmon event select MSR.
DD3H
3539
MSR_C3_PMON_CTR1
Package
Uncore C-box 3 perfmon counter MSR.
DD4H
3540
MSR_C3_PMON_EVNT_SEL2
Package
Uncore C-box 3 perfmon event select MSR.
DD5H
3541
MSR_C3_PMON_CTR2
Package
Uncore C-box 3 perfmon counter MSR.
DD6H
3542
MSR_C3_PMON_EVNT_SEL3
Package
Uncore C-box 3 perfmon event select MSR.
DD7H
3543
MSR_C3_PMON_CTR3
Package
Uncore C-box 3 perfmon counter MSR.
DD8H
3544
MSR_C3_PMON_EVNT_SEL4
Package
Uncore C-box 3 perfmon event select MSR.
DD9H
3545
MSR_C3_PMON_CTR4
Package
Uncore C-box 3 perfmon counter MSR.
DDAH
3546
MSR_C3_PMON_EVNT_SEL5
Package
Uncore C-box 3 perfmon event select MSR.
DDBH
3547
MSR_C3_PMON_CTR5
Package
Uncore C-box 3 perfmon counter MSR.
DE0H
3552
MSR_C7_PMON_BOX_CTRL
Package
Uncore C-box 7 perfmon local box control MSR.
DE1H
3553
MSR_C7_PMON_BOX_STATUS
Package
Uncore C-box 7 perfmon local box status MSR.
DE2H
3554
MSR_C7_PMON_BOX_OVF_CTRL
Package
Uncore C-box 7 perfmon local box overflow control
MSR.
DF0H
3568
MSR_C7_PMON_EVNT_SEL0
Package
Uncore C-box 7 perfmon event select MSR.
DF1H
3569
MSR_C7_PMON_CTR0
Package
Uncore C-box 7 perfmon counter MSR.
DF2H
3570
MSR_C7_PMON_EVNT_SEL1
Package
Uncore C-box 7 perfmon event select MSR.
2-172 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
DF3H
3571
MSR_C7_PMON_CTR1
Package
Uncore C-box 7 perfmon counter MSR.
DF4H
3572
MSR_C7_PMON_EVNT_SEL2
Package
Uncore C-box 7 perfmon event select MSR.
DF5H
3573
MSR_C7_PMON_CTR2
Package
Uncore C-box 7 perfmon counter MSR.
DF6H
3574
MSR_C7_PMON_EVNT_SEL3
Package
Uncore C-box 7 perfmon event select MSR.
DF7H
3575
MSR_C7_PMON_CTR3
Package
Uncore C-box 7 perfmon counter MSR.
DF8H
3576
MSR_C7_PMON_EVNT_SEL4
Package
Uncore C-box 7 perfmon event select MSR.
DF9H
3577
MSR_C7_PMON_CTR4
Package
Uncore C-box 7 perfmon counter MSR.
DFAH
3578
MSR_C7_PMON_EVNT_SEL5
Package
Uncore C-box 7 perfmon event select MSR.
DFBH
3579
MSR_C7_PMON_CTR5
Package
Uncore C-box 7 perfmon counter MSR.
E00H
3584
MSR_R0_PMON_BOX_CTRL
Package
Uncore R-box 0 perfmon local box control MSR.
E01H
3585
MSR_R0_PMON_BOX_STATUS
Package
Uncore R-box 0 perfmon local box status MSR.
E02H
3586
MSR_R0_PMON_BOX_OVF_CTRL
Package
Uncore R-box 0 perfmon local box overflow control
MSR.
E04H
3588
MSR_R0_PMON_IPERF0_P0
Package
Uncore R-box 0 perfmon IPERF0 unit Port 0 select
MSR.
E05H
3589
MSR_R0_PMON_IPERF0_P1
Package
Uncore R-box 0 perfmon IPERF0 unit Port 1 select
MSR.
E06H
3590
MSR_R0_PMON_IPERF0_P2
Package
Uncore R-box 0 perfmon IPERF0 unit Port 2 select
MSR.
E07H
3591
MSR_R0_PMON_IPERF0_P3
Package
Uncore R-box 0 perfmon IPERF0 unit Port 3 select
MSR.
E08H
3592
MSR_R0_PMON_IPERF0_P4
Package
Uncore R-box 0 perfmon IPERF0 unit Port 4 select
MSR.
E09H
3593
MSR_R0_PMON_IPERF0_P5
Package
Uncore R-box 0 perfmon IPERF0 unit Port 5 select
MSR.
E0AH
3594
MSR_R0_PMON_IPERF0_P6
Package
Uncore R-box 0 perfmon IPERF0 unit Port 6 select
MSR.
E0BH
3595
MSR_R0_PMON_IPERF0_P7
Package
Uncore R-box 0 perfmon IPERF0 unit Port 7 select
MSR.
E0CH
3596
MSR_R0_PMON_QLX_P0
Package
Uncore R-box 0 perfmon QLX unit Port 0 select MSR.
E0DH
3597
MSR_R0_PMON_QLX_P1
Package
Uncore R-box 0 perfmon QLX unit Port 1 select MSR.
E0EH
3598
MSR_R0_PMON_QLX_P2
Package
Uncore R-box 0 perfmon QLX unit Port 2 select MSR.
E0FH
3599
MSR_R0_PMON_QLX_P3
Package
Uncore R-box 0 perfmon QLX unit Port 3 select MSR.
E10H
3600
MSR_R0_PMON_EVNT_SEL0
Package
Uncore R-box 0 perfmon event select MSR.
E11H
3601
MSR_R0_PMON_CTR0
Package
Uncore R-box 0 perfmon counter MSR.
Vol. 4
2-173
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
E12H
3602
MSR_R0_PMON_EVNT_SEL1
Package
Uncore R-box 0 perfmon event select MSR.
E13H
3603
MSR_R0_PMON_CTR1
Package
Uncore R-box 0 perfmon counter MSR.
E14H
3604
MSR_R0_PMON_EVNT_SEL2
Package
Uncore R-box 0 perfmon event select MSR.
E15H
3605
MSR_R0_PMON_CTR2
Package
Uncore R-box 0 perfmon counter MSR.
E16H
3606
MSR_R0_PMON_EVNT_SEL3
Package
Uncore R-box 0 perfmon event select MSR.
E17H
3607
MSR_R0_PMON_CTR3
Package
Uncore R-box 0 perfmon counter MSR.
E18H
3608
MSR_R0_PMON_EVNT_SEL4
Package
Uncore R-box 0 perfmon event select MSR.
E19H
3609
MSR_R0_PMON_CTR4
Package
Uncore R-box 0 perfmon counter MSR.
E1AH
3610
MSR_R0_PMON_EVNT_SEL5
Package
Uncore R-box 0 perfmon event select MSR.
E1BH
3611
MSR_R0_PMON_CTR5
Package
Uncore R-box 0 perfmon counter MSR.
E1CH
3612
MSR_R0_PMON_EVNT_SEL6
Package
Uncore R-box 0 perfmon event select MSR.
E1DH
3613
MSR_R0_PMON_CTR6
Package
Uncore R-box 0 perfmon counter MSR.
E1EH
3614
MSR_R0_PMON_EVNT_SEL7
Package
Uncore R-box 0 perfmon event select MSR.
E1FH
3615
MSR_R0_PMON_CTR7
Package
Uncore R-box 0 perfmon counter MSR.
E20H
3616
MSR_R1_PMON_BOX_CTRL
Package
Uncore R-box 1 perfmon local box control MSR.
E21H
3617
MSR_R1_PMON_BOX_STATUS
Package
Uncore R-box 1 perfmon local box status MSR.
E22H
3618
MSR_R1_PMON_BOX_OVF_CTRL
Package
Uncore R-box 1 perfmon local box overflow control
MSR.
E24H
3620
MSR_R1_PMON_IPERF1_P8
Package
Uncore R-box 1 perfmon IPERF1 unit Port 8 select
MSR.
E25H
3621
MSR_R1_PMON_IPERF1_P9
Package
Uncore R-box 1 perfmon IPERF1 unit Port 9 select
MSR.
E26H
3622
MSR_R1_PMON_IPERF1_P10
Package
Uncore R-box 1 perfmon IPERF1 unit Port 10 select
MSR.
E27H
3623
MSR_R1_PMON_IPERF1_P11
Package
Uncore R-box 1 perfmon IPERF1 unit Port 11 select
MSR.
E28H
3624
MSR_R1_PMON_IPERF1_P12
Package
Uncore R-box 1 perfmon IPERF1 unit Port 12 select
MSR.
E29H
3625
MSR_R1_PMON_IPERF1_P13
Package
Uncore R-box 1 perfmon IPERF1 unit Port 13 select
MSR.
E2AH
3626
MSR_R1_PMON_IPERF1_P14
Package
Uncore R-box 1 perfmon IPERF1 unit Port 14 select
MSR.
2-174 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
E2BH
3627
MSR_R1_PMON_IPERF1_P15
Package
Uncore R-box 1 perfmon IPERF1 unit Port 15 select
MSR.
E2CH
3628
MSR_R1_PMON_QLX_P4
Package
Uncore R-box 1 perfmon QLX unit Port 4 select MSR.
E2DH
3629
MSR_R1_PMON_QLX_P5
Package
Uncore R-box 1 perfmon QLX unit Port 5 select MSR.
E2EH
3630
MSR_R1_PMON_QLX_P6
Package
Uncore R-box 1 perfmon QLX unit Port 6 select MSR.
E2FH
3631
MSR_R1_PMON_QLX_P7
Package
Uncore R-box 1 perfmon QLX unit Port 7 select MSR.
E30H
3632
MSR_R1_PMON_EVNT_SEL8
Package
Uncore R-box 1 perfmon event select MSR.
E31H
3633
MSR_R1_PMON_CTR8
Package
Uncore R-box 1 perfmon counter MSR.
E32H
3634
MSR_R1_PMON_EVNT_SEL9
Package
Uncore R-box 1 perfmon event select MSR.
E33H
3635
MSR_R1_PMON_CTR9
Package
Uncore R-box 1 perfmon counter MSR.
E34H
3636
MSR_R1_PMON_EVNT_SEL10
Package
Uncore R-box 1 perfmon event select MSR.
E35H
3637
MSR_R1_PMON_CTR10
Package
Uncore R-box 1 perfmon counter MSR.
E36H
3638
MSR_R1_PMON_EVNT_SEL11
Package
Uncore R-box 1 perfmon event select MSR.
E37H
3639
MSR_R1_PMON_CTR11
Package
Uncore R-box 1 perfmon counter MSR.
E38H
3640
MSR_R1_PMON_EVNT_SEL12
Package
Uncore R-box 1 perfmon event select MSR.
E39H
3641
MSR_R1_PMON_CTR12
Package
Uncore R-box 1 perfmon counter MSR.
E3AH
3642
MSR_R1_PMON_EVNT_SEL13
Package
Uncore R-box 1 perfmon event select MSR.
E3BH
3643
MSR_R1_PMON_CTR13
Package
Uncore R-box 1perfmon counter MSR.
E3CH
3644
MSR_R1_PMON_EVNT_SEL14
Package
Uncore R-box 1 perfmon event select MSR.
E3DH
3645
MSR_R1_PMON_CTR14
Package
Uncore R-box 1 perfmon counter MSR.
E3EH
3646
MSR_R1_PMON_EVNT_SEL15
Package
Uncore R-box 1 perfmon event select MSR.
E3FH
3647
MSR_R1_PMON_CTR15
Package
Uncore R-box 1 perfmon counter MSR.
E45H
3653
MSR_B0_PMON_MATCH
Package
Uncore B-box 0 perfmon local box match MSR.
E46H
3654
MSR_B0_PMON_MASK
Package
Uncore B-box 0 perfmon local box mask MSR.
E49H
3657
MSR_S0_PMON_MATCH
Package
Uncore S-box 0 perfmon local box match MSR.
E4AH
3658
MSR_S0_PMON_MASK
Package
Uncore S-box 0 perfmon local box mask MSR.
E4DH
3661
MSR_B1_PMON_MATCH
Package
Uncore B-box 1 perfmon local box match MSR.
E4EH
3662
MSR_B1_PMON_MASK
Package
Uncore B-box 1 perfmon local box mask MSR.
E54H
3668
MSR_M0_PMON_MM_CONFIG
Package
Uncore M-box 0 perfmon local box address
match/mask config MSR.
Vol. 4
2-175
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
E55H
3669
MSR_M0_PMON_ADDR_MATCH
Package
Uncore M-box 0 perfmon local box address match
MSR.
E56H
3670
MSR_M0_PMON_ADDR_MASK
Package
Uncore M-box 0 perfmon local box address mask
MSR.
E59H
3673
MSR_S1_PMON_MATCH
Package
Uncore S-box 1 perfmon local box match MSR.
E5AH
3674
MSR_S1_PMON_MASK
Package
Uncore S-box 1 perfmon local box mask MSR.
E5CH
3676
MSR_M1_PMON_MM_CONFIG
Package
Uncore M-box 1 perfmon local box address
match/mask config MSR.
E5DH
3677
MSR_M1_PMON_ADDR_MATCH
Package
Uncore M-box 1 perfmon local box address match
MSR.
E5EH
3678
MSR_M1_PMON_ADDR_MASK
Package
Uncore M-box 1 perfmon local box address mask
MSR.
3B5H
965
MSR_UNCORE_PMC5
Package
See Section 20.3.1.2.2, “Uncore Performance Event
Configuration Facility.”
2.9
MSRS IN THE INTEL® XEON® PROCESSOR 5600 SERIES BASED ON
WESTMERE MICROARCHITECTURE
The Intel® Xeon® Processor 5600 Series is based on Westmere microarchitecture and supports the MSR interfaces
listed in Table 2-15, Table 2-16, plus additional MSRs listed in Table 2-18. These MSRs apply to the Intel Core i7, i5,
and i3 processor family with a CPUID Signature DisplayFamily_DisplayModel value of 06_25H or 06_2CH; see Table
2-1.
Table 2-18. Additional MSRs Supported by Intel® Processors Based on Westmere Microarchitecture
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
13CH
316
MSR_FEATURE_CONFIG
Core
AES Configuration (RW-L)
Privileged post-BIOS agent must provide a #GP handler
to handle unsuccessful read of this MSR.
1:0
AES Configuration (RW-L)
Upon a successful read of this MSR, the configuration
of AES instruction set availability is as follows:
11b: AES instructions are not available until next
RESET.
Otherwise, AES instructions are available.
Note, AES instruction set is not available if read is
unsuccessful. If the configuration is not 01b, AES
instructions can be mis-configured if a privileged agent
unintentionally writes 11b.
63:2
Reserved
1A7H
423
MSR_OFFCORE_RSP_1
Thread
Offcore Response Event Select Register (R/W)
2-176 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-18. Additional MSRs Supported by Intel® Processors Based on Westmere Microarchitecture
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
1ADH
429
MSR_TURBO_RATIO_LIMIT
Package
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0.
R/W if MSR_PLATFORM_INFO.[28] = 1.
7:0
Package
Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8
Package
Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
23:16
Package
Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24
Package
Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
39:32
Package
Maximum Ratio Limit for 5C
Maximum turbo ratio limit of 5 core active.
47:40
Package
Maximum Ratio Limit for 6C
Maximum turbo ratio limit of 6 core active.
63:48
Reserved
1B0H
432
IA32_ENERGY_PERF_BIAS
Package
See Table 2-2.
2.10
MSRS IN THE INTEL® XEON® PROCESSOR E7 FAMILY BASED ON WESTMERE
MICROARCHITECTURE
The Intel® Xeon® Processor E7 Family is based on the Westmere microarchitecture and supports the MSR inter-
faces listed in Table 2-15 (except MSR address 1ADH), Table 2-16, plus additional MSRs listed in Table 2-19. These
processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_2FH.
Table 2-19. Additional MSRs Supported by the Intel® Xeon® Processor E7 Family
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
13CH
316
MSR_FEATURE_CONFIG
Core
AES Configuration (RW-L)
Privileged post-BIOS agent must provide a #GP handler
to handle unsuccessful read of this MSR.
1:0
AES Configuration (RW-L)
Upon a successful read of this MSR, the configuration of
AES instruction set availability is as follows:
11b: AES instructions are not available until next RESET.
Otherwise, AES instructions are available.
Note, AES instruction set is not available if read is
unsuccessful. If the configuration is not 01b, AES
instructions can be mis-configured if a privileged agent
unintentionally writes 11b.
Vol. 4
2-177
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-19. Additional MSRs Supported by the Intel® Xeon® Processor E7 Family (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
63:2
Reserved
1A7H
423
MSR_OFFCORE_RSP_1
Thread
Offcore Response Event Select Register (R/W)
1ADH
429
MSR_TURBO_RATIO_LIMIT
Package
Reserved
Attempt to read/write will cause #UD.
1B0H
432
IA32_ENERGY_PERF_BIAS
Package
See Table 2-2.
F40H
3904
MSR_C8_PMON_BOX_CTRL
Package
Uncore C-box 8 perfmon local box control MSR.
F41H
3905
MSR_C8_PMON_BOX_STATUS
Package
Uncore C-box 8 perfmon local box status MSR.
F42H
3906
MSR_C8_PMON_BOX_OVF_CTRL
Package
Uncore C-box 8 perfmon local box overflow control MSR.
F50H
3920
MSR_C8_PMON_EVNT_SEL0
Package
Uncore C-box 8 perfmon event select MSR.
F51H
3921
MSR_C8_PMON_CTR0
Package
Uncore C-box 8 perfmon counter MSR.
F52H
3922
MSR_C8_PMON_EVNT_SEL1
Package
Uncore C-box 8 perfmon event select MSR.
F53H
3923
MSR_C8_PMON_CTR1
Package
Uncore C-box 8 perfmon counter MSR.
F54H
3924
MSR_C8_PMON_EVNT_SEL2
Package
Uncore C-box 8 perfmon event select MSR.
F55H
3925
MSR_C8_PMON_CTR2
Package
Uncore C-box 8 perfmon counter MSR.
F56H
3926
MSR_C8_PMON_EVNT_SEL3
Package
Uncore C-box 8 perfmon event select MSR.
F57H
3927
MSR_C8_PMON_CTR3
Package
Uncore C-box 8 perfmon counter MSR.
F58H
3928
MSR_C8_PMON_EVNT_SEL4
Package
Uncore C-box 8 perfmon event select MSR.
F59H
3929
MSR_C8_PMON_CTR4
Package
Uncore C-box 8 perfmon counter MSR.
F5AH
3930
MSR_C8_PMON_EVNT_SEL5
Package
Uncore C-box 8 perfmon event select MSR.
F5BH
3931
MSR_C8_PMON_CTR5
Package
Uncore C-box 8 perfmon counter MSR.
FC0H
4032
MSR_C9_PMON_BOX_CTRL
Package
Uncore C-box 9 perfmon local box control MSR.
FC1H
4033
MSR_C9_PMON_BOX_STATUS
Package
Uncore C-box 9 perfmon local box status MSR.
FC2H
4034
MSR_C9_PMON_BOX_OVF_CTRL
Package
Uncore C-box 9 perfmon local box overflow control MSR.
FD0H
4048
MSR_C9_PMON_EVNT_SEL0
Package
Uncore C-box 9 perfmon event select MSR.
FD1H
4049
MSR_C9_PMON_CTR0
Package
Uncore C-box 9 perfmon counter MSR.
FD2H
4050
MSR_C9_PMON_EVNT_SEL1
Package
Uncore C-box 9 perfmon event select MSR.
FD3H
4051
MSR_C9_PMON_CTR1
Package
Uncore C-box 9 perfmon counter MSR.
2-178 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-19. Additional MSRs Supported by the Intel® Xeon® Processor E7 Family (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
FD4H
4052
MSR_C9_PMON_EVNT_SEL2
Package
Uncore C-box 9 perfmon event select MSR.
FD5H
4053
MSR_C9_PMON_CTR2
Package
Uncore C-box 9 perfmon counter MSR.
FD6H
4054
MSR_C9_PMON_EVNT_SEL3
Package
Uncore C-box 9 perfmon event select MSR.
FD7H
4055
MSR_C9_PMON_CTR3
Package
Uncore C-box 9 perfmon counter MSR.
FD8H
4056
MSR_C9_PMON_EVNT_SEL4
Package
Uncore C-box 9 perfmon event select MSR.
FD9H
4057
MSR_C9_PMON_CTR4
Package
Uncore C-box 9 perfmon counter MSR.
FDAH
4058
MSR_C9_PMON_EVNT_SEL5
Package
Uncore C-box 9 perfmon event select MSR.
FDBH
4059
MSR_C9_PMON_CTR5
Package
Uncore C-box 9 perfmon counter MSR.
2.11
MSRS IN THE INTEL® PROCESSOR FAMILY BASED ON SANDY BRIDGE
MICROARCHITECTURE
Table 2-20 lists model-specific registers (MSRs) that are common to the Intel® processor family based on Sandy
Bridge microarchitecture. These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_2AH
or 06_2DH; see Table 2-1. Additional MSRs specific to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_2AH are listed in Table 2-21.
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
0H
0
IA32_P5_MC_ADDR
Thread
See Section 2.23, “MSRs in Pentium Processors.”
1H
1
IA32_P5_MC_TYPE
Thread
See Section 2.23, “MSRs in Pentium Processors.”
6H
6
IA32_MONITOR_FILTER_
Thread
See Section 9.10.5, “Monitor/Mwait Address Range
SIZE
Determination,” and Table 2-2.
10H
16
IA32_TIME_STAMP_COUNTER
Thread
See Section 18.17, “Time-Stamp Counter,” and see
Table 2-2.
17H
23
IA32_PLATFORM_ID
Package
Platform ID (R)
See Table 2-2.
1BH
27
IA32_APIC_BASE
Thread
See Section 11.4.4, “Local APIC Status and Location,”
and Table 2-2.
34H
52
MSR_SMI_COUNT
Thread
SMI Counter (R/O)
31:0
SMI Count (R/O)
Count SMIs.
63:32
Reserved.
Vol. 4
2-179
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
3AH
58
IA32_FEATURE_CONTROL
Thread
Control Features in Intel 64 Processor (R/W)
See Table 2-2.
0
Lock (R/WL)
1
Enable VMX Inside SMX Operation (R/WL)
2
Enable VMX Outside SMX Operation (R/WL)
14:8
SENTER Local Functions Enables (R/WL)
15
SENTER Global Functions Enable (R/WL)
79H
121
IA32_BIOS_UPDT_TRIG
Core
BIOS Update Trigger Register (W)
See Table 2-2.
8BH
139
IA32_BIOS_SIGN_ID
Thread
BIOS Update Signature ID (R/W)
See Table 2-2.
C1H
193
IA32_PMC0
Thread
Performance Counter Register
See Table 2-2.
C2H
194
IA32_PMC1
Thread
Performance Counter Register
See Table 2-2.
C3H
195
IA32_PMC2
Thread
Performance Counter Register
See Table 2-2.
C4H
196
IA32_PMC3
Thread
Performance Counter Register
See Table 2-2.
C5H
197
IA32_PMC4
Core
Performance Counter Register (if core not shared by
threads)
C6H
198
IA32_PMC5
Core
Performance Counter Register (if core not shared by
threads)
C7H
199
IA32_PMC6
Core
Performance Counter Register (if core not shared by
threads)
C8H
200
IA32_PMC7
Core
Performance Counter Register (if core not shared by
threads)
CEH
206
MSR_PLATFORM_INFO
Package
Platform Information
Contains power management and other model specific
features enumeration. See http://biosbits.org.
7:0
Reserved
15:8
Package
Maximum Non-Turbo Ratio (R/O)
This is the ratio of the frequency that invariant TSC
runs at. Frequency = ratio * 100 MHz.
27:16
Reserved
28
Package
Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limit
for Turbo mode is enabled. When set to 0, indicates
Programmable Ratio Limit for Turbo mode is disabled.
2-180 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
29
Package
Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limit for Turbo mode
is programmable. When set to 0, indicates TDP Limit for
Turbo mode is not programmable.
39:30
Reserved
47:40
Package
Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that
the processor can operate, in units of 100MHz.
63:48
Reserved
E2H
226
MSR_PKG_CST_CONFIG_CONTROL
Core
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
See http://biosbits.org.
2:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code
name (consuming the least power) for the package. The
default is set as factory-configured package C-state
limit.
The following C-state code name encodings are
supported:
000b: C0/C1 (no package C-sate support)
001b: C2
010b: C6 no retention
011b: C6 retention
100b: C7
101b: C7s
111: No package C-state limit
Note: This field cannot be used to limit package C-state
to C3.
9:3
Reserved
10
I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO
register specified by MSR_PMG_IO_CAPTURE_BASE to
MWAIT instructions.
14:11
Reserved
15
CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next
reset.
24:16
Reserved
25
C3 State Auto Demotion Enable (R/W)
When set, the processor will conditionally demote
C6/C7 requests to C3 based on uncore auto-demote
information.
Vol. 4
2-181
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
26
C1 State Auto Demotion Enable (R/W)
When set, the processor will conditionally demote
C3/C6/C7 requests to C1 based on uncore auto-demote
information.
27
Enable C3 Undemotion (R/W)
When set, enables undemotion from demoted C3.
28
Enable C1 Undemotion (R/W)
When set, enables undemotion from demoted C1.
63:29
Reserved
E4H
228
MSR_PMG_IO_CAPTURE_BASE
Core
Power Management IO Redirection in C-state (R/W)
See http://biosbits.org.
15:0
LVL_2 Base Address (R/W)
Specifies the base address visible to software for IO
redirection. If IO MWAIT Redirection is enabled, reads to
this address will be consumed by the power
management logic and decoded to MWAIT instructions.
When IO port address redirection is enabled, this is the
IO port address reported to the OS/software.
18:16
C-State Range (R/W)
Specifies the encoding value of the maximum C-State
code name to be included when IO read to MWAIT
redirection is enabled by
MSR_PKG_CST_CONFIG_CONTROL[bit10]:
000b - C3 is the max C-State to include.
001b - C6 is the max C-State to include.
010b - C7 is the max C-State to include.
63:19
Reserved
E7H
231
IA32_MPERF
Thread
Maximum Performance Frequency Clock Count (R/W)
See Table 2-2.
E8H
232
IA32_APERF
Thread
Actual Performance Frequency Clock Count (R/W)
See Table 2-2.
FEH
254
IA32_MTRRCAP
Thread
See Table 2-2.
13CH
316
MSR_FEATURE_CONFIG
Core
AES Configuration (RW-L)
Privileged post-BIOS agent must provide a #GP handler
to handle unsuccessful read of this MSR.
2-182 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
1:0
AES Configuration (RW-L)
Upon a successful read of this MSR, the configuration
of AES instruction set availability is as follows:
11b: AES instructions are not available until next
RESET.
Otherwise, AES instructions are available.
Note, AES instruction set is not available if read is
unsuccessful. If the configuration is not 01b, AES
instructions can be mis-configured if a privileged agent
unintentionally writes 11b.
63:2
Reserved
174H
372
IA32_SYSENTER_CS
Thread
See Table 2-2.
175H
373
IA32_SYSENTER_ESP
Thread
See Table 2-2.
176H
374
IA32_SYSENTER_EIP
Thread
See Table 2-2.
179H
377
IA32_MCG_CAP
Thread
See Table 2-2.
17AH
378
IA32_MCG_STATUS
Thread
Global Machine Check Status
0
RIPV
When set, bit indicates that the instruction addressed
by the instruction pointer pushed on the stack (when
the machine check was generated) can be used to
restart the program. If cleared, the program cannot be
reliably restarted.
1
EIPV
When set, bit indicates that the instruction addressed
by the instruction pointer pushed on the stack (when
the machine check was generated) is directly
associated with the error.
2
MCIP
When set, bit indicates that a machine check has been
generated. If a second machine check is detected while
this bit is still set, the processor enters a shutdown
state. Software should write this bit to 0 after
processing a machine check exception.
63:3
Reserved
186H
390
IA32_PERFEVTSEL0
Thread
See Table 2-2.
187H
391
IA32_PERFEVTSEL1
Thread
See Table 2-2.
188H
392
IA32_PERFEVTSEL2
Thread
See Table 2-2.
189H
393
IA32_PERFEVTSEL3
Thread
See Table 2-2.
18AH
394
IA32_PERFEVTSEL4
Core
See Table 2-2. If CPUID.0AH:EAX[15:8] > 4.
18BH
395
IA32_PERFEVTSEL5
Core
See Table 2-2. If CPUID.0AH:EAX[15:8] > 5.
18CH
396
IA32_PERFEVTSEL6
Core
See Table 2-2. If CPUID.0AH:EAX[15:8] > 6.
18DH
397
IA32_PERFEVTSEL7
Core
See Table 2-2. If CPUID.0AH:EAX[15:8] > 7.
198H
408
IA32_PERF_STATUS
Package
See Table 2-2.
Vol. 4
2-183
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
15:0
Current Performance State Value
63:16
Reserved
198H
408
MSR_PERF_STATUS
Package
Performance Status
47:32
Core Voltage (R/O)
P-state core voltage can be computed by
MSR_PERF_STATUS[37:32] * (float) 1/(2^13).
199H
409
IA32_PERF_CTL
Thread
See Table 2-2.
19AH
410
IA32_CLOCK_MODULATION
Thread
Clock Modulation (R/W)
See Table 2-2.
IA32_CLOCK_MODULATION MSR was originally named
IA32_THERM_CONTROL MSR.
3:0
On demand Clock Modulation Duty Cycle (R/W)
In 6.25% increment.
4
On demand Clock Modulation Enable (R/W)
63:5
Reserved
19BH
411
IA32_THERM_INTERRUPT
Core
Thermal Interrupt Control (R/W)
See Table 2-2.
19CH
412
IA32_THERM_STATUS
Core
Thermal Monitor Status (R/W)
See Table 2-2.
0
Thermal Status (R/O)
See Table 2-2.
1
Thermal Status Log (R/WC0)
See Table 2-2.
2
PROTCHOT # or FORCEPR# Status (R/O)
See Table 2-2.
3
PROTCHOT # or FORCEPR# Log (R/WC0)
See Table 2-2.
4
Critical Temperature Status (R/O)
See Table 2-2.
5
Critical Temperature Status Log (R/WC0)
See Table 2-2.
6
Thermal Threshold #1 Status (R/O)
See Table 2-2.
7
Thermal Threshold #1 Log (R/WC0)
See Table 2-2.
8
Thermal Threshold #2 Status (R/O)
See Table 2-2.
9
Thermal Threshold #2 Log (R/WC0)
See Table 2-2.
2-184 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
10
Power Limitation Status (R/O)
See Table 2-2.
11
Power Limitation Log (R/WC0)
See Table 2-2.
15:12
Reserved
22:16
Digital Readout (R/O)
See Table 2-2.
26:23
Reserved
30:27
Resolution in Degrees Celsius (R/O)
See Table 2-2.
31
Reading Valid (R/O)
See Table 2-2.
63:32
Reserved
1A0H
416
IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled
and disabled.
0
Thread
Fast-Strings Enable
See Table 2-2
6:1
Reserved
7
Thread
Performance Monitoring Available (R)
See Table 2-2.
10:8
Reserved
11
Thread
Branch Trace Storage Unavailable (R/O)
See Table 2-2.
12
Thread
Processor Event Based Sampling Unavailable (R/O)
See Table 2-2.
15:13
Reserved
16
Package
Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 2-2.
18
Thread
ENABLE MONITOR FSM (R/W)
See Table 2-2.
21:19
Reserved
22
Thread
Limit CPUID Maxval (R/W)
See Table 2-2.
23
Thread
xTPR Message Disable (R/W)
See Table 2-2.
33:24
Reserved
34
Thread
XD Bit Disable (R/W)
See Table 2-3.
Vol. 4
2-185
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
37:35
Reserved
38
Package
Turbo Mode Disable (R/W)
When set to 1 on processors that support Intel Turbo
Boost Technology, the turbo mode feature is disabled
and the IDA_Enable feature flag will be clear
(CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA,
CPUID.06H: EAX[1] reports the processor’s support of
turbo mode is enabled.
Note: The power-on default value is used by BIOS to
detect hardware support of turbo mode. If the power-
on default value is 1, turbo mode is available in the
processor. If the power-on default value is 0, turbo
mode is not available.
63:39
Reserved
1A2H
418
MSR_TEMPERATURE_TARGET
Unique
Temperature Target
15:0
Reserved
23:16
Temperature Target (R)
The minimum temperature at which PROCHOT# will be
asserted. The value is degrees C.
63:24
Reserved
1A4H
420
MSR_MISC_FEATURE_CONTROL
Miscellaneous Feature Control (R/W)
0
Core
L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher, which
fetches additional lines of code or data into the L2
cache.
1
Core
L2 Adjacent Cache Line Prefetcher Disable (R/W)
If 1, disables the adjacent cache line prefetcher, which
fetches the cache line that comprises a cache line pair
(128 bytes).
2
Core
DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher, which
fetches the next cache line into L1 data cache.
3
Core
DCU IP Prefetcher Disable (R/W)
If 1, disables the L1 data cache IP prefetcher, which
uses sequential load history (based on instruction
pointer of previous loads) to determine whether to
prefetch additional lines.
63:4
Reserved
1A6H
422
MSR_OFFCORE_RSP_0
Thread
Offcore Response Event Select Register (R/W)
1A7H
423
MSR_OFFCORE_RSP_1
Thread
Offcore Response Event Select Register (R/W)
1AAH
426
MSR_MISC_PWR_MGMT
Miscellaneous Power Management Control
Various model specific features enumeration. See
http://biosbits.org.
2-186 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
1B0H
432
IA32_ENERGY_PERF_BIAS
Package
See Table 2-2.
1B1H
433
IA32_PACKAGE_THERM_STATUS
Package
See Table 2-2.
1B2H
434
IA32_PACKAGE_THERM_INTERRUPT
Package
See Table 2-2.
1C8H
456
MSR_LBR_SELECT
Thread
Last Branch Record Filtering Select Register (R/W)
See Section 18.9.2, “Filtering of Last Branch Records.”
0
CPL_EQ_0
1
CPL_NEQ_0
2
JCC
3
NEAR_REL_CALL
4
NEAR_IND_CALL
5
NEAR_RET
6
NEAR_IND_JMP
7
NEAR_REL_JMP
8
FAR_BRANCH
63:9
Reserved
1C9H
457
MSR_LASTBRANCH_TOS
Thread
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-3) that points to the MSR
containing the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP (at 680H).
1D9H
473
IA32_DEBUGCTL
Thread
Debug Control (R/W)
See Table 2-2.
0
LBR: Last Branch Record
1
BTF
5:2
Reserved
6
TR: Branch Trace
7
BTS: Log Branch Trace Message to BTS buffer
8
BTINT
9
BTS_OFF_OS
10
BTS_OFF_USER
11
FREEZE_LBR_ON_PMI
12
FREEZE_PERFMON_ON_PMI
13
ENABLE_UNCORE_PMI
14
FREEZE_WHILE_SMM
63:15
Reserved
1DDH
477
MSR_LER_FROM_LIP
Thread
Last Exception Record From Linear IP (R/W)
Contains a pointer to the last branch instruction that
the processor executed prior to the last exception that
was generated or the last interrupt that was handled.
Vol. 4
2-187
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
1DEH
478
MSR_LER_TO_LIP
Thread
Last Exception Record To Linear IP (R/W)
This area contains a pointer to the target of the last
branch instruction that the processor executed prior to
the last exception that was generated or the last
interrupt that was handled.
1F2H
498
IA32_SMRR_PHYSBASE
Core
See Table 2-2.
1F3H
499
IA32_SMRR_PHYSMASK
Core
See Table 2-2.
1FCH
508
MSR_POWER_CTL
Core
See http://biosbits.org.
200H
512
IA32_MTRR_PHYSBASE0
Thread
See Table 2-2.
201H
513
IA32_MTRR_PHYSMASK0
Thread
See Table 2-2.
202H
514
IA32_MTRR_PHYSBASE1
Thread
See Table 2-2.
203H
515
IA32_MTRR_PHYSMASK1
Thread
See Table 2-2.
204H
516
IA32_MTRR_PHYSBASE2
Thread
See Table 2-2.
205H
517
IA32_MTRR_PHYSMASK2
Thread
See Table 2-2.
206H
518
IA32_MTRR_PHYSBASE3
Thread
See Table 2-2.
207H
519
IA32_MTRR_PHYSMASK3
Thread
See Table 2-2.
208H
520
IA32_MTRR_PHYSBASE4
Thread
See Table 2-2.
209H
521
IA32_MTRR_PHYSMASK4
Thread
See Table 2-2.
20AH
522
IA32_MTRR_PHYSBASE5
Thread
See Table 2-2.
20BH
523
IA32_MTRR_PHYSMASK5
Thread
See Table 2-2.
20CH
524
IA32_MTRR_PHYSBASE6
Thread
See Table 2-2.
20DH
525
IA32_MTRR_PHYSMASK6
Thread
See Table 2-2.
20EH
526
IA32_MTRR_PHYSBASE7
Thread
See Table 2-2.
20FH
527
IA32_MTRR_PHYSMASK7
Thread
See Table 2-2.
210H
528
IA32_MTRR_PHYSBASE8
Thread
See Table 2-2.
211H
529
IA32_MTRR_PHYSMASK8
Thread
See Table 2-2.
212H
530
IA32_MTRR_PHYSBASE9
Thread
See Table 2-2.
213H
531
IA32_MTRR_PHYSMASK9
Thread
See Table 2-2.
250H
592
IA32_MTRR_FIX64K_00000
Thread
See Table 2-2.
258H
600
IA32_MTRR_FIX16K_80000
Thread
See Table 2-2.
259H
601
IA32_MTRR_FIX16K_A0000
Thread
See Table 2-2.
268H
616
IA32_MTRR_FIX4K_C0000
Thread
See Table 2-2.
269H
617
IA32_MTRR_FIX4K_C8000
Thread
See Table 2-2.
26AH
618
IA32_MTRR_FIX4K_D0000
Thread
See Table 2-2.
26BH
619
IA32_MTRR_FIX4K_D8000
Thread
See Table 2-2.
26CH
620
IA32_MTRR_FIX4K_E0000
Thread
See Table 2-2.
2-188 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
26DH
621
IA32_MTRR_FIX4K_E8000
Thread
See Table 2-2.
26EH
622
IA32_MTRR_FIX4K_F0000
Thread
See Table 2-2.
26FH
623
IA32_MTRR_FIX4K_F8000
Thread
See Table 2-2.
277H
631
IA32_PAT
Thread
See Table 2-2.
280H
640
IA32_MC0_CTL2
Core
See Table 2-2.
281H
641
IA32_MC1_CTL2
Core
See Table 2-2.
282H
642
IA32_MC2_CTL2
Core
See Table 2-2.
283H
643
IA32_MC3_CTL2
Core
See Table 2-2.
284H
644
IA32_MC4_CTL2
Package
Always 0 (CMCI not supported).
2FFH
767
IA32_MTRR_DEF_TYPE
Thread
Default Memory Types (R/W)
See Table 2-2.
309H
777
IA32_FIXED_CTR0
Thread
Fixed-Function Performance Counter Register 0 (R/W)
See Table 2-2.
30AH
778
IA32_FIXED_CTR1
Thread
Fixed-Function Performance Counter Register 1 (R/W)
See Table 2-2.
30BH
779
IA32_FIXED_CTR2
Thread
Fixed-Function Performance Counter Register 2 (R/W)
See Table 2-2.
345H
837
IA32_PERF_CAPABILITIES
Thread
See Table 2-2. See Section 18.4.1, “IA32_DEBUGCTL
MSR.”
5:0
LBR Format
See Table 2-2.
6
PEBS Record Format.
7
PEBSSaveArchRegs
See Table 2-2.
11:8
PEBS_REC_FORMAT
See Table 2-2.
12
SMM_FREEZE
See Table 2-2.
63:13
Reserved
38DH
909
IA32_FIXED_CTR_CTRL
Thread
Fixed-Function-Counter Control Register (R/W)
See Table 2-2.
38EH
910
IA32_PERF_GLOBAL_STATUS
See Table 2-2. See Section 20.6.2.2, “Global Counter
Control Facilities.”
0
Thread
Ovf_PMC0
1
Thread
Ovf_PMC1
2
Thread
Ovf_PMC2
3
Thread
Ovf_PMC3
4
Core
Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4)
Vol. 4
2-189
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
5
Core
Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5)
6
Core
Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6)
7
Core
Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7)
31:8
Reserved
32
Thread
Ovf_FixedCtr0
33
Thread
Ovf_FixedCtr1
34
Thread
Ovf_FixedCtr2
60:35
Reserved
61
Thread
Ovf_Uncore
62
Thread
Ovf_BufDSSAVE
63
Thread
CondChgd
38FH
911
IA32_PERF_GLOBAL_CTRL
Thread
See Table 2-2. See Section 20.6.2.2, “Global Counter
Control Facilities.”
0
Thread
Set 1 to enable PMC0 to count.
1
Thread
Set 1 to enable PMC1 to count.
2
Thread
Set 1 to enable PMC2 to count.
3
Thread
Set 1 to enable PMC3 to count.
4
Core
Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8]
> 4).
5
Core
Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8]
> 5).
6
Core
Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8]
> 6).
7
Core
Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8]
> 7).
31:8
Reserved
32
Thread
Set 1 to enable FixedCtr0 to count.
33
Thread
Set 1 to enable FixedCtr1 to count.
34
Thread
Set 1 to enable FixedCtr2 to count.
63:35
Reserved
390H
912
IA32_PERF_GLOBAL_OVF_CTRL
See Table 2-2. See Section 20.6.2.2, “Global Counter
Control Facilities.”
0
Thread
Set 1 to clear Ovf_PMC0.
1
Thread
Set 1 to clear Ovf_PMC1.
2
Thread
Set 1 to clear Ovf_PMC2.
3
Thread
Set 1 to clear Ovf_PMC3.
4
Core
Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
5
Core
Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
6
Core
Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
2-190 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
7
Core
Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
31:8
Reserved
32
Thread
Set 1 to clear Ovf_FixedCtr0.
33
Thread
Set 1 to clear Ovf_FixedCtr1.
34
Thread
Set 1 to clear Ovf_FixedCtr2.
60:35
Reserved
61
Thread
Set 1 to clear Ovf_Uncore.
62
Thread
Set 1 to clear Ovf_BufDSSAVE.
63
Thread
Set 1 to clear CondChgd.
3F1H
1009
IA32_PEBS_ENABLE
Thread
See Section 20.3.1.1.1, “Processor Event Based
Sampling (PEBS).”
(MSR_PEBS_ENABLE)
0
Enable PEBS on IA32_PMC0. (R/W)
1
Enable PEBS on IA32_PMC1. (R/W)
2
Enable PEBS on IA32_PMC2. (R/W)
3
Enable PEBS on IA32_PMC3. (R/W)
31:4
Reserved
32
Enable Load Latency on IA32_PMC0. (R/W)
33
Enable Load Latency on IA32_PMC1. (R/W)
34
Enable Load Latency on IA32_PMC2. (R/W)
35
Enable Load Latency on IA32_PMC3. (R/W)
62:36
Reserved
63
Enable Precise Store (R/W)
3F6H
1014
MSR_PEBS_LD_LAT
Thread
See Section 20.3.1.1.2, “Load Latency Performance
Monitoring Facility.”
15:0
Minimum threshold latency value of tagged load
operation that will be counted. (R/W)
63:36
Reserved
3F8H
1016
MSR_PKG_C3_RESIDENCY
Package
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0
Package C3 Residency Counter (R/O)
Value since last reset that this package is in processor-
specific C3 states. Count at the same frequency as the
TSC.
3F9H
1017
MSR_PKG_C6_RESIDENCY
Package
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
Vol. 4
2-191
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
63:0
Package C6 Residency Counter. (R/O)
Value since last reset that this package is in processor-
specific C6 states. Count at the same frequency as the
TSC.
3FAH
1018
MSR_PKG_C7_RESIDENCY
Package
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0
Package C7 Residency Counter (R/O)
Value since last reset that this package is in processor-
specific C7 states. Count at the same frequency as the
TSC.
3FCH
1020
MSR_CORE_C3_RESIDENCY
Core
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0
CORE C3 Residency Counter (R/O)
Value since last reset that this core is in processor-
specific C3 states. Count at the same frequency as the
TSC.
3FDH
1021
MSR_CORE_C6_RESIDENCY
Core
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0
CORE C6 Residency Counter (R/O)
Value since last reset that this core is in processor-
specific C6 states. Count at the same frequency as the
TSC.
3FEH
1022
MSR_CORE_C7_RESIDENCY
Core
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0
CORE C7 Residency Counter (R/O)
Value since last reset that this core is in processor-
specific C7 states. Count at the same frequency as the
TSC.
400H
1024
IA32_MC0_CTL
Core
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
401H
1025
IA32_MC0_STATUS
Core
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
402H
1026
IA32_MC0_ADDR
Core
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
403H
1027
IA32_MC0_MISC
Core
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
404H
1028
IA32_MC1_CTL
Core
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
405H
1029
IA32_MC1_STATUS
Core
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
406H
1030
IA32_MC1_ADDR
Core
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
407H
1031
IA32_MC1_MISC
Core
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
408H
1032
IA32_MC2_CTL
Core
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
2-192 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
409H
1033
IA32_MC2_STATUS
Core
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
40AH
1034
IA32_MC2_ADDR
Core
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
40BH
1035
IA32_MC2_MISC
Core
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
40CH
1036
IA32_MC3_CTL
Core
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
40DH
1037
IA32_MC3_STATUS
Core
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
40EH
1038
IA32_MC3_ADDR
Core
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
40FH
1039
IA32_MC3_MISC
Core
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
410H
1040
IA32_MC4_CTL
Core
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
0
PCU Hardware Error (R/W)
When set, enables signaling of PCU hardware detected
errors.
1
PCU Controller Error (R/W)
When set, enables signaling of PCU controller detected
errors.
2
PCU Firmware Error (R/W)
When set, enables signaling of PCU firmware detected
errors.
63:2
Reserved
411H
1041
IA32_MC4_STATUS
Core
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
480H
1152
IA32_VMX_BASIC
Thread
Reporting Register of Basic VMX Capabilities (R/O)
See Table 2-2.
See Appendix A.1, “Basic VMX Information.”
481H
1153
IA32_VMX_PINBASED_CTLS
Thread
Capability Reporting Register of Pin-Based
VM-Execution Controls (R/O)
See Table 2-2.
See Appendix A.3, “VM-Execution Controls.”
482H
1154
IA32_VMX_PROCBASED_CTLS
Thread
Capability Reporting Register of Primary Processor-
Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
483H
1155
IA32_VMX_EXIT_CTLS
Thread
Capability Reporting Register of VM-Exit Controls (R/O)
See Table 2-2.
See Appendix A.4, “VM-Exit Controls.”
484H
1156
IA32_VMX_ENTRY_CTLS
Thread
Capability Reporting Register of VM-Entry Controls
(R/O)
See Table 2-2.
See Appendix A.5, “VM-Entry Controls.”
Vol. 4
2-193
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
485H
1157
IA32_VMX_MISC
Thread
Reporting Register of Miscellaneous VMX Capabilities
(R/O)
See Table 2-2.
See Appendix A.6, “Miscellaneous Data.”
486H
1158
IA32_VMX_CR0_FIXED0
Thread
Capability Reporting Register of CR0 Bits Fixed to 0
(R/O)
See Table 2-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
487H
1159
IA32_VMX_CR0_FIXED1
Thread
Capability Reporting Register of CR0 Bits Fixed to 1
(R/O)
See Table 2-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
488H
1160
IA32_VMX_CR4_FIXED0
Thread
Capability Reporting Register of CR4 Bits Fixed to 0
(R/O)
See Table 2-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
489H
1161
IA32_VMX_CR4_FIXED1
Thread
Capability Reporting Register of CR4 Bits Fixed to 1
(R/O)
See Table 2-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
48AH
1162
IA32_VMX_VMCS_ENUM
Thread
Capability Reporting Register of VMCS Field
Enumeration (R/O)
See Table 2-2.
See Appendix A.9, “VMCS Enumeration.”
48BH
1163
IA32_VMX_PROCBASED_CTLS2
Thread
Capability Reporting Register of Secondary Processor-
Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
48CH
1164
IA32_VMX_EPT_VPID_ENUM
Thread
Capability Reporting Register of EPT and VPID (R/O)
See Table 2-2
48DH
1165
IA32_VMX_TRUE_PINBASED_CTLS
Thread
Capability Reporting Register of Pin-Based
VM-Execution Flex Controls (R/O)
See Table 2-2
48EH
1166
IA32_VMX_TRUE_PROCBASED_CTLS
Thread
Capability Reporting Register of Primary Processor-
Based VM-Execution Flex Controls (R/O)
See Table 2-2
48FH
1167
IA32_VMX_TRUE_EXIT_CTLS
Thread
Capability Reporting Register of VM-Exit Flex Controls
(R/O)
See Table 2-2
490H
1168
IA32_VMX_TRUE_ENTRY_CTLS
Thread
Capability Reporting Register of VM-Entry Flex Controls
(R/O)
See Table 2-2
4C1H
1217
IA32_A_PMC0
Thread
See Table 2-2.
2-194 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
4C2H
1218
IA32_A_PMC1
Thread
See Table 2-2.
4C3H
1219
IA32_A_PMC2
Thread
See Table 2-2.
4C4H
1220
IA32_A_PMC3
Thread
See Table 2-2.
4C5H
1221
IA32_A_PMC4
Core
See Table 2-2.
4C6H
1222
IA32_A_PMC5
Core
See Table 2-2.
4C7H
1223
IA32_A_PMC6
Core
See Table 2-2.
4C8H
1224
IA32_A_PMC7
Core
See Table 2-2.
600H
1536
IA32_DS_AREA
Thread
DS Save Area (R/W)
See Table 2-2.
See Section 20.6.3.4, “Debug Store (DS) Mechanism.”
606H
1542
MSR_RAPL_POWER_UNIT
Package
Unit Multipliers used in RAPL Interfaces (R/O)
See Section 15.10.1, “RAPL Interfaces.”
60AH
1546
MSR_PKGC3_IRTL
Package
Package C3 Interrupt Response Limit (R/W)
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
9:0
Interrupt Response Time Limit (R/W)
Specifies the limit that should be used to decide if the
package should be put into a package C3 state.
12:10
Time Unit (R/W)
Specifies the encoding value of time unit of the
interrupt response time limit. The following time unit
encodings are supported:
000b: 1 ns
001b: 32 ns
010b: 1024 ns
011b: 32768 ns
100b: 1048576 ns
101b: 33554432 ns
14:13
Reserved
15
Valid (R/W)
Indicates whether the values in bits 12:0 are valid and
can be used by the processor for package C-sate
management.
63:16
Reserved
Vol. 4
2-195
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
60BH
1547
MSR_PKGC6_IRTL
Package
Package C6 Interrupt Response Limit (R/W)
This MSR defines the budget allocated for the package
to exit from a C6 to a C0 state, where an interrupt
request can be delivered to the core and serviced.
Additional core-exit latency may be applicable
depending on the actual C-state the core is in.
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
9:0
Interrupt Response Time Limit (R/W)
Specifies the limit that should be used to decide if the
package should be put into a package C6 state.
12:10
Time Unit (R/W)
Specifies the encoding value of time unit of the
interrupt response time limit. The following time unit
encodings are supported:
000b: 1 ns
001b: 32 ns
010b: 1024 ns
011b: 32768 ns
100b: 1048576 ns
101b: 33554432 ns
14:13
Reserved
15
Valid (R/W)
Indicates whether the values in bits 12:0 are valid and
can be used by the processor for package C-sate
management.
63:16
Reserved
60DH
1549
MSR_PKG_C2_RESIDENCY
Package
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
63:0
Package C2 Residency Counter (R/O)
Value since last reset that this package is in processor-
specific C2 states. Count at the same frequency as the
TSC.
610H
1552
MSR_PKG_POWER_LIMIT
Package
PKG RAPL Power Limit Control (R/W)
See Section 15.10.3, “Package RAPL Domain.”
611H
1553
MSR_PKG_ENERGY_STATUS
Package
PKG Energy Status (R/O)
See Section 15.10.3, “Package RAPL Domain.”
614H
1556
MSR_PKG_POWER_INFO
Package
PKG RAPL Parameters (R/W) See Section 15.10.3,
“Package RAPL Domain.”
638H
1592
MSR_PP0_POWER_LIMIT
Package
PP0 RAPL Power Limit Control (R/W)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
2-196 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
680H
1664
MSR_LASTBRANCH_0_FROM_IP
Thread
Last Branch Record 0 From IP (R/W)
One of sixteen pairs of last branch record registers on
the last branch record stack. This part of the stack
contains pointers to the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.9.1 and record format in Section 18.4.8.1.
681H
1665
MSR_LASTBRANCH_1_FROM_IP
Thread
Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
682H
1666
MSR_LASTBRANCH_2_FROM_IP
Thread
Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
683H
1667
MSR_LASTBRANCH_3_FROM_IP
Thread
Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
684H
1668
MSR_LASTBRANCH_4_FROM_IP
Thread
Last Branch Record 4 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
685H
1669
MSR_LASTBRANCH_5_FROM_IP
Thread
Last Branch Record 5 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
686H
1670
MSR_LASTBRANCH_6_FROM_IP
Thread
Last Branch Record 6 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
687H
1671
MSR_LASTBRANCH_7_FROM_IP
Thread
Last Branch Record 7 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
688H
1672
MSR_LASTBRANCH_8_FROM_IP
Thread
Last Branch Record 8 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
689H
1673
MSR_LASTBRANCH_9_FROM_IP
Thread
Last Branch Record 9 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68AH
1674
MSR_LASTBRANCH_10_FROM_IP
Thread
Last Branch Record 10 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68BH
1675
MSR_LASTBRANCH_11_FROM_IP
Thread
Last Branch Record 11 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68CH
1676
MSR_LASTBRANCH_12_FROM_IP
Thread
Last Branch Record 12 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68DH
1677
MSR_LASTBRANCH_13_FROM_IP
Thread
Last Branch Record 13 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68EH
1678
MSR_LASTBRANCH_14_FROM_IP
Thread
Last Branch Record 14 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
68FH
1679
MSR_LASTBRANCH_15_FROM_IP
Thread
Last Branch Record 15 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
6C0H
1728
MSR_LASTBRANCH_0_TO_IP
Thread
Last Branch Record 0 To IP (R/W)
One of sixteen pairs of last branch record registers on
the last branch record stack. This part of the stack
contains pointers to the destination instruction.
Vol. 4
2-197
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
6C1H
1729
MSR_LASTBRANCH_1_TO_IP
Thread
Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C2H
1730
MSR_LASTBRANCH_2_TO_IP
Thread
Last Branch Record 2 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C3H
1731
MSR_LASTBRANCH_3_TO_IP
Thread
Last Branch Record 3 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C4H
1732
MSR_LASTBRANCH_4_TO_IP
Thread
Last Branch Record 4 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C5H
1733
MSR_LASTBRANCH_5_TO_IP
Thread
Last Branch Record 5 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C6H
1734
MSR_LASTBRANCH_6_TO_IP
Thread
Last Branch Record 6 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C7H
1735
MSR_LASTBRANCH_7_TO_IP
Thread
Last Branch Record 7 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C8H
1736
MSR_LASTBRANCH_8_TO_IP
Thread
Last Branch Record 8 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6C9H
1737
MSR_LASTBRANCH_9_TO_IP
Thread
Last Branch Record 9 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CAH
1738
MSR_LASTBRANCH_10_TO_IP
Thread
Last Branch Record 10 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CBH
1739
MSR_LASTBRANCH_11_TO_IP
Thread
Last Branch Record 11 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CCH
1740
MSR_LASTBRANCH_12_TO_IP
Thread
Last Branch Record 12 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CDH
1741
MSR_LASTBRANCH_13_TO_IP
Thread
Last Branch Record 13 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CEH
1742
MSR_LASTBRANCH_14_TO_IP
Thread
Last Branch Record 14 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6CFH
1743
MSR_LASTBRANCH_15_TO_IP
Thread
Last Branch Record 15 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
6E0H
1760
IA32_TSC_DEADLINE
Thread
See Table 2-2.
802H-
2050-
X2APIC MSRs
Thread
See Table 2-2.
83FH
2111
C000_
IA32_EFER
Thread
Extended Feature Enables
0080H
See Table 2-2.
C000_
IA32_STAR
Thread
System Call Target Address (R/W)
0081H
See Table 2-2.
C000_
IA32_LSTAR
Thread
IA-32e Mode System Call Target Address (R/W)
0082H
See Table 2-2.
2-198 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
C000_
IA32_FMASK
Thread
System Call Flag Mask (R/W)
0084H
See Table 2-2.
C000_
IA32_FS_BASE
Thread
Map of BASE Address of FS (R/W)
0100H
See Table 2-2.
C000_
IA32_GS_BASE
Thread
Map of BASE Address of GS (R/W)
0101H
See Table 2-2.
C000_
IA32_KERNEL_GS_BASE
Thread
Swap Target of BASE Address of GS (R/W)
0102H
See Table 2-2.
C000_
IA32_TSC_AUX
Thread
AUXILIARY TSC Signature (R/W)
0103H
See Table 2-2 and Section 18.17.2, “IA32_TSC_AUX
Register and RDTSCP Support.”
2.11.1 MSRs in the 2nd Generation Intel® Core™ Processor Family Based on Sandy Bridge
Microarchitecture
Table 2-21 and Table 2-22 list model-specific registers (MSRs) that are specific to the 2nd generation Intel® Core™
processor family based on the Sandy Bridge microarchitecture. These processors have a CPUID Signature
DisplayFamily_DisplayModel value of 06_2AH; see Table 2-1.
Table 2-21. MSRs Supported by the 2nd Generation Intel® Core™ Processors (Sandy Bridge Microarchitecture)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
1ADH
429
MSR_TURBO_RATIO_LIMIT
Package
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0.
R/W if MSR_PLATFORM_INFO.[28] = 1.
7:0
Package
Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8
Package
Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
23:16
Package
Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
31:24
Package
Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
63:32
Reserved
Vol. 4
2-199
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-21. MSRs Supported by the 2nd Generation Intel® Core™ Processors (Sandy Bridge Microarchitecture)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
60CH
1548
MSR_PKGC7_IRTL
Package
Package C7 Interrupt Response Limit (R/W)
This MSR defines the budget allocated for the
package to exit from a C7 to a C0 state, where
interrupt request can be delivered to the core and
serviced. Additional core-exit latency may be
applicable depending on the actual C-state the core
is in.
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
9:0
Interrupt Response Time Limit (R/W)
Specifies the limit that should be used to decide if
the package should be put into a package C7 state.
12:10
Time Unit (R/W)
Specifies the encoding value of time unit of the
interrupt response time limit. The following time unit
encodings are supported:
000b: 1 ns
001b: 32 ns
010b: 1024 ns
011b: 32768 ns
100b: 1048576 ns
101b: 33554432 ns
14:13
Reserved
15
Valid (R/W)
Indicates whether the values in bits 12:0 are valid
and can be used by the processor for package C-sate
management.
63:16
Reserved
639H
1593
MSR_PP0_ENERGY_STATUS
Package
PP0 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
63AH
1594
MSR_PP0_POLICY
Package
PP0 Balance Policy (R/W)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
640H
1600
MSR_PP1_POWER_LIMIT
Package
PP1 RAPL Power Limit Control (R/W)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
641H
1601
MSR_PP1_ENERGY_STATUS
Package
PP1 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
642H
1602
MSR_PP1_POLICY
Package
PP1 Balance Policy (R/W)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
See Table 2-20, Table 2-21, and Table 2-22 for MSR definitions applicable to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_2AH.
Table 2-22 lists the MSRs of uncore PMU for Intel processors with a CPUID Signature DisplayFamily_DisplayModel
value of 06_2AH.
2-200 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
391H
913
MSR_UNC_PERF_GLOBAL_CTRL
Package
Uncore PMU Global Control
0
Slice 0 select.
1
Slice 1 select.
2
Slice 2 select.
3
Slice 3 select.
4
Slice 4 select.
18:5
Reserved
29
Enable all uncore counters.
30
Enable wake on PMI.
31
Enable Freezing counter when overflow.
63:32
Reserved
392H
914
MSR_UNC_PERF_GLOBAL_STATUS
Package
Uncore PMU Main Status
0
Fixed counter overflowed.
1
An ARB counter overflowed.
2
Reserved
3
A CBox counter overflowed (on any slice).
63:4
Reserved
394H
916
MSR_UNC_PERF_FIXED_CTRL
Package
Uncore Fixed Counter Control (R/W)
19:0
Reserved
20
Enable overflow propagation.
21
Reserved
22
Enable counting.
63:23
Reserved
395H
917
MSR_UNC_PERF_FIXED_CTR
Package
Uncore Fixed Counter
47:0
Current count.
63:48
Reserved
396H
918
MSR_UNC_CBO_CONFIG
Package
Uncore C-Box Configuration Information (R/O)
3:0
Report the number of C-Box units with performance
counters, including processor cores and processor
graphics.
63:4
Reserved
3B0H
946
MSR_UNC_ARB_PERFCTR0
Package
Uncore Arb Unit, Performance Counter 0
3B1H
947
MSR_UNC_ARB_PERFCTR1
Package
Uncore Arb Unit, Performance Counter 1
3B2H
944
MSR_UNC_ARB_PERFEVTSEL0
Package
Uncore Arb Unit, Counter 0 Event Select MSR
3B3H
945
MSR_UNC_ARB_PERFEVTSEL1
Package
Uncore Arb unit, Counter 1 Event Select MSR
Vol. 4
2-201
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
700H
1792
MSR_UNC_CBO_0_PERFEVTSEL0
Package
Uncore C-Box 0, Counter 0 Event Select MSR
701H
1793
MSR_UNC_CBO_0_PERFEVTSEL1
Package
Uncore C-Box 0, Counter 1 Event Select MSR
702H
1794
MSR_UNC_CBO_0_PERFEVTSEL2
Package
Uncore C-Box 0, Counter 2 Event Select MSR
703H
1795
MSR_UNC_CBO_0_PERFEVTSEL3
Package
Uncore C-Box 0, Counter 3 Event Select MSR
705H
1797
MSR_UNC_CBO_0_UNIT_STATUS
Package
Uncore C-Box 0, Unit Status for Counter 0-3
706H
1798
MSR_UNC_CBO_0_PERFCTR0
Package
Uncore C-Box 0, Performance Counter 0
707H
1799
MSR_UNC_CBO_0_PERFCTR1
Package
Uncore C-Box 0, Performance Counter 1
708H
1800
MSR_UNC_CBO_0_PERFCTR2
Package
Uncore C-Box 0, Performance Counter 2
709H
1801
MSR_UNC_CBO_0_PERFCTR3
Package
Uncore C-Box 0, Performance Counter 3
710H
1808
MSR_UNC_CBO_1_PERFEVTSEL0
Package
Uncore C-Box 1, Counter 0 Event Select MSR
711H
1809
MSR_UNC_CBO_1_PERFEVTSEL1
Package
Uncore C-Box 1, Counter 1 Event Select MSR
712H
1810
MSR_UNC_CBO_1_PERFEVTSEL2
Package
Uncore C-Box 1, Counter 2 Event Select MSR
713H
1811
MSR_UNC_CBO_1_PERFEVTSEL3
Package
Uncore C-Box 1, Counter 3 Event Select MSR
715H
1813
MSR_UNC_CBO_1_UNIT_STATUS
Package
Uncore C-Box 1, Unit Status for Counter 0-3
716H
1814
MSR_UNC_CBO_1_PERFCTR0
Package
Uncore C-Box 1, Performance Counter 0
717H
1815
MSR_UNC_CBO_1_PERFCTR1
Package
Uncore C-Box 1, Performance Counter 1
718H
1816
MSR_UNC_CBO_1_PERFCTR2
Package
Uncore C-Box 1, Performance Counter 2
719H
1817
MSR_UNC_CBO_1_PERFCTR3
Package
Uncore C-Box 1, Performance Counter 3
720H
1824
MSR_UNC_CBO_2_PERFEVTSEL0
Package
Uncore C-Box 2, Counter 0 Event Select MSR
721H
1825
MSR_UNC_CBO_2_PERFEVTSEL1
Package
Uncore C-Box 2, Counter 1 Event Select MSR
722H
1826
MSR_UNC_CBO_2_PERFEVTSEL2
Package
Uncore C-Box 2, Counter 2 Event Select MSR
723H
1827
MSR_UNC_CBO_2_PERFEVTSEL3
Package
Uncore C-Box 2, Counter 3 Event Select MSR
725H
1829
MSR_UNC_CBO_2_UNIT_STATUS
Package
Uncore C-Box 2, Unit Status for Counter 0-3
726H
1830
MSR_UNC_CBO_2_PERFCTR0
Package
Uncore C-Box 2, Performance Counter 0
727H
1831
MSR_UNC_CBO_2_PERFCTR1
Package
Uncore C-Box 2, Performance Counter 1
728H
1832
MSR_UNC_CBO_3_PERFCTR2
Package
Uncore C-Box 3, Performance Counter 2
729H
1833
MSR_UNC_CBO_3_PERFCTR3
Package
Uncore C-Box 3, Performance Counter 3
730H
1840
MSR_UNC_CBO_3_PERFEVTSEL0
Package
Uncore C-Box 3, Counter 0 Event Select MSR
731H
1841
MSR_UNC_CBO_3_PERFEVTSEL1
Package
Uncore C-Box 3, Counter 1 Event Select MSR
732H
1842
MSR_UNC_CBO_3_PERFEVTSEL2
Package
Uncore C-Box 3, Counter 2 Event Select MSR
733H
1843
MSR_UNC_CBO_3_PERFEVTSEL3
Package
Uncore C-Box 3, counter 3 Event Select MSR
735H
1845
MSR_UNC_CBO_3_UNIT_STATUS
Package
Uncore C-Box 3, Unit Status for Counter 0-3
736H
1846
MSR_UNC_CBO_3_PERFCTR0
Package
Uncore C-Box 3, Performance Counter 0
737H
1847
MSR_UNC_CBO_3_PERFCTR1
Package
Uncore C-Box 3, Performance Counter 1
738H
1848
MSR_UNC_CBO_3_PERFCTR2
Package
Uncore C-Box 3, Performance Counter 2
739H
1849
MSR_UNC_CBO_3_PERFCTR3
Package
Uncore C-Box 3, Performance Counter 3
740H
1856
MSR_UNC_CBO_4_PERFEVTSEL0
Package
Uncore C-Box 4, Counter 0 Event Select MSR
2-202 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
741H
1857
MSR_UNC_CBO_4_PERFEVTSEL1
Package
Uncore C-Box 4, Counter 1 Event Select MSR
742H
1858
MSR_UNC_CBO_4_PERFEVTSEL2
Package
Uncore C-Box 4, Counter 2 Event Select MSR
743H
1859
MSR_UNC_CBO_4_PERFEVTSEL3
Package
Uncore C-Box 4, Counter 3 Event Select MSR
745H
1861
MSR_UNC_CBO_4_UNIT_STATUS
Package
Uncore C-Box 4, Unit status for Counter 0-3
746H
1862
MSR_UNC_CBO_4_PERFCTR0
Package
Uncore C-Box 4, Performance Counter 0
747H
1863
MSR_UNC_CBO_4_PERFCTR1
Package
Uncore C-Box 4, Performance Counter 1
748H
1864
MSR_UNC_CBO_4_PERFCTR2
Package
Uncore C-Box 4, Performance Counter 2
749H
1865
MSR_UNC_CBO_4_PERFCTR3
Package
Uncore C-Box 4, Performance Counter 3
2.11.2 MSRs in the Intel® Xeon® Processor E5 Family Based on Sandy Bridge
Microarchitecture
Table 2-23 lists additional model-specific registers (MSRs) that are specific to the Intel® Xeon® Processor E5
Family based on Sandy Bridge microarchitecture. These processors have a CPUID Signature
DisplayFamily_DisplayModel value of 06_2DH, and also support MSRs listed in Table 2-20 and Table 2-24.
Table 2-23. Selected MSRs Supported by Intel® Xeon® Processors E5 Family Based on Sandy Bridge
Microarchitecture
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
17FH
383
MSR_ERROR_CONTROL
Package
MC Bank Error Configuration (R/W)
0
Reserved
1
MemError Log Enable (R/W)
When set, enables IMC status bank to log additional
info in bits 36:32.
63:2
Reserved
1ADH
429
MSR_TURBO_RATIO_LIMIT
Package
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0,
R/W if MSR_PLATFORM_INFO.[28] = 1
7:0
Package
Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
15:8
Package
Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 cores active.
23:16
Package
Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 cores active.
31:24
Package
Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 cores active.
39:32
Package
Maximum Ratio Limit for 5C
Maximum turbo ratio limit of 5 cores active.
Vol. 4
2-203
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-23. Selected MSRs Supported by Intel® Xeon® Processors E5 Family Based on Sandy Bridge
Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
47:40
Package
Maximum Ratio Limit for 6C
Maximum turbo ratio limit of 6 cores active.
55:48
Package
Maximum Ratio Limit for 7C
Maximum turbo ratio limit of 7 cores active.
63:56
Package
Maximum Ratio Limit for 8C
Maximum turbo ratio limit of 8 cores active.
285H
645
IA32_MC5_CTL2
Package
See Table 2-2.
286H
646
IA32_MC6_CTL2
Package
See Table 2-2.
287H
647
IA32_MC7_CTL2
Package
See Table 2-2.
288H
648
IA32_MC8_CTL2
Package
See Table 2-2.
289H
649
IA32_MC9_CTL2
Package
See Table 2-2.
28AH
650
IA32_MC10_CTL2
Package
See Table 2-2.
28BH
651
IA32_MC11_CTL2
Package
See Table 2-2.
28CH
652
IA32_MC12_CTL2
Package
See Table 2-2.
28DH
653
IA32_MC13_CTL2
Package
See Table 2-2.
28EH
654
IA32_MC14_CTL2
Package
See Table 2-2.
28FH
655
IA32_MC15_CTL2
Package
See Table 2-2.
290H
656
IA32_MC16_CTL2
Package
See Table 2-2.
291H
657
IA32_MC17_CTL2
Package
See Table 2-2.
292H
658
IA32_MC18_CTL2
Package
See Table 2-2.
293H
659
IA32_MC19_CTL2
Package
See Table 2-2.
39CH
924
MSR_PEBS_NUM_ALT
Package
ENABLE_PEBS_NUM_ALT (R/W)
0
ENABLE_PEBS_NUM_ALT (R/W)
Write 1 to enable alternate PEBS counting logic for
specific events requiring additional configuration, see
https://perfmon-events.intel.com/.
63:1
Reserved, must be zero.
414H
1044
IA32_MC5_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
415H
1045
IA32_MC5_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
416H
1046
IA32_MC5_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
417H
1047
IA32_MC5_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
418H
1048
IA32_MC6_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
419H
1049
IA32_MC6_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
41AH
1050
IA32_MC6_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
41BH
1051
IA32_MC6_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
41CH
1052
IA32_MC7_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
2-204 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-23. Selected MSRs Supported by Intel® Xeon® Processors E5 Family Based on Sandy Bridge
Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
41DH
1053
IA32_MC7_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
41EH
1054
IA32_MC7_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
41FH
1055
IA32_MC7_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
420H
1056
IA32_MC8_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
421H
1057
IA32_MC8_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
422H
1058
IA32_MC8_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
423H
1059
IA32_MC8_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
424H
1060
IA32_MC9_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
425H
1061
IA32_MC9_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
426H
1062
IA32_MC9_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
427H
1063
IA32_MC9_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
428H
1064
IA32_MC10_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
429H
1065
IA32_MC10_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
42AH
1066
IA32_MC10_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
42BH
1067
IA32_MC10_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
42CH
1068
IA32_MC11_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
42DH
1069
IA32_MC11_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
42EH
1070
IA32_MC11_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
42FH
1071
IA32_MC11_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
430H
1072
IA32_MC12_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
431H
1073
IA32_MC12_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
432H
1074
IA32_MC12_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
433H
1075
IA32_MC12_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
434H
1076
IA32_MC13_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
435H
1077
IA32_MC13_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
436H
1078
IA32_MC13_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
437H
1079
IA32_MC13_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
438H
1080
IA32_MC14_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
439H
1081
IA32_MC14_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
43AH
1082
IA32_MC14_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
43BH
1083
IA32_MC14_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Vol. 4
2-205
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-23. Selected MSRs Supported by Intel® Xeon® Processors E5 Family Based on Sandy Bridge
Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
43CH
1084
IA32_MC15_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
43DH
1085
IA32_MC15_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
43EH
1086
IA32_MC15_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
43FH
1087
IA32_MC15_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
440H
1088
IA32_MC16_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
441H
1089
IA32_MC16_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
442H
1090
IA32_MC16_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
443H
1091
IA32_MC16_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
444H
1092
IA32_MC17_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
445H
1093
IA32_MC17_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
446H
1094
IA32_MC17_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
447H
1095
IA32_MC17_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
448H
1096
IA32_MC18_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
449H
1097
IA32_MC18_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
44AH
1098
IA32_MC18_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
44BH
1099
IA32_MC18_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
44CH
1100
IA32_MC19_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
44DH
1101
IA32_MC19_STATUS
Package
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and
Chapter 17.
44EH
1102
IA32_MC19_ADDR
Package
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
44FH
1103
IA32_MC19_MISC
Package
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
613H
1555
MSR_PKG_PERF_STATUS
Package
Package RAPL Perf Status (R/O)
618H
1560
MSR_DRAM_POWER_LIMIT
Package
DRAM RAPL Power Limit Control (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
619H
1561
MSR_DRAM_ENERGY_STATUS
Package
DRAM Energy Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
61BH
1563
MSR_DRAM_PERF_STATUS
Package
DRAM Performance Throttling Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
61CH
1564
MSR_DRAM_POWER_INFO
Package
DRAM RAPL Parameters (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
639H
1593
MSR_PP0_ENERGY_STATUS
Package
PP0 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
See Table 2-20, Table 2-23, and Table 2-24 for MSR definitions applicable to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_2DH.
2-206 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.11.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 Family
Intel Xeon Processor E5 family is based on the Sandy Bridge microarchitecture. The MSR-based uncore PMU inter-
faces are listed in Table 2-24. For complete details of the uncore PMU, refer to the Intel Xeon Processor E5 Product
Family Uncore Performance Monitoring Guide. These processors have a CPUID Signature
DisplayFamily_DisplayModel value of 06_2DH.
Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
C08H
3080
MSR_U_PMON_UCLK_FIXED_CTL
Package
Uncore U-box UCLK Fixed Counter Control
C09H
3081
MSR_U_PMON_UCLK_FIXED_CTR
Package
Uncore U-box UCLK Fixed Counter
C10H
3088
MSR_U_PMON_EVNTSEL0
Package
Uncore U-box Perfmon Event Select for U-box
Counter 0
C11H
3089
MSR_U_PMON_EVNTSEL1
Package
Uncore U-box Perfmon Event Select for U-box
Counter 1
C16H
3094
MSR_U_PMON_CTR0
Package
Uncore U-box Perfmon Counter 0
C17H
3095
MSR_U_PMON_CTR1
Package
Uncore U-box Perfmon Counter 1
C24H
3108
MSR_PCU_PMON_BOX_CTL
Package
Uncore PCU Perfmon for PCU-box-wide Control
C30H
3120
MSR_PCU_PMON_EVNTSEL0
Package
Uncore PCU Perfmon Event Select for PCU Counter 0
C31H
3121
MSR_PCU_PMON_EVNTSEL1
Package
Uncore PCU Perfmon Event Select for PCU Counter 1
C32H
3122
MSR_PCU_PMON_EVNTSEL2
Package
Uncore PCU Perfmon Event Select for PCU Counter 2
C33H
3123
MSR_PCU_PMON_EVNTSEL3
Package
Uncore PCU Perfmon Event Select for PCU Counter 3
C34H
3124
MSR_PCU_PMON_BOX_FILTER
Package
Uncore PCU Perfmon box-wide Filter
C36H
3126
MSR_PCU_PMON_CTR0
Package
Uncore PCU Perfmon Counter 0
C37H
3127
MSR_PCU_PMON_CTR1
Package
Uncore PCU Perfmon Counter 1
C38H
3128
MSR_PCU_PMON_CTR2
Package
Uncore PCU Perfmon Counter 2
C39H
3129
MSR_PCU_PMON_CTR3
Package
Uncore PCU Perfmon Counter 3
D04H
3332
MSR_C0_PMON_BOX_CTL
Package
Uncore C-box 0 Perfmon Local Box Wide Control
D10H
3344
MSR_C0_PMON_EVNTSEL0
Package
Uncore C-box 0 Perfmon Event Select for C-box 0
Counter 0
D11H
3345
MSR_C0_PMON_EVNTSEL1
Package
Uncore C-box 0 Perfmon Event Select for C-box 0
Counter 1
D12H
3346
MSR_C0_PMON_EVNTSEL2
Package
Uncore C-box 0 Perfmon Event Select for C-box 0
Counter 2
D13H
3347
MSR_C0_PMON_EVNTSEL3
Package
Uncore C-box 0 Perfmon Event Select for C-box 0
Counter 3
D14H
3348
MSR_C0_PMON_BOX_FILTER
Package
Uncore C-box 0 Perfmon Box Wide Filter
D16H
3350
MSR_C0_PMON_CTR0
Package
Uncore C-box 0 Perfmon Counter 0
D17H
3351
MSR_C0_PMON_CTR1
Package
Uncore C-box 0 Perfmon Counter 1
D18H
3352
MSR_C0_PMON_CTR2
Package
Uncore C-box 0 Perfmon Counter 2
D19H
3353
MSR_C0_PMON_CTR3
Package
Uncore C-box 0 Perfmon Counter 3
D24H
3364
MSR_C1_PMON_BOX_CTL
Package
Uncore C-box 1 Perfmon Local Box Wide Control
Vol. 4
2-207
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
D30H
3376
MSR_C1_PMON_EVNTSEL0
Package
Uncore C-box 1 Perfmon Event Select for C-box 1
Counter 0
D31H
3377
MSR_C1_PMON_EVNTSEL1
Package
Uncore C-box 1 Perfmon Event Select for C-box 1
Counter 1
D32H
3378
MSR_C1_PMON_EVNTSEL2
Package
Uncore C-box 1 Perfmon Event Select for C-box 1
Counter 2
D33H
3379
MSR_C1_PMON_EVNTSEL3
Package
Uncore C-box 1 Perfmon Event Select for C-box 1
Counter 3
D34H
3380
MSR_C1_PMON_BOX_FILTER
Package
Uncore C-box 1 Perfmon Box Wide Filter
D36H
3382
MSR_C1_PMON_CTR0
Package
Uncore C-box 1 Perfmon Counter 0
D37H
3383
MSR_C1_PMON_CTR1
Package
Uncore C-box 1 Perfmon Counter 1
D38H
3384
MSR_C1_PMON_CTR2
Package
Uncore C-box 1 Perfmon Counter 2
D39H
3385
MSR_C1_PMON_CTR3
Package
Uncore C-box 1 Perfmon Counter 3
D44H
3396
MSR_C2_PMON_BOX_CTL
Package
Uncore C-box 2 Perfmon Local Box Wide Control
D50H
3408
MSR_C2_PMON_EVNTSEL0
Package
Uncore C-box 2 Perfmon Event Select for C-box 2
Counter 0
D51H
3409
MSR_C2_PMON_EVNTSEL1
Package
Uncore C-box 2 Perfmon Event Select for C-box 2
Counter 1
D52H
3410
MSR_C2_PMON_EVNTSEL2
Package
Uncore C-box 2 Perfmon Event Select for C-box 2
Counter 2
D53H
3411
MSR_C2_PMON_EVNTSEL3
Package
Uncore C-box 2 Perfmon Event Select for C-box 2
Counter 3
D54H
3412
MSR_C2_PMON_BOX_FILTER
Package
Uncore C-box 2 Perfmon Box Wide Filter
D56H
3414
MSR_C2_PMON_CTR0
Package
Uncore C-box 2 Perfmon Counter 0
D57H
3415
MSR_C2_PMON_CTR1
Package
Uncore C-box 2 Perfmon Counter 1
D58H
3416
MSR_C2_PMON_CTR2
Package
Uncore C-box 2 Perfmon Counter 2
D59H
3417
MSR_C2_PMON_CTR3
Package
Uncore C-box 2 Perfmon Counter 3
D64H
3428
MSR_C3_PMON_BOX_CTL
Package
Uncore C-box 3 Perfmon Local Box Wide Control
D70H
3440
MSR_C3_PMON_EVNTSEL0
Package
Uncore C-box 3 Perfmon Event Select for C-box 3
Counter 0
D71H
3441
MSR_C3_PMON_EVNTSEL1
Package
Uncore C-box 3 Perfmon Event Select for C-box 3
Counter 1
D72H
3442
MSR_C3_PMON_EVNTSEL2
Package
Uncore C-box 3 Perfmon Event Select for C-box 3
Counter 2
D73H
3443
MSR_C3_PMON_EVNTSEL3
Package
Uncore C-box 3 Perfmon Event Select for C-box 3
Counter 3
D74H
3444
MSR_C3_PMON_BOX_FILTER
Package
Uncore C-box 3 Perfmon Box Wide Filter
D76H
3446
MSR_C3_PMON_CTR0
Package
Uncore C-box 3 Perfmon Counter 0
D77H
3447
MSR_C3_PMON_CTR1
Package
Uncore C-box 3 Perfmon Counter 1
D78H
3448
MSR_C3_PMON_CTR2
Package
Uncore C-box 3 Perfmon Counter 2
D79H
3449
MSR_C3_PMON_CTR3
Package
Uncore C-box 3 Perfmon Counter 3
2-208 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
D84H
3460
MSR_C4_PMON_BOX_CTL
Package
Uncore C-box 4 Perfmon Local Box Wide Control
D90H
3472
MSR_C4_PMON_EVNTSEL0
Package
Uncore C-box 4 Perfmon Event Select for C-box 4
Counter 0
D91H
3473
MSR_C4_PMON_EVNTSEL1
Package
Uncore C-box 4 Perfmon Event Select for C-box 4
Counter 1
D92H
3474
MSR_C4_PMON_EVNTSEL2
Package
Uncore C-box 4 Perfmon Event Select for C-box 4
Counter 2
D93H
3475
MSR_C4_PMON_EVNTSEL3
Package
Uncore C-box 4 Perfmon Event Select for C-box 4
Counter 3
D94H
3476
MSR_C4_PMON_BOX_FILTER
Package
Uncore C-box 4 Perfmon Box Wide Filter
D96H
3478
MSR_C4_PMON_CTR0
Package
Uncore C-box 4 Perfmon Counter 0
D97H
3479
MSR_C4_PMON_CTR1
Package
Uncore C-box 4 Perfmon Counter 1
D98H
3480
MSR_C4_PMON_CTR2
Package
Uncore C-box 4 Perfmon Counter 2
D99H
3481
MSR_C4_PMON_CTR3
Package
Uncore C-box 4 Perfmon Counter 3
DA4H
3492
MSR_C5_PMON_BOX_CTL
Package
Uncore C-box 5 Perfmon Local Box Wide Control
DB0H
3504
MSR_C5_PMON_EVNTSEL0
Package
Uncore C-box 5 Perfmon Event Select for C-box 5
Counter 0
DB1H
3505
MSR_C5_PMON_EVNTSEL1
Package
Uncore C-box 5 Perfmon Event Select for C-box 5
Counter 1
DB2H
3506
MSR_C5_PMON_EVNTSEL2
Package
Uncore C-box 5 Perfmon Event Select for C-box 5
Counter 2
DB3H
3507
MSR_C5_PMON_EVNTSEL3
Package
Uncore C-box 5 Perfmon Event Select for C-box 5
Counter 3
DB4H
3508
MSR_C5_PMON_BOX_FILTER
Package
Uncore C-box 5 Perfmon Box Wide Filter
DB6H
3510
MSR_C5_PMON_CTR0
Package
Uncore C-box 5 Perfmon Counter 0
DB7H
3511
MSR_C5_PMON_CTR1
Package
Uncore C-box 5 Perfmon Counter 1
DB8H
3512
MSR_C5_PMON_CTR2
Package
Uncore C-box 5 Perfmon Counter 2
DB9H
3513
MSR_C5_PMON_CTR3
Package
Uncore C-box 5 Perfmon Counter 3
DC4H
3524
MSR_C6_PMON_BOX_CTL
Package
Uncore C-box 6 Perfmon Local Box Wide Control
DD0H
3536
MSR_C6_PMON_EVNTSEL0
Package
Uncore C-box 6 Perfmon Event Select for C-box 6
Counter 0
DD1H
3537
MSR_C6_PMON_EVNTSEL1
Package
Uncore C-box 6 Perfmon Event Select for C-box 6
Counter 1
DD2H
3538
MSR_C6_PMON_EVNTSEL2
Package
Uncore C-box 6 Perfmon Event Select for C-box 6
Counter 2
DD3H
3539
MSR_C6_PMON_EVNTSEL3
Package
Uncore C-box 6 Perfmon Event Select for C-box 6
Counter 3
DD4H
3540
MSR_C6_PMON_BOX_FILTER
Package
Uncore C-box 6 Perfmon Box Wide Filter
DD6H
3542
MSR_C6_PMON_CTR0
Package
Uncore C-box 6 Perfmon Counter 0
DD7H
3543
MSR_C6_PMON_CTR1
Package
Uncore C-box 6 Perfmon Counter 1
DD8H
3544
MSR_C6_PMON_CTR2
Package
Uncore C-box 6 Perfmon Counter 2
Vol. 4
2-209
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
DD9H
3545
MSR_C6_PMON_CTR3
Package
Uncore C-box 6 Perfmon Counter 3
DE4H
3556
MSR_C7_PMON_BOX_CTL
Package
Uncore C-box 7 Perfmon Local Box Wide Control
DF0H
3568
MSR_C7_PMON_EVNTSEL0
Package
Uncore C-box 7 Perfmon Event Select for C-box 7
Counter 0
DF1H
3569
MSR_C7_PMON_EVNTSEL1
Package
Uncore C-box 7 Perfmon Event Select for C-box 7
Counter 1
DF2H
3570
MSR_C7_PMON_EVNTSEL2
Package
Uncore C-box 7 Perfmon Event Select for C-box 7
Counter 2
DF3H
3571
MSR_C7_PMON_EVNTSEL3
Package
Uncore C-box 7 Perfmon Event Select for C-box 7
Counter 3
DF4H
3572
MSR_C7_PMON_BOX_FILTER
Package
Uncore C-box 7 Perfmon Box Wide Filter
DF6H
3574
MSR_C7_PMON_CTR0
Package
Uncore C-box 7 Perfmon Counter 0
DF7H
3575
MSR_C7_PMON_CTR1
Package
Uncore C-box 7 Perfmon Counter 1
DF8H
3576
MSR_C7_PMON_CTR2
Package
Uncore C-box 7 Perfmon Counter 2
DF9H
3577
MSR_C7_PMON_CTR3
Package
Uncore C-box 7 Perfmon Counter 3
2.12
MSRS IN THE 3RD GENERATION INTEL® CORE™ PROCESSOR FAMILY BASED
ON IVY BRIDGE MICROARCHITECTURE
The 3rd generation Intel® Core™ processor family and the Intel® Xeon® processor E3-1200v2 product family
based on Ivy Bridge microarchitecture support the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-22, and
Table 2-25. These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_3AH.
Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge
Microarchitecture
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
CEH
206
MSR_PLATFORM_INFO
Package
Platform Information
Contains power management and other model
specific features enumeration. See http://biosbits.org.
7:0
Reserved
15:8
Package
Maximum Non-Turbo Ratio (R/O)
This is the ratio of the frequency that invariant TSC
runs at. Frequency = ratio * 100 MHz.
27:16
Reserved
28
Package
Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio
Limit for Turbo mode is enabled. When set to 0,
indicates Programmable Ratio Limit for Turbo mode is
disabled.
2-210 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge
Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
29
Package
Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limit for Turbo
mode is programmable. When set to 0, indicates that
TDP Limit for Turbo mode is not programmable.
31:30
Reserved
32
Package
Low Power Mode Support (LPM) (R/O)
When set to 1, indicates that LPM is supported. When
set to 0, indicates LPM is not supported.
34:33
Package
Number of ConfigTDP Levels (R/O)
00: Only Base TDP level available.
01: One additional TDP level available.
02: Two additional TDP level available.
03: Reserved
39:35
Reserved
47:40
Package
Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that
the processor can operate, in units of 100MHz.
55:48
Package
Minimum Operating Ratio (R/O)
Contains the minimum supported operating ratio in
units of 100 MHz.
63:56
Reserved
E2H
226
MSR_PKG_CST_CONFIG_CONTROL
Core
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state
code names, unrelated to MWAIT extension C-state
parameters or ACPI C-States.
See http://biosbits.org.
2:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code
name (consuming the least power) for the package.
The default is set as factory-configured package C-
state limit.
The following C-state code name encodings are
supported:
000b: C0/C1 (no package C-sate support)
001b: C2
010b: C6 no retention
011b: C6 retention
100b: C7
101b: C7s
111: No package C-state limit.
Note: This field cannot be used to limit package C-
state to C3.
Vol. 4
2-211
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge
Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
9:3
Reserved
10
I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO
register specified by MSR_PMG_IO_CAPTURE_BASE
to MWAIT instructions.
14:11
Reserved
15
CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next
reset.
24:16
Reserved
25
C3 State Auto Demotion Enable (R/W)
When set, the processor will conditionally demote
C6/C7 requests to C3 based on uncore auto-demote
information.
26
C1 State Auto Demotion Enable (R/W)
When set, the processor will conditionally demote
C3/C6/C7 requests to C1 based on uncore auto-
demote information.
27
Enable C3 Undemotion (R/W)
When set, enables undemotion from demoted C3.
28
Enable C1 Undemotion (R/W)
When set, enables undemotion from demoted C1.
63:29
Reserved
639H
1593
MSR_PP0_ENERGY_STATUS
Package
PP0 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
648H
1608
MSR_CONFIG_TDP_NOMINAL
Package
Base TDP Ratio (R/O)
7:0
Config_TDP_Base
Base TDP level ratio to be used for this specific
processor (in units of 100 MHz).
63:8
Reserved
649H
1609
MSR_CONFIG_TDP_LEVEL1
Package
ConfigTDP Level 1 ratio and power level (R/O)
14:0
PKG_TDP_LVL1
Power setting for ConfigTDP Level 1.
15
Reserved
23:16
Config_TDP_LVL1_Ratio
ConfigTDP level 1 ratio to be used for this specific
processor.
31:24
Reserved
46:32
PKG_MAX_PWR_LVL1
Max Power setting allowed for ConfigTDP Level 1.
2-212 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge
Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
47
Reserved
62:48
PKG_MIN_PWR_LVL1
MIN Power setting allowed for ConfigTDP Level 1.
63
Reserved
64AH
1610
MSR_CONFIG_TDP_LEVEL2
Package
ConfigTDP Level 2 ratio and power level (R/O)
14:0
PKG_TDP_LVL2
Power setting for ConfigTDP Level 2.
15
Reserved
23:16
Config_TDP_LVL2_Ratio
ConfigTDP level 2 ratio to be used for this specific
processor.
31:24
Reserved
46:32
PKG_MAX_PWR_LVL2
Max Power setting allowed for ConfigTDP Level 2.
47
Reserved
62:48
PKG_MIN_PWR_LVL2
MIN Power setting allowed for ConfigTDP Level 2.
63
Reserved
64BH
1611
MSR_CONFIG_TDP_CONTROL
Package
ConfigTDP Control (R/W)
1:0
TDP_LEVEL (RW/L)
System BIOS can program this field.
30:2
Reserved.
31
Config_TDP_Lock (RW/L)
When this bit is set, the content of this register is
locked until a reset.
63:32
Reserved
64CH
1612
MSR_TURBO_ACTIVATION_RATIO
Package
ConfigTDP Control (R/W)
7:0
MAX_NON_TURBO_RATIO (RW/L)
System BIOS can program this field.
30:8
Reserved
31
TURBO_ACTIVATION_RATIO_Lock (RW/L)
When this bit is set, the content of this register is
locked until a reset.
63:32
Reserved
See Table 2-20, Table 2-21, and Table 2-22 for other MSR definitions applicable to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_3AH.
Vol. 4
2-213
MODEL-SPECIFIC REGISTERS (MSRS)
2.12.1 MSRs in the Intel® Xeon® Processor E5 v2 Product Family Based on Ivy Bridge-E
Microarchitecture
Table 2-26 lists model-specific registers (MSRs) that are specific to the Intel® Xeon® Processor E5 v2 Product
Family (based on Ivy Bridge-E microarchitecture). These processors have a CPUID Signature
DisplayFamily_DisplayModel value of 06_3EH; see Table 2-1. These processors supports the MSR interfaces listed
in Table 2-20 and Table 2-26.
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family Based on Ivy Bridge-E
Microarchitecture
Register
Address
Register Name / Bit Fields
Scope
Bit Description
(Former MSR Name)
Hex
Dec
4EH
78
IA32_PPIN_CTL
Package
Protected Processor Inventory Number Enable Control
(MSR_PPIN_CTL)
(R/W)
0
LockOut (R/WO)
See Table 2-2.
1
Enable_PPIN (R/W)
See Table 2-2.
63:2
Reserved
4FH
79
IA32_PPIN
Package
Protected Processor Inventory Number (R/O)
(MSR_PPIN)
63:0
Protected Processor Inventory Number (R/O)
See Table 2-2.
CEH
206
MSR_PLATFORM_INFO
Package
Platform Information
Contains power management and other model specific
features enumeration. See http://biosbits.org.
7:0
Reserved
15:8
Package
Maximum Non-Turbo Ratio (R/O)
This is the ratio of the frequency that invariant TSC
runs at. Frequency = ratio * 100 MHz.
22:16
Reserved
23
Package
PPIN_CAP (R/O)
When set to 1, indicates that Protected Processor
Inventory Number (PPIN) capability can be enabled for
a privileged system inventory agent to read PPIN from
MSR_PPIN.
When set to 0, PPIN capability is not supported. An
attempt to access MSR_PPIN_CTL or MSR_PPIN will
cause #GP.
27:24
Reserved
28
Package
Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limit
for Turbo mode is enabled. When set to 0, indicates
Programmable Ratio Limit for Turbo mode is disabled.
2-214 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family Based on Ivy Bridge-E
Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
(Former MSR Name)
Hex
Dec
29
Package
Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limit for Turbo mode
is programmable. When set to 0, indicates TDP Limit for
Turbo mode is not programmable.
30
Package
Programmable TJ OFFSET (R/O)
When set to 1, indicates that
MSR_TEMPERATURE_TARGET.[27:24] is valid and
writable to specify a temperature offset.
39:31
Reserved
47:40
Package
Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that
the processor can operate, in units of 100MHz.
63:48
Reserved
E2H
226
MSR_PKG_CST_CONFIG_CONTROL
Core
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code
names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
See http://biosbits.org.
2:0
Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code
name (consuming the least power) for the package.
The default is set as factory-configured package C-
state limit.
The following C-state code name encodings are
supported:
000b: C0/C1 (no package C-sate support)
001b: C2
010b: C6 no retention
011b: C6 retention
100b: C7
101b: C7s
111: No package C-state limit.
Note: This field cannot be used to limit package C-state
to C3.
9:3
Reserved
10
I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO
register specified by MSR_PMG_IO_CAPTURE_BASE to
MWAIT instructions.
14:11
Reserved
15
CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next
reset.
Vol. 4
2-215
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family Based on Ivy Bridge-E
Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
(Former MSR Name)
Hex
Dec
63:16
Reserved
179H
377
IA32_MCG_CAP
Thread
Global Machine Check Capability (R/O)
7:0
Count
8
MCG_CTL_P
9
MCG_EXT_P
10
MCP_CMCI_P
11
MCG_TES_P
15:12
Reserved
23:16
MCG_EXT_CNT
24
MCG_SER_P
25
Reserved
26
MCG_ELOG_P
63:27
Reserved
17FH
383
MSR_ERROR_CONTROL
Package
MC Bank Error Configuration (R/W)
0
Reserved
1
MemError Log Enable (R/W)
When set, enables IMC status bank to log additional info
in bits 36:32.
63:2
Reserved
1A2H
418
MSR_TEMPERATURE_TARGET
Package
Temperature Target
15:0
Reserved
23:16
Temperature Target (R/O)
The minimum temperature at which PROCHOT# will be
asserted. The value is degrees C.
27:24
TCC Activation Offset (R/W)
Specifies a temperature offset in degrees C from the
temperature target (bits 23:16). PROCHOT# will assert
at the offset target temperature. Write is permitted
only if MSR_PLATFORM_INFO.[30] is set.
63:28
Reserved
1AEH
430
MSR_TURBO_RATIO_LIMIT1
Package
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0.
R/W if MSR_PLATFORM_INFO.[28] = 1.
7:0
Package
Maximum Ratio Limit for 9C
Maximum turbo ratio limit of 9 core active.
15:8
Package
Maximum Ratio Limit for 10C
Maximum turbo ratio limit of 10 core active.
23:16
Package
Maximum Ratio Limit for 11C
Maximum turbo ratio limit of 11 core active.
2-216 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family Based on Ivy Bridge-E
Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
(Former MSR Name)
Hex
Dec
31:24
Package
Maximum Ratio Limit for 12C
Maximum turbo ratio limit of 12 core active.
63:32
Reserved
285H
645
IA32_MC5_CTL2
Package
See Table 2-2.
286H
646
IA32_MC6_CTL2
Package
See Table 2-2.
287H
647
IA32_MC7_CTL2
Package
See Table 2-2.
288H
648
IA32_MC8_CTL2
Package
See Table 2-2.
289H
649
IA32_MC9_CTL2
Package
See Table 2-2.
28AH
650
IA32_MC10_CTL2
Package
See Table 2-2.
28BH
651
IA32_MC11_CTL2
Package
See Table 2-2.
28CH
652
IA32_MC12_CTL2
Package
See Table 2-2.
28DH
653
IA32_MC13_CTL2
Package
See Table 2-2.
28EH
654
IA32_MC14_CTL2
Package
See Table 2-2.
28FH
655
IA32_MC15_CTL2
Package
See Table 2-2.
290H
656
IA32_MC16_CTL2
Package
See Table 2-2.
291H
657
IA32_MC17_CTL2
Package
See Table 2-2.
292H
658
IA32_MC18_CTL2
Package
See Table 2-2.
293H
659
IA32_MC19_CTL2
Package
See Table 2-2.
294H
660
IA32_MC20_CTL2
Package
See Table 2-2.
295H
661
IA32_MC21_CTL2
Package
See Table 2-2.
296H
662
IA32_MC22_CTL2
Package
See Table 2-2.
297H
663
IA32_MC23_CTL2
Package
See Table 2-2.
298H
664
IA32_MC24_CTL2
Package
See Table 2-2.
299H
665
IA32_MC25_CTL2
Package
See Table 2-2.
29AH
666
IA32_MC26_CTL2
Package
See Table 2-2.
29BH
667
IA32_MC27_CTL2
Package
See Table 2-2.
29CH
668
IA32_MC28_CTL2
Package
See Table 2-2.
414H
1044
IA32_MC5_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
415H
1045
IA32_MC5_STATUS
Package
Bank MC5 reports MC errors from the Intel QPI module.
416H
1046
IA32_MC5_ADDR
Package
417H
1047
IA32_MC5_MISC
Package
418H
1048
IA32_MC6_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
419H
1049
IA32_MC6_STATUS
Package
Bank MC6 reports MC errors from the integrated I/O
41AH
1050
IA32_MC6_ADDR
Package
module.
41BH
1051
IA32_MC6_MISC
Package
Vol. 4
2-217
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family Based on Ivy Bridge-E
Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
(Former MSR Name)
Hex
Dec
41CH
1052
IA32_MC7_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
41DH
1053
IA32_MC7_STATUS
Package
Banks MC7 and MC 8 report MC errors from the two
41EH
1054
IA32_MC7_ADDR
Package
home agents.
41FH
1055
IA32_MC7_MISC
Package
420H
1056
IA32_MC8_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
421H
1057
IA32_MC8_STATUS
Package
Banks MC7 and MC 8 report MC errors from the two
422H
1058
IA32_MC8_ADDR
Package
home agents.
423H
1059
IA32_MC8_MISC
Package
424H
1060
IA32_MC9_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
425H
1061
IA32_MC9_STATUS
Package
Banks MC9 through MC 16 report MC errors from each
426H
1062
IA32_MC9_ADDR
Package
channel of the integrated memory controllers.
427H
1063
IA32_MC9_MISC
Package
428H
1064
IA32_MC10_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
429H
1065
IA32_MC10_STATUS
Package
Banks MC9 through MC 16 report MC errors from each
42AH
1066
IA32_MC10_ADDR
Package
channel of the integrated memory controllers.
42BH
1067
IA32_MC10_MISC
Package
42CH
1068
IA32_MC11_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
42DH
1069
IA32_MC11_STATUS
Package
Bank MC11 reports MC errors from a specific channel
of the integrated memory controller.
42EH
1070
IA32_MC11_ADDR
Package
42FH
1071
IA32_MC11_MISC
Package
430H
1072
IA32_MC12_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
431H
1073
IA32_MC12_STATUS
Package
Banks MC9 through MC 16 report MC errors from each
432H
1074
IA32_MC12_ADDR
Package
channel of the integrated memory controllers.
433H
1075
IA32_MC12_MISC
Package
434H
1076
IA32_MC13_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
435H
1077
IA32_MC13_STATUS
Package
Banks MC9 through MC 16 report MC errors from each
436H
1078
IA32_MC13_ADDR
Package
channel of the integrated memory controllers.
437H
1079
IA32_MC13_MISC
Package
438H
1080
IA32_MC14_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
439H
1081
IA32_MC14_STATUS
Package
Banks MC9 through MC 16 report MC errors from each
43AH
1082
IA32_MC14_ADDR
Package
channel of the integrated memory controllers.
43BH
1083
IA32_MC14_MISC
Package
2-218 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family Based on Ivy Bridge-E
Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
(Former MSR Name)
Hex
Dec
43CH
1084
IA32_MC15_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
43DH
1085
IA32_MC15_STATUS
Package
Banks MC9 through MC 16 report MC errors from each
43EH
1086
IA32_MC15_ADDR
Package
channel of the integrated memory controllers.
43FH
1087
IA32_MC15_MISC
Package
440H
1088
IA32_MC16_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
441H
1089
IA32_MC16_STATUS
Package
Banks MC9 through MC 16 report MC errors from each
442H
1090
IA32_MC16_ADDR
Package
channel of the integrated memory controllers.
443H
1091
IA32_MC16_MISC
Package
444H
1092
IA32_MC17_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
445H
1093
IA32_MC17_STATUS
Package
Bank MC17 reports MC errors from a specific CBo (core
446H
1094
IA32_MC17_ADDR
Package
broadcast) and its corresponding slice of L3.
447H
1095
IA32_MC17_MISC
Package
448H
1096
IA32_MC18_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
449H
1097
IA32_MC18_STATUS
Package
Bank MC18 reports MC errors from a specific CBo (core
44AH
1098
IA32_MC18_ADDR
Package
broadcast) and its corresponding slice of L3.
44BH
1099
IA32_MC18_MISC
Package
44CH
1100
IA32_MC19_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
44DH
1101
IA32_MC19_STATUS
Package
Bank MC19 reports MC errors from a specific CBo (core
44EH
1102
IA32_MC19_ADDR
Package
broadcast) and its corresponding slice of L3.
44FH
1103
IA32_MC19_MISC
Package
450H
1104
IA32_MC20_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
451H
1105
IA32_MC20_STATUS
Package
Bank MC20 reports MC errors from a specific CBo (core
broadcast) and its corresponding slice of L3.
452H
1106
IA32_MC20_ADDR
Package
453H
1107
IA32_MC20_MISC
Package
454H
1108
IA32_MC21_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
455H
1109
IA32_MC21_STATUS
Package
Bank MC21 reports MC errors from a specific CBo (core
456H
1110
IA32_MC21_ADDR
Package
broadcast) and its corresponding slice of L3.
457H
1111
IA32_MC21_MISC
Package
458H
1112
IA32_MC22_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
459H
1113
IA32_MC22_STATUS
Package
Bank MC22 reports MC errors from a specific CBo (core
45AH
1114
IA32_MC22_ADDR
Package
broadcast) and its corresponding slice of L3.
45BH
1115
IA32_MC22_MISC
Package
Vol. 4
2-219
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family Based on Ivy Bridge-E
Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
(Former MSR Name)
Hex
Dec
45CH
1116
IA32_MC23_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
45DH
1117
IA32_MC23_STATUS
Package
Bank MC23 reports MC errors from a specific CBo (core
45EH
1118
IA32_MC23_ADDR
Package
broadcast) and its corresponding slice of L3.
45FH
1119
IA32_MC23_MISC
Package
460H
1120
IA32_MC24_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
461H
1121
IA32_MC24_STATUS
Package
Bank MC24 reports MC errors from a specific CBo (core
462H
1122
IA32_MC24_ADDR
Package
broadcast) and its corresponding slice of L3.
463H
1123
IA32_MC24_MISC
Package
464H
1124
IA32_MC25_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
465H
1125
IA32_MC25_STATUS
Package
Bank MC25 reports MC errors from a specific CBo (core
466H
1126
IA32_MC25_ADDR
Package
broadcast) and its corresponding slice of L3.
467H
1127
IA32_MC2MISC
Package
468H
1128
IA32_MC26_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
469H
1129
IA32_MC26_STATUS
Package
Bank MC26 reports MC errors from a specific CBo (core
46AH
1130
IA32_MC26_ADDR
Package
broadcast) and its corresponding slice of L3.
46BH
1131
IA32_MC26_MISC
Package
46CH
1132
IA32_MC27_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
46DH
1133
IA32_MC27_STATUS
Package
Bank MC27 reports MC errors from a specific CBo (core
46EH
1134
IA32_MC27_ADDR
Package
broadcast) and its corresponding slice of L3.
46FH
1135
IA32_MC27_MISC
Package
470H
1136
IA32_MC28_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
471H
1137
IA32_MC28_STATUS
Package
Bank MC28 reports MC errors from a specific CBo (core
472H
1138
IA32_MC28_ADDR
Package
broadcast) and its corresponding slice of L3.
473H
1139
IA32_MC28_MISC
Package
613H
1555
MSR_PKG_PERF_STATUS
Package
Package RAPL Perf Status (R/O)
618H
1560
MSR_DRAM_POWER_LIMIT
Package
DRAM RAPL Power Limit Control (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
619H
1561
MSR_DRAM_ENERGY_STATUS
Package
DRAM Energy Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
61BH
1563
MSR_DRAM_PERF_STATUS
Package
DRAM Performance Throttling Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
61CH
1564
MSR_DRAM_POWER_INFO
Package
DRAM RAPL Parameters (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
639H
1593
MSR_PP0_ENERGY_STATUS
Package
PP0 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
2-220 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family Based on Ivy Bridge-E
Microarchitecture (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
(Former MSR Name)
Hex
Dec
See Table 2-20, for other MSR definitions applicable to Intel Xeon processor E5 v2 with a CPUID Signature
DisplayFamily_DisplayModel value of 06_3EH.
2.12.2 Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family
The Intel® Xeon® processor E7 v2 family (based on Ivy Bridge-E microarchitecture) with a CPUID Signature
DisplayFamily_DisplayModel value of 06_3EH supports the MSR interfaces listed in Table 2-20, Table 2-26, and
Table 2-27.
Table 2-27. Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_3EH
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
3AH
58
IA32_FEATURE_CONTROL
Thread
Control Features in Intel 64 Processor (R/W)
See Table 2-2.
0
Lock (R/WL)
1
Enable VMX Inside SMX Operation (R/WL)
2
Enable VMX Outside SMX Operation (R/WL)
14:8
SENTER Local Functions Enables (R/WL)
15
SENTER Global Functions Enable (R/WL)
63:16
Reserved
179H
377
IA32_MCG_CAP
Thread
Global Machine Check Capability (R/O)
7:0
Count
8
MCG_CTL_P
9
MCG_EXT_P
10
MCP_CMCI_P
11
MCG_TES_P
15:12
Reserved
23:16
MCG_EXT_CNT
24
MCG_SER_P
63:25
Reserved
17AH
378
IA32_MCG_STATUS
Thread
Global Machine Check Status (R/WO)
0
RIPV
1
EIPV
2
MCIP
3
LMCE Signaled
63:4
Reserved
Vol. 4
2-221
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-27. Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_3EH (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
1AEH
430
MSR_TURBO_RATIO_LIMIT1
Package
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0.
R/W if MSR_PLATFORM_INFO.[28] = 1.
7:0
Package
Maximum Ratio Limit for 9C
Maximum turbo ratio limit of 9 core active.
15:8
Package
Maximum Ratio Limit for 10C
Maximum turbo ratio limit of 10core active.
23:16
Package
Maximum Ratio Limit for 11C
Maximum turbo ratio limit of 11 core active.
31:24
Package
Maximum Ratio Limit for 12C
Maximum turbo ratio limit of 12 core active.
39:32
Package
Maximum Ratio Limit for 13C
Maximum turbo ratio limit of 13 core active.
47:40
Package
Maximum Ratio Limit for 14C
Maximum turbo ratio limit of 14 core active.
55:48
Package
Maximum Ratio Limit for 15C
Maximum turbo ratio limit of 15 core active.
62:56
Reserved
63
Package
Semaphore for Turbo Ratio Limit Configuration
If 1, the processor uses override configuration1 specified
in MSR_TURBO_RATIO_LIMIT and
MSR_TURBO_RATIO_LIMIT1.
If 0, the processor uses factory-set configuration
(Default).
29DH
669
IA32_MC29_CTL2
Package
See Table 2-2.
29EH
670
IA32_MC30_CTL2
Package
See Table 2-2.
29FH
671
IA32_MC31_CTL2
Package
See Table 2-2.
3F1H
1009
IA32_PEBS_ENABLE
Thread
See Section 20.3.1.1.1, “Processor Event Based Sampling
(PEBS).”
(MSR_PEBS_ENABLE)
n:0
Enable PEBS on IA32_PMCx. (R/W)
31:n+1
Reserved
32+m:32
Enable Load Latency on IA32_PMCx. (R/W)
63:33+m
Reserved
41BH
1051
IA32_MC6_MISC
Package
Misc MAC Information of Integrated I/O (R/O)
See Section 16.3.2.4.
5:0
Recoverable Address LSB
8:6
Address Mode
15:9
Reserved
31:16
PCI Express Requestor ID
2-222 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-27. Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_3EH (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
39:32
PCI Express Segment Number
63:32
Reserved
474H
1140
IA32_MC29_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
475H
1141
IA32_MC29_STATUS
Package
Bank MC29 reports MC errors from a specific CBo (core
476H
1142
IA32_MC29_ADDR
Package
broadcast) and its corresponding slice of L3.
477H
1143
IA32_MC29_MISC
Package
478H
1144
IA32_MC30_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
479H
1145
IA32_MC30_STATUS
Package
Bank MC30 reports MC errors from a specific CBo (core
47AH
1146
IA32_MC30_ADDR
Package
broadcast) and its corresponding slice of L3.
47BH
1147
IA32_MC30_MISC
Package
47CH
1148
IA32_MC31_CTL
Package
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through
Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
47DH
1149
IA32_MC31_STATUS
Package
Bank MC31 reports MC errors from a specific CBo (core
47EH
1150
IA32_MC31_ADDR
Package
broadcast) and its corresponding slice of L3.
47FH
1147
IA32_MC31_MISC
Package
See Table 2-20, Table 2-26 for other MSR definitions applicable to Intel Xeon processor E7 v2 with a CPUID Signature
DisplayFamily_DisplayModel value of 06_3AH.
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the
factory-set configuration is dependent on features specific to the processor and the platform.
2.12.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families
Intel Xeon Processor E5 v2 and E7 v2 families are based on the Ivy Bridge-E microarchitecture. The MSR-based
uncore PMU interfaces are listed in Table 2-24 and Table 2-28. For complete detail of the uncore PMU, refer to Intel
Xeon Processor E5 v2 Product Family Uncore Performance Monitoring Guide. These processors have a CPUID
Signature DisplayFamily_DisplayModel value of 06_3EH.
Table 2-28. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
C00H
3072
MSR_PMON_GLOBAL_CTL
Package
Uncore Perfmon Per-Socket Global Control
C01H
3073
MSR_PMON_GLOBAL_STATUS
Package
Uncore Perfmon Per-Socket Global Status
C06H
3078
MSR_PMON_GLOBAL_CONFIG
Package
Uncore Perfmon Per-Socket Global Configuration
C15H
3093
MSR_U_PMON_BOX_STATUS
Package
Uncore U-box Perfmon U-Box Wide Status
C35H
3125
MSR_PCU_PMON_BOX_STATUS
Package
Uncore PCU Perfmon Box Wide Status
D1AH
3354
MSR_C0_PMON_BOX_FILTER1
Package
Uncore C-Box 0 Perfmon Box Wide Filter1
D3AH
3386
MSR_C1_PMON_BOX_FILTER1
Package
Uncore C-Box 1 Perfmon Box Wide Filter1
Vol. 4
2-223
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-28. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families (Contd.)
Register
Address
Register Name / Bit Fields
Scope
Bit Description
Hex
Dec
D5AH
3418
MSR_C2_PMON_BOX_FILTER1
Package
Uncore C-Box 2 Perfmon Box Wide Filter1
D7AH
3450
MSR_C3_PMON_BOX_FILTER1
Package
Uncore C-Box 3 Perfmon Box Wide Filter1
D9AH
3482
MSR_C4_PMON_BOX_FILTER1
Package
Uncore C-Box 4 Perfmon Box Wide Filter1
DBAH
3514
MSR_C5_PMON_BOX_FILTER1
Package
Uncore C-Box 5 Perfmon Box Wide Filter1
DDAH
3546
MSR_C6_PMON_BOX_FILTER1
Package
Uncore C-Box 6 Perfmon Box Wide Filter1
DFAH
3578
MSR_C7_PMON_BOX_FILTER1
Package
Uncore C-Box 7 Perfmon Box Wide Filter1
E04H
3588
MSR_C8_PMON_BOX_CTL
Package
Uncore C-Box 8 Perfmon Local Box Wide Control
E10H
3600
MSR_C8_PMON_EVNTSEL0
Package
Uncore C-Box 8 Perfmon Event Select for C-Box 8
Counter 0
E11H
3601
MSR_C8_PMON_EVNTSEL1
Package
Uncore C-Box 8 Perfmon Event Select for C-Box 8
Counter 1
E12H
3602
MSR_C8_PMON_EVNTSEL2
Package
Uncore C-Box 8 Perfmon Event Select for C-Box 8
Counter 2
E13H
3603
MSR_C8_PMON_EVNTSEL3
Package
Uncore C-Box 8 Perfmon Event Select for C-Box 8
Counter 3
E14H
3604
MSR_C8_PMON_BOX_FILTER
Package
Uncore C-Box 8 Perfmon Box Wide Filter
E16H
3606
MSR_C8_PMON_CTR0
Package
Uncore C-Box 8 Perfmon Counter 0
E17H
3607
MSR_C8_PMON_CTR1
Package
Uncore C-Box 8 Perfmon Counter 1
E18H
3608
MSR_C8_PMON_CTR2
Package
Uncore C-Box 8 Perfmon Counter 2
E19H
3609
MSR_C8_PMON_CTR3
Package
Uncore C-Box 8 Perfmon Counter 3
E1AH
3610
MSR_C8_PMON_BOX_FILTER1
Package
Uncore C-Box 8 Perfmon Box Wide Filter1
E24H
3620
MSR_C9_PMON_BOX_CTL
Package
Uncore C-Box 9 Perfmon Local Box Wide Control
E30H
3632
MSR_C9_PMON_EVNTSEL0
Package
Uncore C-Box 9 Perfmon Event Select for C-box 9
Counter 0
E31H
3633
MSR_C9_PMON_EVNTSEL1
Package
Uncore C-Box 9 Perfmon Event Select for C-box 9
Counter 1
E32H
3634
MSR_C9_PMON_EVNTSEL2
Package
Uncore C-Box 9 Perfmon Event Select for C-box 9
Counter 2
E33H
3635
MSR_C9_PMON_EVNTSEL3
Package
Uncore C-Box 9 Perfmon Event Select for C-box 9
Counter 3
E34H
3636
MSR_C9_PMON_BOX_FILTER
Package
Uncore C-Box 9 Perfmon Box Wide Filter
E36H
3638
MSR_C9_PMON_CTR0
Package
Uncore C-Box 9 Perfmon Counter 0
E37H
3639
MSR_C9_PMON_CTR1
Package
Uncore C-Box 9 Perfmon Counter 1
E38H
3640
MSR_C9_PMON_CTR2
Package
Uncore C-Box 9 Perfmon Counter 2
E39H
3641
MSR_C9_PMON_CTR3
Package
Uncore C-Box 9 Perfmon Counter 3
E3AH
3642
MSR_C9_PMON_BOX_FILTER1
Package
Uncore C-Box 9 Perfmon Box Wide Filter1
E44H
3652
MSR_C10_PMON_BOX_CTL
Package
Uncore C-Box 10 Perfmon Local Box Wide Control
E50H
3664
MSR_C10_PMON_EVNTSEL0
Package
Uncore C-Box 10 Perfmon Event Select for C-Box
10 Counter 0
2-224 Vol. 4

 

 

 

 

 

 

 

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