Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

INSTRUCTION SET REFERENCE, M-U

PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F EC /r¹

V/V

MMX

Add packed signed byte integers from

mm/m64 and mm and saturate the results.

PADDSB mm, mm/m64

66 0F EC /r

V/V

SSE2

Add packed signed byte integers from

xmm2/m128 and xmm1 saturate the results.

PADDSB xmm1, xmm2/m128

NP 0F ED /r¹

V/V

MMX

Add packed signed word integers from

mm/m64 and mm and saturate the results.

PADDSW mm, mm/m64

66 0F ED /r

V/V

SSE2

Add packed signed word integers from

xmm2/m128 and xmm1 and saturate the

PADDSW xmm1, xmm2/m128

results.

VEX.128.66.0F.WIG EC /r

V/V

AVX

Add packed signed byte integers from

VPADDSB xmm1, xmm2, xmm3/m128

xmm3/m128 and xmm2 saturate the results.

VEX.128.66.0F.WIG ED /r

V/V

AVX

Add packed signed word integers from

xmm3/m128 and xmm2 and saturate the

VPADDSW xmm1, xmm2, xmm3/m128

results.

VEX.256.66.0F.WIG EC /r

V/V

AVX2

Add packed signed byte integers from ymm2,

VPADDSB ymm1, ymm2, ymm3/m256

and ymm3/m256 and store the saturated

results in ymm1.

VEX.256.66.0F.WIG ED /r

V/V

AVX2

Add packed signed word integers from ymm2,

and ymm3/m256 and store the saturated

VPADDSW ymm1, ymm2, ymm3/m256

results in ymm1.

EVEX.128.66.0F.WIG EC /r

V/V

AVX512VL

Add packed signed byte integers from xmm2,

VPADDSB xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

and xmm3/m128 and store the saturated

results in xmm1 under writemask k1.

EVEX.256.66.0F.WIG EC /r

V/V

AVX512VL

Add packed signed byte integers from ymm2,

VPADDSB ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

and ymm3/m256 and store the saturated

results in ymm1 under writemask k1.

EVEX.512.66.0F.WIG EC /r

V/V

AVX512BW

Add packed signed byte integers from zmm2,

VPADDSB zmm1 {k1}{z}, zmm2, zmm3/m512

and zmm3/m512 and store the saturated

results in zmm1 under writemask k1.

EVEX.128.66.0F.WIG ED /r

V/V

AVX512VL

Add packed signed word integers from xmm2,

VPADDSW xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

and xmm3/m128 and store the saturated

results in xmm1 under writemask k1.

EVEX.256.66.0F.WIG ED /r

V/V

AVX512VL

Add packed signed word integers from ymm2,

VPADDSW ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

and ymm3/m256 and store the saturated

results in ymm1 under writemask k1.

EVEX.512.66.0F.WIG ED /r

V/V

AVX512BW

Add packed signed word integers from zmm2,

VPADDSW zmm1 {k1}{z}, zmm2, zmm3/m512

and zmm3/m512 and store the saturated

results in zmm1 under writemask k1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation

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INSTRUCTION SET REFERENCE, M-U

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a SIMD add of the packed signed integers from the source operand (second operand) and the destination

operand (first operand), and stores the packed integer results in the destination operand. See Figure 9-4 in the

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a SIMD operation.

Overflow is handled with signed saturation, as described in the following paragraphs.

(V)PADDSB performs a SIMD add of the packed signed integers with saturation from the first source operand and

second source operand and stores the packed integer results in the destination operand. When an individual byte

result is beyond the range of a signed byte integer (that is, greater than 7FH or less than 80H), the saturated value

of 7FH or 80H, respectively, is written to the destination operand.

(V)PADDSW performs a SIMD add of the packed signed word integers with saturation from the first source operand

and second source operand and stores the packed integer results in the destination operand. When an individual

word result is beyond the range of a signed word integer (that is, greater than 7FFFH or less than 8000H), the satu-

rated value of 7FFFH or 8000H, respectively, is written to the destination operand.

EVEX encoded versions: The first source operand is an ZMM/YMM/XMM register. The second source operand is an

ZMM/YMM/XMM register or a memory location. The destination operand is an ZMM/YMM/XMM register.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding register destination are zeroed.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (MAXVL-1:128) of the corresponding register destination are unmodified.

Operation

PADDSB (with 64-bit operands)

DEST[7:0] := SaturateToSignedByte(DEST[7:0] + SRC (7:0]);

(* Repeat add operation for 2nd through 7th bytes *)

DEST[63:56] := SaturateToSignedByte(DEST[63:56] + SRC[63:56] );

PADDSB (with 128-bit operands)

DEST[7:0] := SaturateToSignedByte (DEST[7:0] + SRC[7:0]);

(* Repeat add operation for 2nd through 14th bytes *)

DEST[127:120] := SaturateToSignedByte (DEST[111:120] + SRC[127:120]);

VPADDSB (VEX.128 encoded version)

DEST[7:0] := SaturateToSignedByte (SRC1[7:0] + SRC2[7:0]);

(* Repeat subtract operation for 2nd through 14th bytes *)

DEST[127:120] := SaturateToSignedByte (SRC1[111:120] + SRC2[127:120]);

DEST[MAXVL-1:128] := 0

VPADDSB (VEX.256 encoded version)

DEST[7:0] := SaturateToSignedByte (SRC1[7:0] + SRC2[7:0]);

(* Repeat add operation for 2nd through 31st bytes *)

DEST[255:248] := SaturateToSignedByte (SRC1[255:248] + SRC2[255:248]);

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PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation

INSTRUCTION SET REFERENCE, M-U

VPADDSB (EVEX encoded versions)

(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j := 0 TO KL-1

i := j * 8

IF k1[j] OR *no writemask*

THEN DEST[i+7:i] := SaturateToSignedByte (SRC1[i+7:i] + SRC2[i+7:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+7:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+7:i] = 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

PADDSW (with 64-bit operands)

DEST[15:0] := SaturateToSignedWord(DEST[15:0] + SRC[15:0] );

(* Repeat add operation for 2nd and 7th words *)

DEST[63:48] := SaturateToSignedWord(DEST[63:48] + SRC[63:48] );

PADDSW (with 128-bit operands)

DEST[15:0] := SaturateToSignedWord (DEST[15:0] + SRC[15:0]);

(* Repeat add operation for 2nd through 7th words *)

DEST[127:112] := SaturateToSignedWord (DEST[127:112] + SRC[127:112]);

VPADDSW (VEX.128 encoded version)

DEST[15:0] := SaturateToSignedWord (SRC1[15:0] + SRC2[15:0]);

(* Repeat subtract operation for 2nd through 7th words *)

DEST[127:112] := SaturateToSignedWord (SRC1[127:112] + SRC2[127:112]);

DEST[MAXVL-1:128] := 0

VPADDSW (VEX.256 encoded version)

DEST[15:0] := SaturateToSignedWord (SRC1[15:0] + SRC2[15:0]);

(* Repeat add operation for 2nd through 15th words *)

DEST[255:240] := SaturateToSignedWord (SRC1[255:240] + SRC2[255:240])

VPADDSW (EVEX encoded versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := SaturateToSignedWord (SRC1[i+15:i] + SRC2[i+15:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] = 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation

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INSTRUCTION SET REFERENCE, M-U

Intel C/C++ Compiler Intrinsic Equivalents

PADDSB:

__m64 _mm_adds_pi8(__m64 m1, __m64 m2)

(V)PADDSB:

__m128i _mm_adds_epi8 ( __m128i a, __m128i b)

VPADDSB:

__m256i _mm256_adds_epi8 ( __m256i a, __m256i b)

PADDSW:

__m64 _mm_adds_pi16(__m64 m1, __m64 m2)

(V)PADDSW:

__m128i _mm_adds_epi16 ( __m128i a, __m128i b)

VPADDSW:

__m256i _mm256_adds_epi16 ( __m256i a, __m256i b)

VPADDSB__m512i _mm512_adds_epi8 ( __m512i a, __m512i b)

VPADDSW__m512i _mm512_adds_epi16 ( __m512i a, __m512i b)

VPADDSB__m512i _mm512_mask_adds_epi8 ( __m512i s, __mmask64 m, __m512i a, __m512i b)

VPADDSW__m512i _mm512_mask_adds_epi16 ( __m512i s, __mmask32 m, __m512i a, __m512i b)

VPADDSB__m512i _mm512_maskz_adds_epi8 (__mmask64 m, __m512i a, __m512i b)

VPADDSW__m512i _mm512_maskz_adds_epi16 (__mmask32 m, __m512i a, __m512i b)

VPADDSB__m256i _mm256_mask_adds_epi8 (__m256i s, __mmask32 m, __m256i a, __m256i b)

VPADDSW__m256i _mm256_mask_adds_epi16 (__m256i s, __mmask16 m, __m256i a, __m256i b)

VPADDSB__m256i _mm256_maskz_adds_epi8 (__mmask32 m, __m256i a, __m256i b)

VPADDSW__m256i _mm256_maskz_adds_epi16 (__mmask16 m, __m256i a, __m256i b)

VPADDSB__m128i _mm_mask_adds_epi8 (__m128i s, __mmask16 m, __m128i a, __m128i b)

VPADDSW__m128i _mm_mask_adds_epi16 (__m128i s, __mmask8 m, __m128i a, __m128i b)

VPADDSB__m128i _mm_maskz_adds_epi8 (__mmask16 m, __m128i a, __m128i b)

VPADDSW__m128i _mm_maskz_adds_epi16 (__mmask8 m, __m128i a, __m128i b)

Flags Affected

None.

SIMD Floating-Point Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions”.

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PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation

INSTRUCTION SET REFERENCE, M-U

PADDUSB/PADDUSW—Add Packed Unsigned Integers With Unsigned Saturation

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature Flag

Support

NP 0F DC /r¹

V/V

MMX

Add packed unsigned byte integers from

mm/m64 and mm and saturate the results.

PADDUSB mm, mm/m64

66 0F DC /r

V/V

SSE2

Add packed unsigned byte integers from

xmm2/m128 and xmm1 saturate the results.

PADDUSB xmm1, xmm2/m128

NP 0F DD /r¹

V/V

MMX

Add packed unsigned word integers from

mm/m64 and mm and saturate the results.

PADDUSW mm, mm/m64

66 0F DD /r

V/V

SSE2

Add packed unsigned word integers from

xmm2/m128 to xmm1 and saturate the

PADDUSW xmm1, xmm2/m128

results.

VEX.128.660F.WIG DC /r

V/V

AVX

Add packed unsigned byte integers from

xmm3/m128 to xmm2 and saturate the

VPADDUSB xmm1, xmm2, xmm3/m128

results.

VEX.128.66.0F.WIG DD /r

V/V

AVX

Add packed unsigned word integers from

xmm3/m128 to xmm2 and saturate the

VPADDUSW xmm1, xmm2, xmm3/m128

results.

VEX.256.66.0F.WIG DC /r

V/V

AVX2

Add packed unsigned byte integers from

VPADDUSB ymm1, ymm2, ymm3/m256

ymm2, and ymm3/m256 and store the

saturated results in ymm1.

VEX.256.66.0F.WIG DD /r

V/V

AVX2

Add packed unsigned word integers from

VPADDUSW ymm1, ymm2, ymm3/m256

ymm2, and ymm3/m256 and store the

saturated results in ymm1.

EVEX.128.66.0F.WIG DC /r

V/V

AVX512VL

Add packed unsigned byte integers from

VPADDUSB xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

xmm2, and xmm3/m128 and store the

saturated results in xmm1 under writemask

k1.

EVEX.256.66.0F.WIG DC /r

V/V

AVX512VL

Add packed unsigned byte integers from

VPADDUSB ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

ymm2, and ymm3/m256 and store the

saturated results in ymm1 under writemask

k1.

EVEX.512.66.0F.WIG DC /r

V/V

AVX512BW

Add packed unsigned byte integers from

VPADDUSB zmm1 {k1}{z}, zmm2, zmm3/m512

zmm2, and zmm3/m512 and store the

saturated results in zmm1 under writemask

k1.

EVEX.128.66.0F.WIG DD /r

V/V

AVX512VL

Add packed unsigned word integers from

VPADDUSW xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

xmm2, and xmm3/m128 and store the

saturated results in xmm1 under writemask

k1.

EVEX.256.66.0F.WIG DD /r

V/V

AVX512VL

Add packed unsigned word integers from

VPADDUSW ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

ymm2, and ymm3/m256 and store the

saturated results in ymm1 under writemask

k1.

EVEX.512.66.0F.WIG DD /r

V/V

AVX512BW

Add packed unsigned word integers from

VPADDUSW zmm1 {k1}{z}, zmm2, zmm3/m512

zmm2, and zmm3/m512 and store the

saturated results in zmm1 under writemask

k1.

PADDUSB/PADDUSW—Add Packed Unsigned Integers With Unsigned Saturation

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INSTRUCTION SET REFERENCE, M-U

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a SIMD add of the packed unsigned integers from the source operand (second operand) and the destina-

tion operand (first operand), and stores the packed integer results in the destination operand. See Figure 9-4 in the

Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustration of a SIMD operation.

Overflow is handled with unsigned saturation, as described in the following paragraphs.

(V)PADDUSB performs a SIMD add of the packed unsigned integers with saturation from the first source operand

and second source operand and stores the packed integer results in the destination operand. When an individual

byte result is beyond the range of an unsigned byte integer (that is, greater than FFH), the saturated value of FFH

is written to the destination operand.

(V)PADDUSW performs a SIMD add of the packed unsigned word integers with saturation from the first source

operand and second source operand and stores the packed integer results in the destination operand. When an

individual word result is beyond the range of an unsigned word integer (that is, greater than FFFFH), the saturated

value of FFFFH is written to the destination operand.

EVEX encoded versions: The first source operand is an ZMM/YMM/XMM register. The second source operand is an

ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination is an ZMM/YMM/XMM register.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM

the corresponding destination register destination are zeroed.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (MAXVL-1:128) of the corresponding register destination are unmodified.

Operation

PADDUSB (with 64-bit operands)

DEST[7:0] := SaturateToUnsignedByte(DEST[7:0] + SRC (7:0] );

(* Repeat add operation for 2nd through 7th bytes *)

DEST[63:56] := SaturateToUnsignedByte(DEST[63:56] + SRC[63:56]

PADDUSB (with 128-bit operands)

DEST[7:0] := SaturateToUnsignedByte (DEST[7:0] + SRC[7:0]);

(* Repeat add operation for 2nd through 14th bytes *)

DEST[127:120] := SaturateToUnSignedByte (DEST[127:120] + SRC[127:120]);

VPADDUSB (VEX.128 encoded version)

DEST[7:0] := SaturateToUnsignedByte (SRC1[7:0] + SRC2[7:0]);

(* Repeat subtract operation for 2nd through 14th bytes *)

DEST[127:120] := SaturateToUnsignedByte (SRC1[111:120] + SRC2[127:120]);

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PADDUSB/PADDUSW—Add Packed Unsigned Integers With Unsigned Saturation

INSTRUCTION SET REFERENCE, M-U

DEST[MAXVL-1:128] := 0

VPADDUSB (VEX.256 encoded version)

DEST[7:0] := SaturateToUnsignedByte (SRC1[7:0] + SRC2[7:0]);

(* Repeat add operation for 2nd through 31st bytes *)

DEST[255:248] := SaturateToUnsignedByte (SRC1[255:248] + SRC2[255:248]);

PADDUSW (with 64-bit operands)

DEST[15:0] := SaturateToUnsignedWord(DEST[15:0] + SRC[15:0] );

(* Repeat add operation for 2nd and 3rd words *)

DEST[63:48] := SaturateToUnsignedWord(DEST[63:48] + SRC[63:48] );

PADDUSW (with 128-bit operands)

DEST[15:0] := SaturateToUnsignedWord (DEST[15:0] + SRC[15:0]);

(* Repeat add operation for 2nd through 7th words *)

DEST[127:112] := SaturateToUnSignedWord (DEST[127:112] + SRC[127:112]);

VPADDUSW (VEX.128 encoded version)

DEST[15:0] := SaturateToUnsignedWord (SRC1[15:0] + SRC2[15:0]);

(* Repeat subtract operation for 2nd through 7th words *)

DEST[127:112] := SaturateToUnsignedWord (SRC1[127:112] + SRC2[127:112]);

DEST[MAXVL-1:128] := 0

VPADDUSW (VEX.256 encoded version)

DEST[15:0] := SaturateToUnsignedWord (SRC1[15:0] + SRC2[15:0]);

(* Repeat add operation for 2nd through 15th words *)

DEST[255:240] := SaturateToUnsignedWord (SRC1[255:240] + SRC2[255:240])

VPADDUSB (EVEX encoded versions)

(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j := 0 TO KL-1

i := j * 8

IF k1[j] OR *no writemask*

THEN DEST[i+7:i] := SaturateToUnsignedByte (SRC1[i+7:i] + SRC2[i+7:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+7:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+7:i] = 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

PADDUSB/PADDUSW—Add Packed Unsigned Integers With Unsigned Saturation

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4-223

INSTRUCTION SET REFERENCE, M-U

VPADDUSW (EVEX encoded versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := SaturateToUnsignedWord (SRC1[i+15:i] + SRC2[i+15:i])

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] = 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalents

PADDUSB:

__m64 _mm_adds_pu8(__m64 m1, __m64 m2)

PADDUSW:

__m64 _mm_adds_pu16(__m64 m1, __m64 m2)

(V)PADDUSB:

__m128i _mm_adds_epu8 ( __m128i a, __m128i b)

(V)PADDUSW:

__m128i _mm_adds_epu16 ( __m128i a, __m128i b)

VPADDUSB:

__m256i _mm256_adds_epu8 ( __m256i a, __m256i b)

VPADDUSW:

__m256i _mm256_adds_epu16 ( __m256i a, __m256i b)

VPADDUSB__m512i _mm512_adds_epu8 ( __m512i a, __m512i b)

VPADDUSW__m512i _mm512_adds_epu16 ( __m512i a, __m512i b)

VPADDUSB__m512i _mm512_mask_adds_epu8 ( __m512i s, __mmask64 m, __m512i a, __m512i b)

VPADDUSW__m512i _mm512_mask_adds_epu16 ( __m512i s, __mmask32 m, __m512i a, __m512i b)

VPADDUSB__m512i _mm512_maskz_adds_epu8 (__mmask64 m, __m512i a, __m512i b)

VPADDUSW__m512i _mm512_maskz_adds_epu16 (__mmask32 m, __m512i a, __m512i b)

VPADDUSB__m256i _mm256_mask_adds_epu8 (__m256i s, __mmask32 m, __m256i a, __m256i b)

VPADDUSW__m256i _mm256_mask_adds_epu16 (__m256i s, __mmask16 m, __m256i a, __m256i b)

VPADDUSB__m256i _mm256_maskz_adds_epu8 (__mmask32 m, __m256i a, __m256i b)

VPADDUSW__m256i _mm256_maskz_adds_epu16 (__mmask16 m, __m256i a, __m256i b)

VPADDUSB__m128i _mm_mask_adds_epu8 (__m128i s, __mmask16 m, __m128i a, __m128i b)

VPADDUSW__m128i _mm_mask_adds_epu16 (__m128i s, __mmask8 m, __m128i a, __m128i b)

VPADDUSB__m128i _mm_maskz_adds_epu8 (__mmask16 m, __m128i a, __m128i b)

VPADDUSW__m128i _mm_maskz_adds_epu16 (__mmask8 m, __m128i a, __m128i b)

Flags Affected

None.

Numeric Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions”.

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PADDUSB/PADDUSW—Add Packed Unsigned Integers With Unsigned Saturation

INSTRUCTION SET REFERENCE, M-U

PALIGNR—Packed Align Right

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F 3A 0F /r ib¹

V/V

SSSE3

Concatenate destination and source operands,

extract byte-aligned result shifted to the right by

PALIGNR mm1, mm2/m64, imm8

constant value in imm8 into mm1.

66 0F 3A 0F /r ib

V/V

SSSE3

Concatenate destination and source operands,

extract byte-aligned result shifted to the right by

PALIGNR xmm1, xmm2/m128, imm8

constant value in imm8 into xmm1.

VEX.128.66.0F3A.WIG 0F /r ib

V/V

AVX

Concatenate xmm2 and xmm3/m128, extract

byte aligned result shifted to the right by

VPALIGNR xmm1, xmm2, xmm3/m128, imm8

constant value in imm8 and result is stored in

xmm1.

VEX.256.66.0F3A.WIG 0F /r ib

V/V

AVX2

Concatenate pairs of 16 bytes in ymm2 and

ymm3/m256 into 32-byte intermediate result,

VPALIGNR ymm1, ymm2, ymm3/m256, imm8

extract byte-aligned, 16-byte result shifted to

the right by constant values in imm8 from each

intermediate result, and two 16-byte results are

stored in ymm1.

EVEX.128.66.0F3A.WIG 0F /r ib

V/V

AVX512VL

Concatenate xmm2 and xmm3/m128 into a 32-

VPALIGNR xmm1 {k1}{z}, xmm2, xmm3/m128,

AVX512BW

byte intermediate result, extract byte aligned

imm8

result shifted to the right by constant value in

imm8 and result is stored in xmm1.

EVEX.256.66.0F3A.WIG 0F /r ib

V/V

AVX512VL

Concatenate pairs of 16 bytes in ymm2 and

VPALIGNR ymm1 {k1}{z}, ymm2, ymm3/m256,

AVX512BW

ymm3/m256 into 32-byte intermediate result,

imm8

extract byte-aligned, 16-byte result shifted to

the right by constant values in imm8 from each

intermediate result, and two 16-byte results are

stored in ymm1.

EVEX.512.66.0F3A.WIG 0F /r ib

V/V

AVX512BW

Concatenate pairs of 16 bytes in zmm2 and

VPALIGNR zmm1 {k1}{z}, zmm2, zmm3/m512,

zmm3/m512 into 32-byte intermediate result,

imm8

extract byte-aligned, 16-byte result shifted to

the right by constant values in imm8 from each

intermediate result, and four 16-byte results are

stored in zmm1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

imm8

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

(V)PALIGNR concatenates the destination operand (the first operand) and the source operand (the second

operand) into an intermediate composite, shifts the composite at byte granularity to the right by a constant imme-

diate, and extracts the right-aligned result into the destination. The first and the second operands can be an MMX,

PALIGNR—Packed Align Right

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INSTRUCTION SET REFERENCE, M-U

XMM or a YMM register. The immediate value is considered unsigned. Immediate shift counts larger than the 2L

(i.e., 32 for 128-bit operands, or 16 for 64-bit operands) produce a zero result. Both operands can be MMX regis-

ters, XMM registers or YMM registers. When the source operand is a 128-bit memory operand, the operand must

be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.

In 64-bit mode and not encoded by VEX/EVEX prefix, use the REX prefix to access additional registers.

128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.

EVEX.512 encoded version: The first source operand is a ZMM register and contains four 16-byte blocks. The

second source operand is a ZMM register or a 512-bit memory location containing four 16-byte block. The destina-

tion operand is a ZMM register and contain four 16-byte results. The imm8[7:0] is the common shift count

used for each of the four successive 16-byte block sources. The low 16-byte block of the two source operands

produce the low 16-byte result of the destination operand, the high 16-byte block of the two source operands

produce the high 16-byte result of the destination operand and so on for the blocks in the middle.

VEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register and contains two 16-byte

blocks. The second source operand is a YMM register or a 256-bit memory location containing two 16-byte block.

The destination operand is a YMM register and contain two 16-byte results. The imm8[7:0] is the common shift

count used for the two lower 16-byte block sources and the two upper 16-byte block sources. The low 16-byte

block of the two source operands produce the low 16-byte result of the destination operand, the high 16-byte block

of the two source operands produce the high 16-byte result of the destination operand. The upper bits (MAXVL-

1:256) of the corresponding ZMM register destination are zeroed.

VEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand

is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-

1:128) of the corresponding ZMM register destination are zeroed.

Concatenation is done with 128-bit data in the first and second source operand for both 128-bit and 256-bit

instructions. The high 128-bits of the intermediate composite 256-bit result came from the 128-bit data from the

first source operand; the low 128-bits of the intermediate result came from the 128-bit data of the second source

operand.

127

SRC1

SRC2

Imm8[7:0]*8

255

128

255

128

SRC1

SRC2

Imm8[7:0]*8

255

128

127

DEST

Figure 4-7. 256-bit VPALIGN Instruction Operation

Operation

PALIGNR (with 64-bit operands)

temp1[127:0] = CONCATENATE(DEST,SRC)>>(imm8*8)

DEST[63:0] = temp1[63:0]

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PALIGNR—Packed Align Right

INSTRUCTION SET REFERENCE, M-U

PALIGNR (with 128-bit operands)

temp1[255:0] := ((DEST[127:0] << 128) OR SRC[127:0])>>(imm8*8);

DEST[127:0] := temp1[127:0]

DEST[MAXVL-1:128] (Unmodified)

VPALIGNR (VEX.128 encoded version)

temp1[255:0] := ((SRC1[127:0] << 128) OR SRC2[127:0])>>(imm8*8);

DEST[127:0] := temp1[127:0]

DEST[MAXVL-1:128] := 0

VPALIGNR (VEX.256 encoded version)

temp1[255:0] := ((SRC1[127:0] << 128) OR SRC2[127:0])>>(imm8[7:0]*8);

DEST[127:0] := temp1[127:0]

temp1[255:0] := ((SRC1[255:128] << 128) OR SRC2[255:128])>>(imm8[7:0]*8);

DEST[MAXVL-1:128] := temp1[127:0]

VPALIGNR (EVEX encoded versions)

(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR l := 0 TO VL-1 with increments of 128

temp1[255:0] := ((SRC1[l+127:l] << 128) OR SRC2[l+127:l])>>(imm8[7:0]*8);

TMP_DEST[l+127:l] := temp1[127:0]

ENDFOR;

FOR j := 0 TO KL-1

i := j * 8

IF k1[j] OR *no writemask*

THEN DEST[i+7:i] := TMP_DEST[i+7:i]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+7:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+7:i] = 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalents

PALIGNR:

__m64 _mm_alignr_pi8 (__m64 a, __m64 b, int n)

(V)PALIGNR:

__m128i _mm_alignr_epi8 (__m128i a, __m128i b, int n)

VPALIGNR:

__m256i _mm256_alignr_epi8 (__m256i a, __m256i b, const int n)

VPALIGNR __m512i _mm512_alignr_epi8 (__m512i a, __m512i b, const int n)

VPALIGNR __m512i _mm512_mask_alignr_epi8 (__m512i s, __mmask64 m, __m512i a, __m512i b, const int n)

VPALIGNR __m512i _mm512_maskz_alignr_epi8 ( __mmask64 m, __m512i a, __m512i b, const int n)

VPALIGNR __m256i _mm256_mask_alignr_epi8 (__m256i s, __mmask32 m, __m256i a, __m256i b, const int n)

VPALIGNR __m256i _mm256_maskz_alignr_epi8 (__mmask32 m, __m256i a, __m256i b, const int n)

VPALIGNR __m128i _mm_mask_alignr_epi8 (__m128i s, __mmask16 m, __m128i a, __m128i b, const int n)

VPALIGNR __m128i _mm_maskz_alignr_epi8 (__mmask16 m, __m128i a, __m128i b, const int n)

SIMD Floating-Point Exceptions

None.

PALIGNR—Packed Align Right

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INSTRUCTION SET REFERENCE, M-U

PAND—Logical AND

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature Flag

Support

NP 0F DB /r¹

V/V

MMX

Bitwise AND mm/m64 and mm.

PAND mm, mm/m64

66 0F DB /r

V/V

SSE2

Bitwise AND of xmm2/m128 and xmm1.

PAND xmm1, xmm2/m128

VEX.128.66.0F.WIG DB /r

V/V

AVX

Bitwise AND of xmm3/m128 and xmm.

VPAND xmm1, xmm2, xmm3/m128

VEX.256.66.0F.WIG DB /r

V/V

AVX2

Bitwise AND of ymm2, and ymm3/m256 and

store result in ymm1.

VPAND ymm1, ymm2, ymm3/.m256

EVEX.128.66.0F.W0 DB /r

V/V

AVX512VL

Bitwise AND of packed doubleword integers in

VPANDD xmm1 {k1}{z}, xmm2,

AVX512F

xmm2 and xmm3/m128/m32bcst and store

xmm3/m128/m32bcst

result in xmm1 using writemask k1.

EVEX.256.66.0F.W0 DB /r

V/V

AVX512VL

Bitwise AND of packed doubleword integers in

VPANDD ymm1 {k1}{z}, ymm2,

AVX512F

ymm2 and ymm3/m256/m32bcst and store

ymm3/m256/m32bcst

result in ymm1 using writemask k1.

EVEX.512.66.0F.W0 DB /r

V/V

AVX512F

Bitwise AND of packed doubleword integers in

VPANDD zmm1 {k1}{z}, zmm2,

zmm2 and zmm3/m512/m32bcst and store

zmm3/m512/m32bcst

result in zmm1 using writemask k1.

EVEX.128.66.0F.W1 DB /r

V/V

AVX512VL

Bitwise AND of packed quadword integers in

VPANDQ xmm1 {k1}{z}, xmm2,

AVX512F

xmm2 and xmm3/m128/m64bcst and store

xmm3/m128/m64bcst

result in xmm1 using writemask k1.

EVEX.256.66.0F.W1 DB /r

V/V

AVX512VL

Bitwise AND of packed quadword integers in

VPANDQ ymm1 {k1}{z}, ymm2,

AVX512F

ymm2 and ymm3/m256/m64bcst and store

ymm3/m256/m64bcst

result in ymm1 using writemask k1.

EVEX.512.66.0F.W1 DB /r

V/V

AVX512F

Bitwise AND of packed quadword integers in

VPANDQ zmm1 {k1}{z}, zmm2,

zmm2 and zmm3/m512/m64bcst and store

zmm3/m512/m64bcst

result in zmm1 using writemask k1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a bitwise logical AND operation on the first source operand and second source operand and stores the

result in the destination operand. Each bit of the result is set to 1 if the corresponding bits of the first and second

operands are 1, otherwise it is set to 0.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

PAND—Logical AND

Vol. 2B

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INSTRUCTION SET REFERENCE, M-U

Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The

destination operand can be an MMX technology register.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified.

EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be

a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a

32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with

writemask k1 at 32/64-bit granularity.

VEX.256 encoded versions: The first source operand is a YMM register. The second source operand is a YMM

the corresponding ZMM register destination are zeroed.

VEX.128 encoded versions: The first source operand is an XMM register. The second source operand is an XMM

the corresponding ZMM register destination are zeroed.

Operation

PAND (64-bit operand)

DEST := DEST AND SRC

PAND (128-bit Legacy SSE version)

DEST := DEST AND SRC

DEST[MAXVL-1:128] (Unmodified)

VPAND (VEX.128 encoded version)

DEST := SRC1 AND SRC2

DEST[MAXVL-1:128] := 0

VPAND (VEX.256 encoded instruction)

DEST[255:0] := (SRC1[255:0] AND SRC2[255:0])

DEST[MAXVL-1:256] := 0

VPANDD (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN DEST[i+31:i] := SRC1[i+31:i] BITWISE AND SRC2[31:0]

ELSE DEST[i+31:i] := SRC1[i+31:i] BITWISE AND SRC2[i+31:i]

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

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PAND—Logical AND

INSTRUCTION SET REFERENCE, M-U

VPANDQ (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN DEST[i+63:i] := SRC1[i+63:i] BITWISE AND SRC2[63:0]

ELSE DEST[i+63:i] := SRC1[i+63:i] BITWISE AND SRC2[i+63:i]

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalents

VPANDD __m512i _mm512_and_epi32( __m512i a, __m512i b);

VPANDD __m512i _mm512_mask_and_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);

VPANDD __m512i _mm512_maskz_and_epi32( __mmask16 k, __m512i a, __m512i b);

VPANDQ __m512i _mm512_and_epi64( __m512i a, __m512i b);

VPANDQ __m512i _mm512_mask_and_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);

VPANDQ __m512i _mm512_maskz_and_epi64( __mmask8 k, __m512i a, __m512i b);

VPANDND __m256i _mm256_mask_and_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);

VPANDND __m256i _mm256_maskz_and_epi32( __mmask8 k, __m256i a, __m256i b);

VPANDND __m128i _mm_mask_and_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);

VPANDND __m128i _mm_maskz_and_epi32( __mmask8 k, __m128i a, __m128i b);

VPANDNQ __m256i _mm256_mask_and_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);

VPANDNQ __m256i _mm256_maskz_and_epi64( __mmask8 k, __m256i a, __m256i b);

VPANDNQ __m128i _mm_mask_and_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);

VPANDNQ __m128i _mm_maskz_and_epi64( __mmask8 k, __m128i a, __m128i b);

PAND:

__m64 _mm_and_si64 (__m64 m1, __m64 m2)

(V)PAND:__m128i _mm_and_si128 ( __m128i a, __m128i b)

VPAND:

__m256i _mm256_and_si256 ( __m256i a, __m256i b)

Flags Affected

None.

Numeric Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions”.

PAND—Logical AND

Vol. 2B

4-231

INSTRUCTION SET REFERENCE, M-U

PANDN—Logical AND NOT

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F DF /r¹

V/V

MMX

Bitwise AND NOT of mm/m64 and mm.

PANDN mm, mm/m64

66 0F DF /r

V/V

SSE2

Bitwise AND NOT of xmm2/m128 and xmm1.

PANDN xmm1, xmm2/m128

VEX.128.66.0F.WIG DF /r

V/V

AVX

Bitwise AND NOT of xmm3/m128 and xmm2.

VPANDN xmm1, xmm2, xmm3/m128

VEX.256.66.0F.WIG DF /r

V/V

AVX2

Bitwise AND NOT of ymm2, and ymm3/m256

and store result in ymm1.

VPANDN ymm1, ymm2, ymm3/m256

EVEX.128.66.0F.W0 DF /r

V/V

AVX512VL

Bitwise AND NOT of packed doubleword

VPANDND xmm1 {k1}{z}, xmm2,

AVX512F

integers in xmm2 and xmm3/m128/m32bcst

xmm3/m128/m32bcst

and store result in xmm1 using writemask k1.

EVEX.256.66.0F.W0 DF /r

V/V

AVX512VL

Bitwise AND NOT of packed doubleword

VPANDND ymm1 {k1}{z}, ymm2,

AVX512F

integers in ymm2 and ymm3/m256/m32bcst

ymm3/m256/m32bcst

and store result in ymm1 using writemask k1.

EVEX.512.66.0F.W0 DF /r

V/V

AVX512F

Bitwise AND NOT of packed doubleword

VPANDND zmm1 {k1}{z}, zmm2,

integers in zmm2 and zmm3/m512/m32bcst

zmm3/m512/m32bcst

and store result in zmm1 using writemask k1.

EVEX.128.66.0F.W1 DF /r

V/V

AVX512VL

Bitwise AND NOT of packed quadword

VPANDNQ xmm1 {k1}{z}, xmm2,

AVX512F

integers in xmm2 and xmm3/m128/m64bcst

xmm3/m128/m64bcst

and store result in xmm1 using writemask k1.

EVEX.256.66.0F.W1 DF /r

V/V

AVX512VL

Bitwise AND NOT of packed quadword

VPANDNQ ymm1 {k1}{z}, ymm2,

AVX512F

integers in ymm2 and ymm3/m256/m64bcst

ymm3/m256/m64bcst

and store result in ymm1 using writemask k1.

EVEX.512.66.0F.W1 DF /r

V/V

AVX512F

Bitwise AND NOT of packed quadword

VPANDNQ zmm1 {k1}{z}, zmm2,

integers in zmm2 and zmm3/m512/m64bcst

zmm3/m512/m64bcst

and store result in zmm1 using writemask k1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a bitwise logical NOT operation on the first source operand, then performs bitwise AND with second

source operand and stores the result in the destination operand. Each bit of the result is set to 1 if the corre-

sponding bit in the first operand is 0 and the corresponding bit in the second operand is 1, otherwise it is set to 0.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

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PANDN—Logical AND NOT

INSTRUCTION SET REFERENCE, M-U

Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The

destination operand can be an MMX technology register.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (MAXVL-1:128) of the corresponding ZMM register destination are unmodified.

EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be

a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a

32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with

writemask k1 at 32/64-bit granularity.

VEX.256 encoded versions: The first source operand is a YMM register. The second source operand is a YMM

the corresponding ZMM register destination are zeroed.

VEX.128 encoded versions: The first source operand is an XMM register. The second source operand is an XMM

the corresponding ZMM register destination are zeroed.

Operation

PANDN (64-bit operand)

DEST := NOT(DEST) AND SRC

PANDN (128-bit Legacy SSE version)

DEST := NOT(DEST) AND SRC

DEST[MAXVL-1:128] (Unmodified)

VPANDN (VEX.128 encoded version)

DEST := NOT(SRC1) AND SRC2

DEST[MAXVL-1:128] := 0

VPANDN (VEX.256 encoded instruction)

DEST[255:0] := ((NOT SRC1[255:0]) AND SRC2[255:0])

DEST[MAXVL-1:256] := 0

VPANDND (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN DEST[i+31:i] := ((NOT SRC1[i+31:i]) AND SRC2[31:0])

ELSE DEST[i+31:i] := ((NOT SRC1[i+31:i]) AND SRC2[i+31:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

PANDN—Logical AND NOT

Vol. 2B

4-233

INSTRUCTION SET REFERENCE, M-U

VPANDNQ (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN DEST[i+63:i] := ((NOT SRC1[i+63:i]) AND SRC2[63:0])

ELSE DEST[i+63:i] := ((NOT SRC1[i+63:i]) AND SRC2[i+63:i])

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalents

VPANDND __m512i _mm512_andnot_epi32( __m512i a, __m512i b);

VPANDND __m512i _mm512_mask_andnot_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);

VPANDND __m512i _mm512_maskz_andnot_epi32( __mmask16 k, __m512i a, __m512i b);

VPANDND __m256i _mm256_mask_andnot_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);

VPANDND __m256i _mm256_maskz_andnot_epi32( __mmask8 k, __m256i a, __m256i b);

VPANDND __m128i _mm_mask_andnot_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);

VPANDND __m128i _mm_maskz_andnot_epi32( __mmask8 k, __m128i a, __m128i b);

VPANDNQ __m512i _mm512_andnot_epi64( __m512i a, __m512i b);

VPANDNQ __m512i _mm512_mask_andnot_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);

VPANDNQ __m512i _mm512_maskz_andnot_epi64( __mmask8 k, __m512i a, __m512i b);

VPANDNQ __m256i _mm256_mask_andnot_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);

VPANDNQ __m256i _mm256_maskz_andnot_epi64( __mmask8 k, __m256i a, __m256i b);

VPANDNQ __m128i _mm_mask_andnot_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);

VPANDNQ __m128i _mm_maskz_andnot_epi64( __mmask8 k, __m128i a, __m128i b);

PANDN: __m64 _mm_andnot_si64 (__m64 m1, __m64 m2)

(V)PANDN:__m128i _mm_andnot_si128 ( __m128i a, __m128i b)

VPANDN:

__m256i _mm256_andnot_si256 ( __m256i a, __m256i b)

Flags Affected

None.

Numeric Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions”.

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PANDN—Logical AND NOT

INSTRUCTION SET REFERENCE, M-U

PAUSE—Spin Loop Hint

Opcode

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

F3 90

PAUSE

Valid

Gives hint to processor that improves

performance of spin-wait loops.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

N/A

Description

Improves the performance of spin-wait loops. When executing a “spin-wait loop,” processors will suffer a severe

performance penalty when exiting the loop because it detects a possible memory order violation. The PAUSE

instruction provides a hint to the processor that the code sequence is a spin-wait loop. The processor uses this hint

to avoid the memory order violation in most situations, which greatly improves processor performance. For this

reason, it is recommended that a PAUSE instruction be placed in all spin-wait loops.

An additional function of the PAUSE instruction is to reduce the power consumed by a processor while executing a

spin loop. A processor can execute a spin-wait loop extremely quickly, causing the processor to consume a lot of

power while it waits for the resource it is spinning on to become available. Inserting a pause instruction in a spin-

wait loop greatly reduces the processor’s power consumption.

This instruction was introduced in the Pentium 4 processors, but is backward compatible with all IA-32 processors.

In earlier IA-32 processors, the PAUSE instruction operates like a NOP instruction. The Pentium 4 and Intel Xeon

processors implement the PAUSE instruction as a delay. The delay is finite and can be zero for some processors.

This instruction does not change the architectural state of the processor (that is, it performs essentially a delaying

no-op operation).

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

Execute_Next_Instruction(DELAY);

Numeric Exceptions

None.

Exceptions (All Operating Modes)

#UD

If the LOCK prefix is used.

PAUSE—Spin Loop Hint

Vol. 2B

4-235

INSTRUCTION SET REFERENCE, M-U

PAVGB/PAVGW—Average Packed Integers

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F E0 /r¹

V/V

SSE

Average packed unsigned byte integers from

mm2/m64 and mm1 with rounding.

PAVGB mm1, mm2/m64

66 0F E0, /r

V/V

SSE2

Average packed unsigned byte integers from

xmm2/m128 and xmm1 with rounding.

PAVGB xmm1, xmm2/m128

NP 0F E3 /r¹

V/V

SSE

Average packed unsigned word integers from

mm2/m64 and mm1 with rounding.

PAVGW mm1, mm2/m64

66 0F E3 /r

V/V

SSE2

Average packed unsigned word integers from

xmm2/m128 and xmm1 with rounding.

PAVGW xmm1, xmm2/m128

VEX.128.66.0F.WIG E0 /r

V/V

AVX

Average packed unsigned byte integers from

xmm3/m128 and xmm2 with rounding.

VPAVGB xmm1, xmm2, xmm3/m128

VEX.128.66.0F.WIG E3 /r

V/V

AVX

Average packed unsigned word integers from

xmm3/m128 and xmm2 with rounding.

VPAVGW xmm1, xmm2, xmm3/m128

VEX.256.66.0F.WIG E0 /r

V/V

AVX2

Average packed unsigned byte integers from

ymm2, and ymm3/m256 with rounding and

VPAVGB ymm1, ymm2, ymm3/m256

store to ymm1.

VEX.256.66.0F.WIG E3 /r

V/V

AVX2

Average packed unsigned word integers from

VPAVGW ymm1, ymm2, ymm3/m256

ymm2, ymm3/m256 with rounding to ymm1.

EVEX.128.66.0F.WIG E0 /r

V/V

AVX512VL

Average packed unsigned byte integers from

VPAVGB xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

xmm2, and xmm3/m128 with rounding and

store to xmm1 under writemask k1.

EVEX.256.66.0F.WIG E0 /r

V/V

AVX512VL

Average packed unsigned byte integers from

VPAVGB ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

ymm2, and ymm3/m256 with rounding and

store to ymm1 under writemask k1.

EVEX.512.66.0F.WIG E0 /r

V/V

AVX512BW

Average packed unsigned byte integers from

VPAVGB zmm1 {k1}{z}, zmm2, zmm3/m512

zmm2, and zmm3/m512 with rounding and

store to zmm1 under writemask k1.

EVEX.128.66.0F.WIG E3 /r

V/V

AVX512VL

Average packed unsigned word integers from

VPAVGW xmm1 {k1}{z}, xmm2, xmm3/m128

AVX512BW

xmm2, xmm3/m128 with rounding to xmm1

under writemask k1.

EVEX.256.66.0F.WIG E3 /r

V/V

AVX512VL

Average packed unsigned word integers from

VPAVGW ymm1 {k1}{z}, ymm2, ymm3/m256

AVX512BW

ymm2, ymm3/m256 with rounding to ymm1

under writemask k1.

EVEX.512.66.0F.WIG E3 /r

V/V

AVX512BW

Average packed unsigned word integers from

VPAVGW zmm1 {k1}{z}, zmm2, zmm3/m512

zmm2, zmm3/m512 with rounding to zmm1

under writemask k1.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Reg-

isters” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

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PAVGB/PAVGW—Average Packed Integers

INSTRUCTION SET REFERENCE, M-U

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a SIMD average of the packed unsigned integers from the source operand (second operand) and the

destination operand (first operand), and stores the results in the destination operand. For each corresponding pair

of data elements in the first and second operands, the elements are added together, a 1 is added to the temporary

sum, and that result is shifted right one bit position.

The (V)PAVGB instruction operates on packed unsigned bytes and the (V)PAVGW instruction operates on packed

unsigned words.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The

destination operand can be an MMX technology register.

128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM

upper bits (MAXVL-1:128) of the corresponding register destination are unmodified.

EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM

VEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand

is a YMM register or a 256-bit memory location. The destination operand is a YMM register.

VEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand

is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-

1:128) of the corresponding register destination are zeroed.

Operation

PAVGB (with 64-bit operands)

DEST[7:0] := (SRC[7:0] + DEST[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)

(* Repeat operation performed for bytes 2 through 6 *)

DEST[63:56] := (SRC[63:56] + DEST[63:56] + 1) >> 1;

PAVGW (with 64-bit operands)

DEST[15:0] := (SRC[15:0] + DEST[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)

(* Repeat operation performed for words 2 and 3 *)

DEST[63:48] := (SRC[63:48] + DEST[63:48] + 1) >> 1;

PAVGB (with 128-bit operands)

DEST[7:0] := (SRC[7:0] + DEST[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)

(* Repeat operation performed for bytes 2 through 14 *)

DEST[127:120] := (SRC[127:120] + DEST[127:120] + 1) >> 1;

PAVGW (with 128-bit operands)

DEST[15:0] := (SRC[15:0] + DEST[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)

(* Repeat operation performed for words 2 through 6 *)

DEST[127:112] := (SRC[127:112] + DEST[127:112] + 1) >> 1;

PAVGB/PAVGW—Average Packed Integers

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INSTRUCTION SET REFERENCE, M-U

VPAVGB (VEX.128 encoded version)

DEST[7:0] := (SRC1[7:0] + SRC2[7:0] + 1) >> 1;

(* Repeat operation performed for bytes 2 through 15 *)

DEST[127:120] := (SRC1[127:120] + SRC2[127:120] + 1) >> 1

DEST[MAXVL-1:128] := 0

VPAVGW (VEX.128 encoded version)

DEST[15:0] := (SRC1[15:0] + SRC2[15:0] + 1) >> 1;

(* Repeat operation performed for 16-bit words 2 through 7 *)

DEST[127:112] := (SRC1[127:112] + SRC2[127:112] + 1) >> 1

DEST[MAXVL-1:128] := 0

VPAVGB (VEX.256 encoded instruction)

DEST[7:0] := (SRC1[7:0] + SRC2[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)

(* Repeat operation performed for bytes 2 through 31)

DEST[255:248] := (SRC1[255:248] + SRC2[255:248] + 1) >> 1;

VPAVGW (VEX.256 encoded instruction)

DEST[15:0] := (SRC1[15:0] + SRC2[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)

(* Repeat operation performed for words 2 through 15)

DEST[255:14]) := (SRC1[255:240] + SRC2[255:240] + 1) >> 1;

VPAVGB (EVEX encoded versions)

(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j := 0 TO KL-1

i := j * 8

IF k1[j] OR *no writemask*

THEN DEST[i+7:i] := (SRC1[i+7:i] + SRC2[i+7:i] + 1) >> 1; (* Temp sum before shifting is 9 bits *)

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+7:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+7:i] = 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

VPAVGW (EVEX encoded versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO KL-1

i := j * 16

IF k1[j] OR *no writemask*

THEN DEST[i+15:i] := (SRC1[i+15:i] + SRC2[i+15:i] + 1) >> 1

; (* Temp sum before shifting is 17 bits *)

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+15:i] remains unchanged*

ELSE *zeroing-masking*

; zeroing-masking

DEST[i+15:i] = 0

FI;

ENDFOR;

DEST[MAXVL-1:VL] := 0

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PAVGB/PAVGW—Average Packed Integers

INSTRUCTION SET REFERENCE, M-U

Intel C/C++ Compiler Intrinsic Equivalents

VPAVGB __m512i _mm512_avg_epu8( __m512i a, __m512i b);

VPAVGW __m512i _mm512_avg_epu16( __m512i a, __m512i b);

VPAVGB __m512i _mm512_mask_avg_epu8(__m512i s, __mmask64 m, __m512i a, __m512i b);

VPAVGW __m512i _mm512_mask_avg_epu16(__m512i s, __mmask32 m, __m512i a, __m512i b);

VPAVGB __m512i _mm512_maskz_avg_epu8( __mmask64 m, __m512i a, __m512i b);

VPAVGW __m512i _mm512_maskz_avg_epu16( __mmask32 m, __m512i a, __m512i b);

VPAVGB __m256i _mm256_mask_avg_epu8(__m256i s, __mmask32 m, __m256i a, __m256i b);

VPAVGW __m256i _mm256_mask_avg_epu16(__m256i s, __mmask16 m, __m256i a, __m256i b);

VPAVGB __m256i _mm256_maskz_avg_epu8( __mmask32 m, __m256i a, __m256i b);

VPAVGW __m256i _mm256_maskz_avg_epu16( __mmask16 m, __m256i a, __m256i b);

VPAVGB __m128i _mm_mask_avg_epu8(__m128i s, __mmask16 m, __m128i a, __m128i b);

VPAVGW __m128i _mm_mask_avg_epu16(__m128i s, __mmask8 m, __m128i a, __m128i b);

VPAVGB __m128i _mm_maskz_avg_epu8( __mmask16 m, __m128i a, __m128i b);

VPAVGW __m128i _mm_maskz_avg_epu16( __mmask8 m, __m128i a, __m128i b);

PAVGB: __m64 _mm_avg_pu8 (__m64 a, __m64 b)

PAVGW: __m64 _mm_avg_pu16 (__m64 a, __m64 b)

(V)PAVGB: __m128i _mm_avg_epu8 ( __m128i a, __m128i b)

(V)PAVGW: __m128i _mm_avg_epu16 ( __m128i a, __m128i b)

VPAVGB:

__m256i _mm256_avg_epu8 ( __m256i a, __m256i b)

VPAVGW:

__m256i _mm256_avg_epu16 ( __m256i a, __m256i b)

Flags Affected

None.

Numeric Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded instruction, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions”.

PAVGB/PAVGW—Average Packed Integers

Vol. 2B

4-239

INSTRUCTION SET REFERENCE, M-U

PBLENDVB—Variable Blend Packed Bytes

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

66 0F 38 10 /r

V/V

SSE4_1

Select byte values from xmm1 and

PBLENDVB xmm1, xmm2/m128, <XMM0>

xmm2/m128 from mask specified in the high

bit of each byte in XMM0 and store the

values into xmm1.

VEX.128.66.0F3A.W0 4C /r /is4

RVMR

V/V

AVX

Select byte values from xmm2 and

VPBLENDVB xmm1, xmm2, xmm3/m128, xmm4

xmm3/m128 using mask bits in the specified

mask register, xmm4, and store the values

into xmm1.

VEX.256.66.0F3A.W0 4C /r /is4

RVMR

V/V

AVX2

Select byte values from ymm2 and

VPBLENDVB ymm1, ymm2, ymm3/m256, ymm4

ymm3/m256 from mask specified in the high

bit of each byte in ymm4 and store the

values into ymm1.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:reg (r, w)

ModRM:r/m (r)

<XMM0>

N/A

RVMR

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8[7:4]

Description

Conditionally copies byte elements from the source operand (second operand) to the destination operand (first

operand) depending on mask bits defined in the implicit third register argument, XMM0. The mask bits are the most

significant bit in each byte element of the XMM0 register.

If a mask bit is “1", then the corresponding byte element in the source operand is copied to the destination, else

the byte element in the destination operand is left unchanged.

The register assignment of the implicit third operand is defined to be the architectural register XMM0.

128-bit Legacy SSE version: The first source operand and the destination operand is the same. Bits (MAXVL-1:128)

of the corresponding YMM destination register remain unchanged. The mask register operand is implicitly defined

to be the architectural register XMM0. An attempt to execute PBLENDVB with a VEX prefix will cause #UD.

VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second

source operand is an XMM register or 128-bit memory location. The mask operand is the third source register, and

encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is

ignored. The upper bits (MAXVL-1:128) of the corresponding YMM register (destination register) are zeroed. VEX.L

must be 0, otherwise the instruction will #UD. VEX.W must be 0, otherwise, the instruction will #UD.

VEX.256 encoded version: The first source operand and the destination operand are YMM registers. The second

source operand is an YMM register or 256-bit memory location. The third source register is an YMM register and

encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is

ignored.

VPBLENDVB permits the mask to be any XMM or YMM register. In contrast, PBLENDVB treats XMM0 implicitly as the

mask and do not support non-destructive destination operation. An attempt to execute PBLENDVB encoded with a

VEX prefix will cause a #UD exception.

Operation

PBLENDVB (128-bit Legacy SSE version)

MASK := XMM0

IF (MASK[7] = 1) THEN DEST[7:0] := SRC[7:0];

ELSE DEST[7:0] := DEST[7:0];

IF (MASK[15] = 1) THEN DEST[15:8] := SRC[15:8];

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PBLENDVB—Variable Blend Packed Bytes

INSTRUCTION SET REFERENCE, M-U

ELSE DEST[15:8] := DEST[15:8];

IF (MASK[23] = 1) THEN DEST[23:16] := SRC[23:16]

ELSE DEST[23:16] := DEST[23:16];

IF (MASK[31] = 1) THEN DEST[31:24] := SRC[31:24]

ELSE DEST[31:24] := DEST[31:24];

IF (MASK[39] = 1) THEN DEST[39:32] := SRC[39:32]

ELSE DEST[39:32] := DEST[39:32];

IF (MASK[47] = 1) THEN DEST[47:40] := SRC[47:40]

ELSE DEST[47:40] := DEST[47:40];

IF (MASK[55] = 1) THEN DEST[55:48] := SRC[55:48]

ELSE DEST[55:48] := DEST[55:48];

IF (MASK[63] = 1) THEN DEST[63:56] := SRC[63:56]

ELSE DEST[63:56] := DEST[63:56];

IF (MASK[71] = 1) THEN DEST[71:64] := SRC[71:64]

ELSE DEST[71:64] := DEST[71:64];

IF (MASK[79] = 1) THEN DEST[79:72] := SRC[79:72]

ELSE DEST[79:72] := DEST[79:72];

IF (MASK[87] = 1) THEN DEST[87:80] := SRC[87:80]

ELSE DEST[87:80] := DEST[87:80];

IF (MASK[95] = 1) THEN DEST[95:88] := SRC[95:88]

ELSE DEST[95:88] := DEST[95:88];

IF (MASK[103] = 1) THEN DEST[103:96] := SRC[103:96]

ELSE DEST[103:96] := DEST[103:96];

IF (MASK[111] = 1) THEN DEST[111:104] := SRC[111:104]

ELSE DEST[111:104] := DEST[111:104];

IF (MASK[119] = 1) THEN DEST[119:112] := SRC[119:112]

ELSE DEST[119:112] := DEST[119:112];

IF (MASK[127] = 1) THEN DEST[127:120] := SRC[127:120]

ELSE DEST[127:120] := DEST[127:120])

DEST[MAXVL-1:128] (Unmodified)

VPBLENDVB (VEX.128 encoded version)

MASK := SRC3

IF (MASK[7] = 1) THEN DEST[7:0] := SRC2[7:0];

ELSE DEST[7:0] := SRC1[7:0];

IF (MASK[15] = 1) THEN DEST[15:8] := SRC2[15:8];

ELSE DEST[15:8] := SRC1[15:8];

IF (MASK[23] = 1) THEN DEST[23:16] := SRC2[23:16]

ELSE DEST[23:16] := SRC1[23:16];

IF (MASK[31] = 1) THEN DEST[31:24] := SRC2[31:24]

ELSE DEST[31:24] := SRC1[31:24];

IF (MASK[39] = 1) THEN DEST[39:32] := SRC2[39:32]

ELSE DEST[39:32] := SRC1[39:32];

IF (MASK[47] = 1) THEN DEST[47:40] := SRC2[47:40]

ELSE DEST[47:40] := SRC1[47:40];

IF (MASK[55] = 1) THEN DEST[55:48] := SRC2[55:48]

ELSE DEST[55:48] := SRC1[55:48];

IF (MASK[63] = 1) THEN DEST[63:56] := SRC2[63:56]

ELSE DEST[63:56] := SRC1[63:56];

IF (MASK[71] = 1) THEN DEST[71:64] := SRC2[71:64]

ELSE DEST[71:64] := SRC1[71:64];

IF (MASK[79] = 1) THEN DEST[79:72] := SRC2[79:72]

ELSE DEST[79:72] := SRC1[79:72];

IF (MASK[87] = 1) THEN DEST[87:80] := SRC2[87:80]

PBLENDVB—Variable Blend Packed Bytes

Vol. 2B

4-241

INSTRUCTION SET REFERENCE, M-U

ELSE DEST[87:80] := SRC1[87:80];

IF (MASK[95] = 1) THEN DEST[95:88] := SRC2[95:88]

ELSE DEST[95:88] := SRC1[95:88];

IF (MASK[103] = 1) THEN DEST[103:96] := SRC2[103:96]

ELSE DEST[103:96] := SRC1[103:96];

IF (MASK[111] = 1) THEN DEST[111:104] := SRC2[111:104]

ELSE DEST[111:104] := SRC1[111:104];

IF (MASK[119] = 1) THEN DEST[119:112] := SRC2[119:112]

ELSE DEST[119:112] := SRC1[119:112];

IF (MASK[127] = 1) THEN DEST[127:120] := SRC2[127:120]

ELSE DEST[127:120] := SRC1[127:120])

DEST[MAXVL-1:128] := 0

VPBLENDVB (VEX.256 encoded version)

MASK := SRC3

IF (MASK[7] == 1) THEN DEST[7:0] := SRC2[7:0];

ELSE DEST[7:0] := SRC1[7:0];

IF (MASK[15] == 1) THEN DEST[15:8] := SRC2[15:8];

ELSE DEST[15:8] := SRC1[15:8];

IF (MASK[23] == 1) THEN DEST[23:16] := SRC2[23:16]

ELSE DEST[23:16] := SRC1[23:16];

IF (MASK[31] == 1) THEN DEST[31:24] := SRC2[31:24]

ELSE DEST[31:24] := SRC1[31:24];

IF (MASK[39] == 1) THEN DEST[39:32] := SRC2[39:32]

ELSE DEST[39:32] := SRC1[39:32];

IF (MASK[47] == 1) THEN DEST[47:40] := SRC2[47:40]

ELSE DEST[47:40] := SRC1[47:40];

IF (MASK[55] == 1) THEN DEST[55:48] := SRC2[55:48]

ELSE DEST[55:48] := SRC1[55:48];

IF (MASK[63] == 1) THEN DEST[63:56] := SRC2[63:56]

ELSE DEST[63:56] := SRC1[63:56];

IF (MASK[71] == 1) THEN DEST[71:64] := SRC2[71:64]

ELSE DEST[71:64] := SRC1[71:64];

IF (MASK[79] == 1) THEN DEST[79:72] := SRC2[79:72]

ELSE DEST[79:72] := SRC1[79:72];

IF (MASK[87] == 1) THEN DEST[87:80] := SRC2[87:80]

ELSE DEST[87:80] := SRC1[87:80];

IF (MASK[95] == 1) THEN DEST[95:88] := SRC2[95:88]

ELSE DEST[95:88] := SRC1[95:88];

IF (MASK[103] == 1) THEN DEST[103:96] := SRC2[103:96]

ELSE DEST[103:96] := SRC1[103:96];

IF (MASK[111] == 1) THEN DEST[111:104] := SRC2[111:104]

ELSE DEST[111:104] := SRC1[111:104];

IF (MASK[119] == 1) THEN DEST[119:112] := SRC2[119:112]

ELSE DEST[119:112] := SRC1[119:112];

IF (MASK[127] == 1) THEN DEST[127:120] := SRC2[127:120]

ELSE DEST[127:120] := SRC1[127:120])

IF (MASK[135] == 1) THEN DEST[135:128] := SRC2[135:128];

ELSE DEST[135:128] := SRC1[135:128];

IF (MASK[143] == 1) THEN DEST[143:136] := SRC2[143:136];

ELSE DEST[[143:136] := SRC1[143:136];

IF (MASK[151] == 1) THEN DEST[151:144] := SRC2[151:144]

ELSE DEST[151:144] := SRC1[151:144];

IF (MASK[159] == 1) THEN DEST[159:152] := SRC2[159:152]

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Vol. 2B

PBLENDVB—Variable Blend Packed Bytes

INSTRUCTION SET REFERENCE, M-U

ELSE DEST[159:152] := SRC1[159:152];

IF (MASK[167] == 1) THEN DEST[167:160] := SRC2[167:160]

ELSE DEST[167:160] := SRC1[167:160];

IF (MASK[175] == 1) THEN DEST[175:168] := SRC2[175:168]

ELSE DEST[175:168] := SRC1[175:168];

IF (MASK[183] == 1) THEN DEST[183:176] := SRC2[183:176]

ELSE DEST[183:176] := SRC1[183:176];

IF (MASK[191] == 1) THEN DEST[191:184] := SRC2[191:184]

ELSE DEST[191:184] := SRC1[191:184];

IF (MASK[199] == 1) THEN DEST[199:192] := SRC2[199:192]

ELSE DEST[199:192] := SRC1[199:192];

IF (MASK[207] == 1) THEN DEST[207:200] := SRC2[207:200]

ELSE DEST[207:200] := SRC1[207:200]

IF (MASK[215] == 1) THEN DEST[215:208] := SRC2[215:208]

ELSE DEST[215:208] := SRC1[215:208];

IF (MASK[223] == 1) THEN DEST[223:216] := SRC2[223:216]

ELSE DEST[223:216] := SRC1[223:216];

IF (MASK[231] == 1) THEN DEST[231:224] := SRC2[231:224]

ELSE DEST[231:224] := SRC1[231:224];

IF (MASK[239] == 1) THEN DEST[239:232] := SRC2[239:232]

ELSE DEST[239:232] := SRC1[239:232];

IF (MASK[247] == 1) THEN DEST[247:240] := SRC2[247:240]

ELSE DEST[247:240] := SRC1[247:240];

IF (MASK[255] == 1) THEN DEST[255:248] := SRC2[255:248]

ELSE DEST[255:248] := SRC1[255:248]

Intel C/C++ Compiler Intrinsic Equivalent

(V)PBLENDVB:

__m128i _mm_blendv_epi8 (__m128i v1, __m128i v2, __m128i mask);

VPBLENDVB:

__m256i _mm256_blendv_epi8 (__m256i v1, __m256i v2, __m256i mask);

Flags Affected

None.

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions”; additionally:

#UD

If VEX.W = 1.

PBLENDVB—Variable Blend Packed Bytes

Vol. 2B

4-243

INSTRUCTION SET REFERENCE, M-U

PBLENDW—Blend Packed Words

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

66 0F 3A 0E /r ib

RMI

V/V

SSE4_1

Select words from xmm1 and xmm2/m128

PBLENDW xmm1, xmm2/m128, imm8

from mask specified in imm8 and store the

values into xmm1.

VEX.128.66.0F3A.WIG 0E /r ib

RVMI

V/V

AVX

Select words from xmm2 and xmm3/m128

VPBLENDW xmm1, xmm2, xmm3/m128, imm8

from mask specified in imm8 and store the

values into xmm1.

VEX.256.66.0F3A.WIG 0E /r ib

RVMI

V/V

AVX2

Select words from ymm2 and ymm3/m256

VPBLENDW ymm1, ymm2, ymm3/m256, imm8

from mask specified in imm8 and store the

values into ymm1.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RMI

ModRM:reg (r, w)

ModRM:r/m (r)

imm8

N/A

RVMI

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

Words from the source operand (second operand) are conditionally written to the destination operand (first

operand) depending on bits in the immediate operand (third operand). The immediate bits (bits 7:0) form a mask

that determines whether the corresponding word in the destination is copied from the source. If a bit in the mask,

corresponding to a word, is “1", then the word is copied, else the word element in the destination operand is

unchanged.

128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The

first source and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM destination

VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The

first source and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM register

are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

Operation

PBLENDW (128-bit Legacy SSE version)

IF (imm8[0] = 1) THEN DEST[15:0] := SRC[15:0]

ELSE DEST[15:0] := DEST[15:0]

IF (imm8[1] = 1) THEN DEST[31:16] := SRC[31:16]

ELSE DEST[31:16] := DEST[31:16]

IF (imm8[2] = 1) THEN DEST[47:32] := SRC[47:32]

ELSE DEST[47:32] := DEST[47:32]

IF (imm8[3] = 1) THEN DEST[63:48] := SRC[63:48]

ELSE DEST[63:48] := DEST[63:48]

IF (imm8[4] = 1) THEN DEST[79:64] := SRC[79:64]

ELSE DEST[79:64] := DEST[79:64]

IF (imm8[5] = 1) THEN DEST[95:80] := SRC[95:80]

ELSE DEST[95:80] := DEST[95:80]

IF (imm8[6] = 1) THEN DEST[111:96] := SRC[111:96]

ELSE DEST[111:96] := DEST[111:96]

IF (imm8[7] = 1) THEN DEST[127:112] := SRC[127:112]

4-244

Vol. 2B

PBLENDW—Blend Packed Words

INSTRUCTION SET REFERENCE, M-U

ELSE DEST[127:112] := DEST[127:112]

VPBLENDW (VEX.128 encoded version)

IF (imm8[0] = 1) THEN DEST[15:0] := SRC2[15:0]

ELSE DEST[15:0] := SRC1[15:0]

IF (imm8[1] = 1) THEN DEST[31:16] := SRC2[31:16]

ELSE DEST[31:16] := SRC1[31:16]

IF (imm8[2] = 1) THEN DEST[47:32] := SRC2[47:32]

ELSE DEST[47:32] := SRC1[47:32]

IF (imm8[3] = 1) THEN DEST[63:48] := SRC2[63:48]

ELSE DEST[63:48] := SRC1[63:48]

IF (imm8[4] = 1) THEN DEST[79:64] := SRC2[79:64]

ELSE DEST[79:64] := SRC1[79:64]

IF (imm8[5] = 1) THEN DEST[95:80] := SRC2[95:80]

ELSE DEST[95:80] := SRC1[95:80]

IF (imm8[6] = 1) THEN DEST[111:96] := SRC2[111:96]

ELSE DEST[111:96] := SRC1[111:96]

IF (imm8[7] = 1) THEN DEST[127:112] := SRC2[127:112]

ELSE DEST[127:112] := SRC1[127:112]

DEST[MAXVL-1:128] := 0

VPBLENDW (VEX.256 encoded version)

IF (imm8[0] == 1) THEN DEST[15:0] := SRC2[15:0]

ELSE DEST[15:0] := SRC1[15:0]

IF (imm8[1] == 1) THEN DEST[31:16] := SRC2[31:16]

ELSE DEST[31:16] := SRC1[31:16]

IF (imm8[2] == 1) THEN DEST[47:32] := SRC2[47:32]

ELSE DEST[47:32] := SRC1[47:32]

IF (imm8[3] == 1) THEN DEST[63:48] := SRC2[63:48]

ELSE DEST[63:48] := SRC1[63:48]

IF (imm8[4] == 1) THEN DEST[79:64] := SRC2[79:64]

ELSE DEST[79:64] := SRC1[79:64]

IF (imm8[5] == 1) THEN DEST[95:80] := SRC2[95:80]

ELSE DEST[95:80] := SRC1[95:80]

IF (imm8[6] == 1) THEN DEST[111:96] := SRC2[111:96]

ELSE DEST[111:96] := SRC1[111:96]

IF (imm8[7] == 1) THEN DEST[127:112] := SRC2[127:112]

ELSE DEST[127:112] := SRC1[127:112]

IF (imm8[0] == 1) THEN DEST[143:128] := SRC2[143:128]

ELSE DEST[143:128] := SRC1[143:128]

IF (imm8[1] == 1) THEN DEST[159:144] := SRC2[159:144]

ELSE DEST[159:144] := SRC1[159:144]

IF (imm8[2] == 1) THEN DEST[175:160] := SRC2[175:160]

ELSE DEST[175:160] := SRC1[175:160]

IF (imm8[3] == 1) THEN DEST[191:176] := SRC2[191:176]

ELSE DEST[191:176] := SRC1[191:176]

IF (imm8[4] == 1) THEN DEST[207:192] := SRC2[207:192]

ELSE DEST[207:192] := SRC1[207:192]

IF (imm8[5] == 1) THEN DEST[223:208] := SRC2[223:208]

ELSE DEST[223:208] := SRC1[223:208]

IF (imm8[6] == 1) THEN DEST[239:224] := SRC2[239:224]

ELSE DEST[239:224] := SRC1[239:224]

IF (imm8[7] == 1) THEN DEST[255:240] := SRC2[255:240]

ELSE DEST[255:240] := SRC1[255:240]

PBLENDW—Blend Packed Words

Vol. 2B

4-245

INSTRUCTION SET REFERENCE, M-U

PCLMULQDQ—Carry-Less Multiplication Quadword

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature Flag

Support

66 0F 3A 44 /r ib

V/V

PCLMULQDQ

Carry-less multiplication of one quadword of

PCLMULQDQ xmm1, xmm2/m128, imm8

xmm1 by one quadword of xmm2/m128,

stores the 128-bit result in xmm1. The imme-

diate is used to determine which quadwords

of xmm1 and xmm2/m128 should be used.

VEX.128.66.0F3A.WIG 44 /r ib

V/V

PCLMULQDQ

Carry-less multiplication of one quadword of

VPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8

AVX

xmm2 by one quadword of xmm3/m128,

stores the 128-bit result in xmm1. The imme-

diate is used to determine which quadwords

of xmm2 and xmm3/m128 should be used.

VEX.256.66.0F3A.WIG 44 /r /ib

V/V

VPCLMULQDQ

Carry-less multiplication of one quadword of

VPCLMULQDQ ymm1, ymm2, ymm3/m256, imm8

ymm2 by one quadword of ymm3/m256,

stores the 128-bit result in ymm1. The imme-

diate is used to determine which quadwords

of ymm2 and ymm3/m256 should be used.

EVEX.128.66.0F3A.WIG 44 /r /ib

V/V

VPCLMULQDQ

Carry-less multiplication of one quadword of

VPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8

AVX512VL

xmm2 by one quadword of xmm3/m128,

stores the 128-bit result in xmm1. The imme-

diate is used to determine which quadwords

of xmm2 and xmm3/m128 should be used.

EVEX.256.66.0F3A.WIG 44 /r /ib

V/V

VPCLMULQDQ

Carry-less multiplication of one quadword of

VPCLMULQDQ ymm1, ymm2, ymm3/m256, imm8

AVX512VL

ymm2 by one quadword of ymm3/m256,

stores the 128-bit result in ymm1. The imme-

diate is used to determine which quadwords

of ymm2 and ymm3/m256 should be used.

EVEX.512.66.0F3A.WIG 44 /r /ib

V/V

VPCLMULQDQ

Carry-less multiplication of one quadword of

VPCLMULQDQ zmm1, zmm2, zmm3/m512, imm8

AVX512F

zmm2 by one quadword of zmm3/m512,

stores the 128-bit result in zmm1. The imme-

diate is used to determine which quadwords

of zmm2 and zmm3/m512 should be used.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

imm8

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

imm8 (r)

Description

Performs a carry-less multiplication of two quadwords, selected from the first source and second source operand

according to the value of the immediate byte. Bits 4 and 0 are used to select which 64-bit half of each operand to

use according to Table 4-13, other bits of the immediate byte are ignored.

The EVEX encoded form of this instruction does not support memory fault suppression.

PCLMULQDQ—Carry-Less Multiplication Quadword

Vol. 2B

4-247

INSTRUCTION SET REFERENCE, M-U

Table 4-13. PCLMULQDQ Quadword Selection of Immediate Byte

Imm[4]

Imm[0]

PCLMULQDQ Operation

CL_MUL( SRC2¹[63:0], SRC1[63:0] )

CL_MUL( SRC2[63:0], SRC1[127:64] )

CL_MUL( SRC2[127:64], SRC1[63:0] )

CL_MUL( SRC2[127:64], SRC1[127:64] )

NOTES:

1. SRC2 denotes the second source operand, which can be a register or memory; SRC1 denotes the first source and destination oper-

and.

The first source operand and the destination operand are the same and must be a ZMM/YMM/XMM register. The

second source operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location. Bits (VL_MAX-

1:128) of the corresponding YMM destination register remain unchanged.

Compilers and assemblers may implement the following pseudo-op syntax to simplify programming and emit the

required encoding for imm8.

Table 4-14. Pseudo-Op and PCLMULQDQ Implementation

Pseudo-Op

Imm8 Encoding

PCLMULLQLQDQ xmm1, xmm2

0000_0000B

PCLMULHQLQDQ xmm1, xmm2

0000_0001B

PCLMULLQHQDQ xmm1, xmm2

0001_0000B

PCLMULHQHQDQ xmm1, xmm2

0001_0001B

Operation

define PCLMUL128(X,Y):

// helper function

FOR i := 0 to 63:

TMP [ i ] := X[ 0 ] and Y[ i ]

FOR j := 1 to i:

TMP [ i ] := TMP [ i ] xor (X[ j ] and Y[ i - j ])

DEST[ i ] := TMP[ i ]

FOR i := 64 to 126:

TMP [ i ] := 0

FOR j := i - 63 to 63:

TMP [ i ] := TMP [ i ] xor (X[ j ] and Y[ i - j ])

DEST[ i ] := TMP[ i ]

DEST[127] := 0;

RETURN DEST

// 128b vector

4-248

Vol. 2B

PCLMULQDQ—Carry-Less Multiplication Quadword

INSTRUCTION SET REFERENCE, M-U

PCLMULQDQ (SSE version)

IF imm8[0] = 0:

TEMP1 := SRC1.qword[0]

ELSE:

TEMP1 := SRC1.qword[1]

IF imm8[4] = 0:

TEMP2 := SRC2.qword[0]

ELSE:

TEMP2 := SRC2.qword[1]

DEST[127:0] := PCLMUL128(TEMP1, TEMP2)

DEST[MAXVL-1:128] (Unmodified)

VPCLMULQDQ (128b and 256b VEX encoded versions)

(KL,VL) = (1,128), (2,256)

FOR i= 0 to KL-1:

IF imm8[0] = 0:

TEMP1 := SRC1.xmm[i].qword[0]

ELSE:

TEMP1 := SRC1.xmm[i].qword[1]

IF imm8[4] = 0:

TEMP2 := SRC2.xmm[i].qword[0]

ELSE:

TEMP2 := SRC2.xmm[i].qword[1]

DEST.xmm[i] := PCLMUL128(TEMP1, TEMP2)

DEST[MAXVL-1:VL] := 0

VPCLMULQDQ (EVEX encoded version)

(KL,VL) = (1,128), (2,256), (4,512)

FOR i = 0 to KL-1:

IF imm8[0] = 0:

TEMP1 := SRC1.xmm[i].qword[0]

ELSE:

TEMP1 := SRC1.xmm[i].qword[1]

IF imm8[4] = 0:

TEMP2 := SRC2.xmm[i].qword[0]

ELSE:

TEMP2 := SRC2.xmm[i].qword[1]

DEST.xmm[i] := PCLMUL128(TEMP1, TEMP2)

DEST[MAXVL-1:VL] := 0

Intel C/C++ Compiler Intrinsic Equivalent

(V)PCLMULQDQ

__m128i _mm_clmulepi64_si128 (__m128i, __m128i, const int)

VPCLMULQDQ

__m256i _mm256_clmulepi64_epi128(__m256i, __m256i, const int);

VPCLMULQDQ

__m512i _mm512_clmulepi64_epi128(__m512i, __m512i, const int);

SIMD Floating-Point Exceptions

None.

PCLMULQDQ—Carry-Less Multiplication Quadword

Vol. 2B

4-249

INSTRUCTION SET REFERENCE, M-U

PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal

Opcode/

Op/ En

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F 74 /r¹

V/V

MMX

Compare packed bytes in mm/m64 and mm for

equality.

PCMPEQB mm, mm/m64

66 0F 74 /r

V/V

SSE2

Compare packed bytes in xmm2/m128 and

xmm1 for equality.

PCMPEQB xmm1, xmm2/m128

NP 0F 75 /r¹

V/V

MMX

Compare packed words in mm/m64 and mm

for equality.

PCMPEQW mm, mm/m64

66 0F 75 /r

V/V

SSE2

Compare packed words in xmm2/m128 and

xmm1 for equality.

PCMPEQW xmm1, xmm2/m128

NP 0F 76 /r¹

V/V

MMX

Compare packed doublewords in mm/m64 and

mm for equality.

PCMPEQD mm, mm/m64

66 0F 76 /r

V/V

SSE2

Compare packed doublewords in xmm2/m128

and xmm1 for equality.

PCMPEQD xmm1, xmm2/m128

VEX.128.66.0F.WIG 74 /r

V/V

AVX

Compare packed bytes in xmm3/m128 and

xmm2 for equality.

VPCMPEQB xmm1, xmm2, xmm3/m128

VEX.128.66.0F.WIG 75 /r

V/V

AVX

Compare packed words in xmm3/m128 and

xmm2 for equality.

VPCMPEQW xmm1, xmm2, xmm3/m128

VEX.128.66.0F.WIG 76 /r

V/V

AVX

Compare packed doublewords in xmm3/m128

and xmm2 for equality.

VPCMPEQD xmm1, xmm2, xmm3/m128

VEX.256.66.0F.WIG 74 /r

V/V

AVX2

Compare packed bytes in ymm3/m256 and

VPCMPEQB ymm1, ymm2, ymm3 /m256

ymm2 for equality.

VEX.256.66.0F.WIG 75 /r

V/V

AVX2

Compare packed words in ymm3/m256 and

ymm2 for equality.

VPCMPEQW ymm1, ymm2, ymm3 /m256

VEX.256.66.0F.WIG 76 /r

V/V

AVX2

Compare packed doublewords in ymm3/m256

and ymm2 for equality.

VPCMPEQD ymm1, ymm2, ymm3 /m256

EVEX.128.66.0F.W0 76 /r

V/V

AVX512VL

Compare Equal between int32 vector xmm2

VPCMPEQD k1 {k2}, xmm2, xmm3/m128/m32bcst

AVX512F

and int32 vector xmm3/m128/m32bcst, and

set vector mask k1 to reflect the

zero/nonzero status of each element of the

result, under writemask.

EVEX.256.66.0F.W0 76 /r

V/V

AVX512VL

Compare Equal between int32 vector ymm2

VPCMPEQD k1 {k2}, ymm2, ymm3/m256/m32bcst

AVX512F

and int32 vector ymm3/m256/m32bcst, and

set vector mask k1 to reflect the

zero/nonzero status of each element of the

result, under writemask.

EVEX.512.66.0F.W0 76 /r

V/V

AVX512F

Compare Equal between int32 vectors in

VPCMPEQD k1 {k2}, zmm2, zmm3/m512/m32bcst

zmm2 and zmm3/m512/m32bcst, and set

destination k1 according to the comparison

results under writemask k2.

EVEX.128.66.0F.WIG 74 /r

V/V

AVX512VL

Compare packed bytes in xmm3/m128 and

VPCMPEQB k1 {k2}, xmm2, xmm3 /m128

AVX512BW

xmm2 for equality and set vector mask k1 to

reflect the zero/nonzero status of each

element of the result, under writemask.

PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal

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INSTRUCTION SET REFERENCE, M-U

EVEX.256.66.0F.WIG 74 /r

V/V

AVX512VL

Compare packed bytes in ymm3/m256 and

VPCMPEQB k1 {k2}, ymm2, ymm3 /m256

AVX512BW

ymm2 for equality and set vector mask k1 to

reflect the zero/nonzero status of each

element of the result, under writemask.

EVEX.512.66.0F.WIG 74 /r

V/V

AVX512BW

Compare packed bytes in zmm3/m512 and

VPCMPEQB k1 {k2}, zmm2, zmm3 /m512

zmm2 for equality and set vector mask k1 to

reflect the zero/nonzero status of each

element of the result, under writemask.

EVEX.128.66.0F.WIG 75 /r

V/V

AVX512VL

Compare packed words in xmm3/m128 and

VPCMPEQW k1 {k2}, xmm2, xmm3 /m128

AVX512BW

xmm2 for equality and set vector mask k1 to

reflect the zero/nonzero status of each

element of the result, under writemask.

EVEX.256.66.0F.WIG 75 /r

V/V

AVX512VL

Compare packed words in ymm3/m256 and

VPCMPEQW k1 {k2}, ymm2, ymm3 /m256

AVX512BW

ymm2 for equality and set vector mask k1 to

reflect the zero/nonzero status of each

element of the result, under writemask.

EVEX.512.66.0F.WIG 75 /r

V/V

AVX512BW

Compare packed words in zmm3/m512 and

VPCMPEQW k1 {k2}, zmm2, zmm3 /m512

zmm2 for equality and set vector mask k1 to

reflect the zero/nonzero status of each

element of the result, under writemask.

NOTES:

1. See note in Section 2.5, “Intel® AVX and Intel® SSE Instruction Exception Specification” in the Intel® 64 and IA-32 Architectures Soft-

ware Developer’s Manual, Volume 2A and Section 23.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX

Registers” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Full Mem

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a SIMD compare for equality of the packed bytes, words, or doublewords in the destination operand (first

operand) and the source operand (second operand). If a pair of data elements is equal, the corresponding data

element in the destination operand is set to all 1s; otherwise, it is set to all 0s.

The (V)PCMPEQB instruction compares the corresponding bytes in the destination and source operands; the

(V)PCMPEQW instruction compares the corresponding words in the destination and source operands; and the

(V)PCMPEQD instruction compares the corresponding doublewords in the destination and source operands.

In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to

access additional registers (XMM8-XMM15).

Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The

destination operand can be an MMX technology register.

128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The

first source and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM destination

VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The

first source and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM register

are zeroed.

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PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal

INSTRUCTION SET REFERENCE, M-U

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

EVEX encoded VPCMPEQD: The first source operand (second operand) is a ZMM/YMM/XMM register. The second

source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector

broadcasted from a 32-bit memory location. The destination operand (first operand) is a mask register updated

according to the writemask k2.

EVEX encoded VPCMPEQB/W: The first source operand (second operand) is a ZMM/YMM/XMM register. The second

source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand

(first operand) is a mask register updated according to the writemask k2.

Operation

PCMPEQB (with 64-bit operands)

IF DEST[7:0] = SRC[7:0]

THEN DEST[7:0) := FFH;

ELSE DEST[7:0] := 0; FI;

(* Continue comparison of 2nd through 7th bytes in DEST and SRC *)

IF DEST[63:56] = SRC[63:56]

THEN DEST[63:56] := FFH;

ELSE DEST[63:56] := 0; FI;

COMPARE_BYTES_EQUAL (SRC1, SRC2)

IF SRC1[7:0] = SRC2[7:0]

THEN DEST[7:0] := FFH;

ELSE DEST[7:0] := 0; FI;

(* Continue comparison of 2nd through 15th bytes in SRC1 and SRC2 *)

IF SRC1[127:120] = SRC2[127:120]

THEN DEST[127:120] := FFH;

ELSE DEST[127:120] := 0; FI;

COMPARE_WORDS_EQUAL (SRC1, SRC2)

IF SRC1[15:0] = SRC2[15:0]

THEN DEST[15:0] := FFFFH;

ELSE DEST[15:0] := 0; FI;

(* Continue comparison of 2nd through 7th 16-bit words in SRC1 and SRC2 *)

IF SRC1[127:112] = SRC2[127:112]

THEN DEST[127:112] := FFFFH;

ELSE DEST[127:112] := 0; FI;

COMPARE_DWORDS_EQUAL (SRC1, SRC2)

IF SRC1[31:0] = SRC2[31:0]

THEN DEST[31:0] := FFFFFFFFH;

ELSE DEST[31:0] := 0; FI;

(* Continue comparison of 2nd through 3rd 32-bit dwords in SRC1 and SRC2 *)

IF SRC1[127:96] = SRC2[127:96]

THEN DEST[127:96] := FFFFFFFFH;

ELSE DEST[127:96] := 0; FI;

PCMPEQB (with 128-bit operands)

DEST[127:0] := COMPARE_BYTES_EQUAL(DEST[127:0],SRC[127:0])

DEST[MAXVL-1:128] (Unmodified)

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INSTRUCTION SET REFERENCE, M-U

VPCMPEQB (VEX.128 encoded version)

DEST[127:0] := COMPARE_BYTES_EQUAL(SRC1[127:0],SRC2[127:0])

DEST[MAXVL-1:128] := 0

VPCMPEQB (VEX.256 encoded version)

DEST[127:0] := COMPARE_BYTES_EQUAL(SRC1[127:0],SRC2[127:0])

DEST[255:128] := COMPARE_BYTES_EQUAL(SRC1[255:128],SRC2[255:128])

DEST[MAXVL-1:256] := 0

VPCMPEQB (EVEX encoded versions)

(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j := 0 TO KL-1

i := j * 8

IF k2[j] OR *no writemask*

THEN

/* signed comparison */

CMP := SRC1[i+7:i] == SRC2[i+7:i];

IF CMP = TRUE

THEN DEST[j] := 1;

ELSE DEST[j] := 0; FI;

ELSE

DEST[j] := 0

; zeroing-masking onlyFI;

FI;

ENDFOR

DEST[MAX_KL-1:KL] := 0

PCMPEQW (with 64-bit operands)

IF DEST[15:0] = SRC[15:0]

THEN DEST[15:0] := FFFFH;

ELSE DEST[15:0] := 0; FI;

(* Continue comparison of 2nd and 3rd words in DEST and SRC *)

IF DEST[63:48] = SRC[63:48]

THEN DEST[63:48] := FFFFH;

ELSE DEST[63:48] := 0; FI;

PCMPEQW (with 128-bit operands)

DEST[127:0] := COMPARE_WORDS_EQUAL(DEST[127:0],SRC[127:0])

DEST[MAXVL-1:128] (Unmodified)

VPCMPEQW (VEX.128 encoded version)

DEST[127:0] := COMPARE_WORDS_EQUAL(SRC1[127:0],SRC2[127:0])

DEST[MAXVL-1:128] := 0

VPCMPEQW (VEX.256 encoded version)

DEST[127:0] := COMPARE_WORDS_EQUAL(SRC1[127:0],SRC2[127:0])

DEST[255:128] := COMPARE_WORDS_EQUAL(SRC1[255:128],SRC2[255:128])

DEST[MAXVL-1:256] := 0

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PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal

INSTRUCTION SET REFERENCE, M-U

VPCMPEQW (EVEX encoded versions)

(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j := 0 TO KL-1

i := j * 16

IF k2[j] OR *no writemask*

THEN

/* signed comparison */

CMP := SRC1[i+15:i] == SRC2[i+15:i];

IF CMP = TRUE

THEN DEST[j] := 1;

ELSE DEST[j] := 0; FI;

ELSE

DEST[j] := 0

; zeroing-masking onlyFI;

FI;

ENDFOR

DEST[MAX_KL-1:KL] := 0

PCMPEQD (with 64-bit operands)

IF DEST[31:0] = SRC[31:0]

THEN DEST[31:0] := FFFFFFFFH;

ELSE DEST[31:0] := 0; FI;

IF DEST[63:32] = SRC[63:32]

THEN DEST[63:32] := FFFFFFFFH;

ELSE DEST[63:32] := 0; FI;

PCMPEQD (with 128-bit operands)

DEST[127:0] := COMPARE_DWORDS_EQUAL(DEST[127:0],SRC[127:0])

DEST[MAXVL-1:128] (Unmodified)

VPCMPEQD (VEX.128 encoded version)

DEST[127:0] := COMPARE_DWORDS_EQUAL(SRC1[127:0],SRC2[127:0])

DEST[MAXVL-1:128] := 0

VPCMPEQD (VEX.256 encoded version)

DEST[127:0] := COMPARE_DWORDS_EQUAL(SRC1[127:0],SRC2[127:0])

DEST[255:128] := COMPARE_DWORDS_EQUAL(SRC1[255:128],SRC2[255:128])

DEST[MAXVL-1:256] := 0

VPCMPEQD (EVEX encoded versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j := 0 TO KL-1

i := j * 32

IF k2[j] OR *no writemask*

THEN

/* signed comparison */

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN CMP := SRC1[i+31:i] = SRC2[31:0];

ELSE CMP := SRC1[i+31:i] = SRC2[i+31:i];

FI;

IF CMP = TRUE

THEN DEST[j] := 1;

ELSE DEST[j] := 0; FI;

ELSE

DEST[j] := 0

; zeroing-masking only

FI;

ENDFOR

DEST[MAX_KL-1:KL] := 0

PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal

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INSTRUCTION SET REFERENCE, M-U

Intel C/C++ Compiler Intrinsic Equivalents

VPCMPEQB __mmask64 _mm512_cmpeq_epi8_mask(__m512i a, __m512i b);

VPCMPEQB __mmask64 _mm512_mask_cmpeq_epi8_mask(__mmask64 k, __m512i a, __m512i b);

VPCMPEQB __mmask32 _mm256_cmpeq_epi8_mask(__m256i a, __m256i b);

VPCMPEQB __mmask32 _mm256_mask_cmpeq_epi8_mask(__mmask32 k, __m256i a, __m256i b);

VPCMPEQB __mmask16 _mm_cmpeq_epi8_mask(__m128i a, __m128i b);

VPCMPEQB __mmask16 _mm_mask_cmpeq_epi8_mask(__mmask16 k, __m128i a, __m128i b);

VPCMPEQW __mmask32 _mm512_cmpeq_epi16_mask(__m512i a, __m512i b);

VPCMPEQW __mmask32 _mm512_mask_cmpeq_epi16_mask(__mmask32 k, __m512i a, __m512i b);

VPCMPEQW __mmask16 _mm256_cmpeq_epi16_mask(__m256i a, __m256i b);

VPCMPEQW __mmask16 _mm256_mask_cmpeq_epi16_mask(__mmask16 k, __m256i a, __m256i b);

VPCMPEQW __mmask8 _mm_cmpeq_epi16_mask(__m128i a, __m128i b);

VPCMPEQW __mmask8 _mm_mask_cmpeq_epi16_mask(__mmask8 k, __m128i a, __m128i b);

VPCMPEQD __mmask16 _mm512_cmpeq_epi32_mask( __m512i a, __m512i b);

VPCMPEQD __mmask16 _mm512_mask_cmpeq_epi32_mask(__mmask16 k, __m512i a, __m512i b);

VPCMPEQD __mmask8 _mm256_cmpeq_epi32_mask(__m256i a, __m256i b);

VPCMPEQD __mmask8 _mm256_mask_cmpeq_epi32_mask(__mmask8 k, __m256i a, __m256i b);

VPCMPEQD __mmask8 _mm_cmpeq_epi32_mask(__m128i a, __m128i b);

VPCMPEQD __mmask8 _mm_mask_cmpeq_epi32_mask(__mmask8 k, __m128i a, __m128i b);

PCMPEQB: __m64 _mm_cmpeq_pi8 (__m64 m1, __m64 m2)

PCMPEQW: __m64 _mm_cmpeq_pi16 (__m64 m1, __m64 m2)

PCMPEQD: __m64 _mm_cmpeq_pi32 (__m64 m1, __m64 m2)

(V)PCMPEQB: __m128i _mm_cmpeq_epi8 ( __m128i a, __m128i b)

(V)PCMPEQW: __m128i _mm_cmpeq_epi16 ( __m128i a, __m128i b)

(V)PCMPEQD: __m128i _mm_cmpeq_epi32 ( __m128i a, __m128i b)

VPCMPEQB:

__m256i _mm256_cmpeq_epi8 ( __m256i a, __m256i b)

VPCMPEQW:

__m256i _mm256_cmpeq_epi16 ( __m256i a, __m256i b)

VPCMPEQD:

__m256i _mm256_cmpeq_epi32 ( __m256i a, __m256i b)

Flags Affected

None.

SIMD Floating-Point Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded VPCMPEQD, see Table 2-49, “Type E4 Class Exception Conditions”.

EVEX-encoded VPCMPEQB/W, see Exceptions Type E4.nb in Table 2-49, “Type E4 Class Exception Conditions”.

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PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal

INSTRUCTION SET REFERENCE, M-U

PCMPEQQ—Compare Packed Qword Data for Equal

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

66 0F 38 29 /r

V/V

SSE4_1

Compare packed qwords in xmm2/m128 and

PCMPEQQ xmm1, xmm2/m128

xmm1 for equality.

VEX.128.66.0F38.WIG 29 /r

V/V

AVX

Compare packed quadwords in xmm3/m128

VPCMPEQQ xmm1, xmm2, xmm3/m128

and xmm2 for equality.

VEX.256.66.0F38.WIG 29 /r

V/V

AVX2

Compare packed quadwords in ymm3/m256

VPCMPEQQ ymm1, ymm2, ymm3 /m256

and ymm2 for equality.

EVEX.128.66.0F38.W1 29 /r

V/V

AVX512VL

Compare Equal between int64 vector xmm2

VPCMPEQQ k1 {k2}, xmm2, xmm3/m128/m64bcst

AVX512F

and int64 vector xmm3/m128/m64bcst, and

set vector mask k1 to reflect the zero/nonzero

status of each element of the result, under

writemask.

EVEX.256.66.0F38.W1 29 /r

V/V

AVX512VL

Compare Equal between int64 vector ymm2

VPCMPEQQ k1 {k2}, ymm2, ymm3/m256/m64bcst

AVX512F

and int64 vector ymm3/m256/m64bcst, and

set vector mask k1 to reflect the zero/nonzero

status of each element of the result, under

writemask.

EVEX.512.66.0F38.W1 29 /r

V/V

AVX512F

Compare Equal between int64 vector zmm2

VPCMPEQQ k1 {k2}, zmm2, zmm3/m512/m64bcst

and int64 vector zmm3/m512/m64bcst, and

set vector mask k1 to reflect the zero/nonzero

status of each element of the result, under

writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs an SIMD compare for equality of the packed quadwords in the destination operand (first operand) and the

source operand (second operand). If a pair of data elements is equal, the corresponding data element in the desti-

nation is set to all 1s; otherwise, it is set to 0s.

128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The

first source and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM destination

VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The

first source and destination operands are XMM registers. Bits (MAXVL-1:128) of the corresponding YMM register

are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register

or a 256-bit memory location. The destination operand is a YMM register.

EVEX encoded VPCMPEQQ: The first source operand (second operand) is a ZMM/YMM/XMM register. The second

source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector

broadcasted from a 64-bit memory location. The destination operand (first operand) is a mask register updated

according to the writemask k2.

PCMPEQQ—Compare Packed Qword Data for Equal

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4-257

INSTRUCTION SET REFERENCE, M-U

Operation

PCMPEQQ (with 128-bit operands)

IF (DEST[63:0] = SRC[63:0])

THEN DEST[63:0] := FFFFFFFFFFFFFFFFH;

ELSE DEST[63:0] := 0; FI;

IF (DEST[127:64] = SRC[127:64])

THEN DEST[127:64] := FFFFFFFFFFFFFFFFH;

ELSE DEST[127:64] := 0; FI;

DEST[MAXVL-1:128] (Unmodified)

COMPARE_QWORDS_EQUAL (SRC1, SRC2)

IF SRC1[63:0] = SRC2[63:0]

THEN DEST[63:0] := FFFFFFFFFFFFFFFFH;

ELSE DEST[63:0] := 0; FI;

IF SRC1[127:64] = SRC2[127:64]

THEN DEST[127:64] := FFFFFFFFFFFFFFFFH;

ELSE DEST[127:64] := 0; FI;

VPCMPEQQ (VEX.128 encoded version)

DEST[127:0] := COMPARE_QWORDS_EQUAL(SRC1,SRC2)

DEST[MAXVL-1:128] := 0

VPCMPEQQ (VEX.256 encoded version)

DEST[127:0] := COMPARE_QWORDS_EQUAL(SRC1[127:0],SRC2[127:0])

DEST[255:128] := COMPARE_QWORDS_EQUAL(SRC1[255:128],SRC2[255:128])

DEST[MAXVL-1:256] := 0

VPCMPEQQ (EVEX encoded versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j := 0 TO KL-1

i := j * 64

IF k2[j] OR *no writemask*

THEN

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN CMP := SRC1[i+63:i] = SRC2[63:0];

ELSE CMP := SRC1[i+63:i] = SRC2[i+63:i];

FI;

IF CMP = TRUE

THEN DEST[j] := 1;

ELSE DEST[j] := 0; FI;

ELSE

DEST[j] := 0

; zeroing-masking only

FI;

ENDFOR

DEST[MAX_KL-1:KL] := 0

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PCMPEQQ—Compare Packed Qword Data for Equal

INSTRUCTION SET REFERENCE, M-U

Intel C/C++ Compiler Intrinsic Equivalent

VPCMPEQQ __mmask8 _mm512_cmpeq_epi64_mask( __m512i a, __m512i b);

VPCMPEQQ __mmask8 _mm512_mask_cmpeq_epi64_mask(__mmask8 k, __m512i a, __m512i b);

VPCMPEQQ __mmask8 _mm256_cmpeq_epi64_mask( __m256i a, __m256i b);

VPCMPEQQ __mmask8 _mm256_mask_cmpeq_epi64_mask(__mmask8 k, __m256i a, __m256i b);

VPCMPEQQ __mmask8 _mm_cmpeq_epi64_mask( __m128i a, __m128i b);

VPCMPEQQ __mmask8 _mm_mask_cmpeq_epi64_mask(__mmask8 k, __m128i a, __m128i b);

(V)PCMPEQQ:

__m128i _mm_cmpeq_epi64(__m128i a, __m128i b);

VPCMPEQQ:

__m256i _mm256_cmpeq_epi64( __m256i a, __m256i b);

Flags Affected

None.

SIMD Floating-Point Exceptions

None.

Other Exceptions

Non-EVEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.

EVEX-encoded VPCMPEQQ, see Table 2-49, “Type E4 Class Exception Conditions”.

PCMPEQQ—Compare Packed Qword Data for Equal

Vol. 2B

4-259

INSTRUCTION SET REFERENCE, M-U

PCMPESTRI—Packed Compare Explicit Length Strings, Return Index

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

66 0F 3A 61 /r imm8

RMI

V/V

SSE4_2

Perform a packed comparison of string data

PCMPESTRI xmm1, xmm2/m128, imm8

with explicit lengths, generating an index, and

storing the result in ECX.

VEX.128.66.0F3A 61 /r ib

RMI

V/V

AVX

Perform a packed comparison of string data

VPCMPESTRI xmm1, xmm2/m128, imm8

with explicit lengths, generating an index, and

storing the result in ECX.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RMI

ModRM:reg (r)

ModRM:r/m (r)

imm8

N/A

Description

The instruction compares and processes data from two string fragments based on the encoded value in the imm8

control byte (see Section 4.1, “Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMP-

ISTRM”), and generates an index stored to the count register (ECX).

Each string fragment is represented by two values. The first value is an xmm (or possibly m128 for the second

operand) which contains the data elements of the string (byte or word data). The second value is stored in an input

length register. The input length register is EAX/RAX (for xmm1) or EDX/RDX (for xmm2/m128). The length repre-

sents the number of bytes/words which are valid for the respective xmm/m128 data.

The length of each input is interpreted as being the absolute-value of the value in the length register. The absolute-

value computation saturates to 16 (for bytes) and 8 (for words), based on the value of imm8[bit3] when the value

in the length register is greater than 16 (8) or less than -16 (-8).

The comparison and aggregation operations are performed according to the encoded value of imm8 bit fields (see

Section 4.1). The index of the first (or last, according to imm8[6]) set bit of IntRes2 (see Section 4.1.4) is returned

in ECX. If no bits are set in IntRes2, ECX is set to 16 (8).

Note that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant informa-

tion:

CFlag - Reset if IntRes2 is equal to zero, set otherwise

ZFlag - Set if absolute-value of EDX is < 16 (8), reset otherwise

SFlag - Set if absolute-value of EAX is < 16 (8), reset otherwise

OFlag - IntRes2[0]

AFlag - Reset

PFlag - Reset

Effective Operand Size

Operating mode/size

Operand 1

Operand 2

Length 1

Length 2

Result

16 bit

xmm

xmm/m128

EAX

EDX

ECX

32 bit

xmm

xmm/m128

EAX

EDX

ECX

64 bit

xmm

xmm/m128

EAX

EDX

ECX

64 bit + REX.W

xmm

xmm/m128

RAX

RDX

ECX

Intel C/C++ Compiler Intrinsic Equivalent For Returning Index

int

_mm_cmpestri (__m128i a, int la, __m128i b, int lb, const int mode);

4-260

Vol. 2B

PCMPESTRI—Packed Compare Explicit Length Strings, Return Index

INSTRUCTION SET REFERENCE, M-U

Intel C/C++ Compiler Intrinsics For Reading EFlag Results

int

_mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode);

int

_mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode);

int

_mm_cmpestro (__m128i a, int la, __m128i b, int lb, const int mode);

int

_mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode);

int

_mm_cmpestrz (__m128i a, int la, __m128i b, int lb, const int mode);

SIMD Floating-Point Exceptions

None.

Other Exceptions

See Table 2-21, “Type 4 Class Exception Conditions”; additionally, this instruction does not cause #GP if the

memory operand is not aligned to 16 Byte boundary, and:

#UD

If VEX.L = 1.

If VEX.vvvv ≠ 1111B.

PCMPESTRI—Packed Compare Explicit Length Strings, Return Index

Vol. 2B

4-261

INSTRUCTION SET REFERENCE, M-U

PCMPESTRM—Packed Compare Explicit Length Strings, Return Mask

Opcode/

Op/

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

66 0F 3A 60 /r imm8

RMI

V/V

SSE4_2

Perform a packed comparison of string data

PCMPESTRM xmm1, xmm2/m128, imm8

with explicit lengths, generating a mask, and

storing the result in XMM0.

VEX.128.66.0F3A 60 /r ib

RMI

V/V

AVX

Perform a packed comparison of string data

VPCMPESTRM xmm1, xmm2/m128, imm8

with explicit lengths, generating a mask, and

storing the result in XMM0.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RMI

ModRM:reg (r)

ModRM:r/m (r)

imm8

N/A

Description

The instruction compares data from two string fragments based on the encoded value in the imm8 contol byte (see

Section 4.1, “Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM”), and gener-

ates a mask stored to XMM0.