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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 79

INSTRUCTION SET REFERENCE, M-U

MOVSD—Move or Merge Scalar Double Precision Floating-Point Value

Opcode/

Op / En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

F2 0F 10 /r

A

V/V

SSE2

Move scalar double precision floating-point value

MOVSD xmm1, xmm2

from xmm2 to xmm1 register.

F2 0F 10 /r

A

V/V

SSE2

Load scalar double precision floating-point value

MOVSD xmm1, m64

from m64 to xmm1 register.

F2 0F 11 /r

C

V/V

SSE2

Move scalar double precision floating-point value

MOVSD xmm1/m64, xmm2

from xmm2 register to xmm1/m64.

VEX.LIG.F2.0F.WIG 10 /r

B

V/V

AVX

Merge scalar double precision floating-point value

VMOVSD xmm1, xmm2, xmm3

from xmm2 and xmm3 to xmm1 register.

VEX.LIG.F2.0F.WIG 10 /r

D

V/V

AVX

Load scalar double precision floating-point value

VMOVSD xmm1, m64

from m64 to xmm1 register.

VEX.LIG.F2.0F.WIG 11 /r

E

V/V

AVX

Merge scalar double precision floating-point value

VMOVSD xmm1, xmm2, xmm3

from xmm2 and xmm3 registers to xmm1.

VEX.LIG.F2.0F.WIG 11 /r

C

V/V

AVX

Store scalar double precision floating-point value

VMOVSD m64, xmm1

from xmm1 register to m64.

EVEX.LLIG.F2.0F.W1 10 /r

B

V/V

AVX512F

Merge scalar double precision floating-point value

VMOVSD xmm1 {k1}{z}, xmm2, xmm3

from xmm2 and xmm3 registers to xmm1 under

writemask k1.

EVEX.LLIG.F2.0F.W1 10 /r

F

V/V

AVX512F

Load scalar double precision floating-point value

VMOVSD xmm1 {k1}{z}, m64

from m64 to xmm1 register under writemask k1.

EVEX.LLIG.F2.0F.W1 11 /r

E

V/V

AVX512F

Merge scalar double precision floating-point value

VMOVSD xmm1 {k1}{z}, xmm2, xmm3

from xmm2 and xmm3 registers to xmm1 under

writemask k1.

EVEX.LLIG.F2.0F.W1 11 /r

G

V/V

AVX512F

Store scalar double precision floating-point value

VMOVSD m64 {k1}, xmm1

from xmm1 register to m64 under writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

N/A

ModRM:r/m (w)

ModRM:reg (r)

N/A

N/A

D

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

E

N/A

ModRM:r/m (w)

EVEX.vvvv (r)

ModRM:reg (r)

N/A

F

Tuple1 Scalar

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

G

Tuple1 Scalar

ModRM:r/m (w)

ModRM:reg (r)

N/A

N/A

MOVSD—Move or Merge Scalar Double Precision Floating-Point Value

Vol. 2B

4-117

INSTRUCTION SET REFERENCE, M-U

MOVSHDUP—Replicate Single Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

F3 0F 16 /r

A

V/V

SSE3

Move odd index single precision floating-point values from

MOVSHDUP xmm1, xmm2/m128

xmm2/mem and duplicate each element into xmm1.

VEX.128.F3.0F.WIG 16 /r

A

V/V

AVX

Move odd index single precision floating-point values from

VMOVSHDUP xmm1, xmm2/m128

xmm2/mem and duplicate each element into xmm1.

VEX.256.F3.0F.WIG 16 /r

A

V/V

AVX

Move odd index single precision floating-point values from

VMOVSHDUP ymm1, ymm2/m256

ymm2/mem and duplicate each element into ymm1.

EVEX.128.F3.0F.W0 16 /r

B

V/V

AVX512VL

Move odd index single precision floating-point values from

VMOVSHDUP xmm1 {k1}{z},

AVX512F

xmm2/m128 and duplicate each element into xmm1 under

xmm2/m128

writemask.

EVEX.256.F3.0F.W0 16 /r

B

V/V

AVX512VL

Move odd index single precision floating-point values from

VMOVSHDUP ymm1 {k1}{z},

AVX512F

ymm2/m256 and duplicate each element into ymm1 under

ymm2/m256

writemask.

EVEX.512.F3.0F.W0 16 /r

B

V/V

AVX512F

Move odd index single precision floating-point values from

VMOVSHDUP zmm1 {k1}{z},

zmm2/m512 and duplicate each element into zmm1 under

zmm2/m512

writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

B

Full Mem

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Duplicates odd-indexed single precision floating-point values from the source operand (the second operand) to

adjacent element pair in the destination operand (the first operand). See Figure 4-3. The source operand is an

XMM, YMM or ZMM register or 128, 256 or 512-bit memory location and the destination operand is an XMM, YMM

or ZMM register.

128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding destination register remain unchanged.

VEX.128 encoded version: Bits (MAXVL-1:128) of the destination register are zeroed.

VEX.256 encoded version: Bits (MAXVL-1:256) of the destination register are zeroed.

EVEX encoded version: The destination operand is updated at 32-bit granularity according to the writemask.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

SRC

X7

X6

X5

X4

X3

X2

X1

X0

DEST

X7

X7

X5

X5

X3

X3

X1

X1

Figure 4-3. MOVSHDUP Operation

4-120

Vol. 2B

MOVSHDUP—Replicate Single Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

MOVSLDUP—Replicate Single Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

F3 0F 12 /r

A

V/V

SSE3

Move even index single precision floating-point values from

MOVSLDUP xmm1, xmm2/m128

xmm2/mem and duplicate each element into xmm1.

VEX.128.F3.0F.WIG 12 /r

A

V/V

AVX

Move even index single precision floating-point values from

VMOVSLDUP xmm1, xmm2/m128

xmm2/mem and duplicate each element into xmm1.

VEX.256.F3.0F.WIG 12 /r

A

V/V

AVX

Move even index single precision floating-point values from

VMOVSLDUP ymm1, ymm2/m256

ymm2/mem and duplicate each element into ymm1.

EVEX.128.F3.0F.W0 12 /r

B

V/V

AVX512VL

Move even index single precision floating-point values from

VMOVSLDUP xmm1 {k1}{z},

AVX512F

xmm2/m128 and duplicate each element into xmm1 under

xmm2/m128

writemask.

EVEX.256.F3.0F.W0 12 /r

B

V/V

AVX512VL

Move even index single precision floating-point values from

VMOVSLDUP ymm1 {k1}{z},

AVX512F

ymm2/m256 and duplicate each element into ymm1 under

ymm2/m256

writemask.

EVEX.512.F3.0F.W0 12 /r

B

V/V

AVX512F

Move even index single precision floating-point values from

VMOVSLDUP zmm1 {k1}{z},

zmm2/m512 and duplicate each element into zmm1 under

zmm2/m512

writemask.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

B

Full Mem

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Duplicates even-indexed single precision floating-point values from the source operand (the second operand). See

Figure 4-4. The source operand is an XMM, YMM or ZMM register or 128, 256 or 512-bit memory location and the

destination operand is an XMM, YMM or ZMM register.

128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding destination register remain unchanged.

VEX.128 encoded version: Bits (MAXVL-1:128) of the destination register are zeroed.

VEX.256 encoded version: Bits (MAXVL-1:256) of the destination register are zeroed.

EVEX encoded version: The destination operand is updated at 32-bit granularity according to the writemask.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

SRC

X7

X6

X5

X4

X3

X2

X1

X0

DEST

X6

X6

X4

X4

X2

X2

X0

X0

Figure 4-4. MOVSLDUP Operation

MOVSLDUP—Replicate Single Precision Floating-Point Values

Vol. 2B

4-123

INSTRUCTION SET REFERENCE, M-U

MOVSS—Move or Merge Scalar Single Precision Floating-Point Value

Opcode/

Op / En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

F3 0F 10 /r

A

V/V

SSE

Merge scalar single precision floating-point value

MOVSS xmm1, xmm2

from xmm2 to xmm1 register.

F3 0F 10 /r

A

V/V

SSE

Load scalar single precision floating-point value from

MOVSS xmm1, m32

m32 to xmm1 register.

VEX.LIG.F3.0F.WIG 10 /r

B

V/V

AVX

Merge scalar single precision floating-point value

VMOVSS xmm1, xmm2, xmm3

from xmm2 and xmm3 to xmm1 register

VEX.LIG.F3.0F.WIG 10 /r

D

V/V

AVX

Load scalar single precision floating-point value from

VMOVSS xmm1, m32

m32 to xmm1 register.

F3 0F 11 /r

C

V/V

SSE

Move scalar single precision floating-point value from

MOVSS xmm2/m32, xmm1

xmm1 register to xmm2/m32.

VEX.LIG.F3.0F.WIG 11 /r

E

V/V

AVX

Move scalar single precision floating-point value from

VMOVSS xmm1, xmm2, xmm3

xmm2 and xmm3 to xmm1 register.

VEX.LIG.F3.0F.WIG 11 /r

C

V/V

AVX

Move scalar single precision floating-point value from

VMOVSS m32, xmm1

xmm1 register to m32.

EVEX.LLIG.F3.0F.W0 10 /r

B

V/V

AVX512F

Move scalar single precision floating-point value from

VMOVSS xmm1 {k1}{z}, xmm2, xmm3

xmm2 and xmm3 to xmm1 register under writemask

k1.

EVEX.LLIG.F3.0F.W0 10 /r

F

V/V

AVX512F

Move scalar single precision floating-point values

VMOVSS xmm1 {k1}{z}, m32

from m32 to xmm1 under writemask k1.

EVEX.LLIG.F3.0F.W0 11 /r

E

V/V

AVX512F

Move scalar single precision floating-point value from

VMOVSS xmm1 {k1}{z}, xmm2, xmm3

xmm2 and xmm3 to xmm1 register under writemask

k1.

EVEX.LLIG.F3.0F.W0 11 /r

G

V/V

AVX512F

Move scalar single precision floating-point values

VMOVSS m32 {k1}, xmm1

from xmm1 to m32 under writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

N/A

ModRM:r/m (w)

ModRM:reg (r)

N/A

N/A

D

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

E

N/A

ModRM:r/m (w)

EVEX.vvvv (r)

ModRM:reg (r)

N/A

F

Tuple1 Scalar

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

G

Tuple1 Scalar

ModRM:r/m (w)

ModRM:reg (r)

N/A

N/A

4-126

Vol. 2B

MOVSS—Move or Merge Scalar Single Precision Floating-Point Value

INSTRUCTION SET REFERENCE, M-U

MOVSX/MOVSXD—Move With Sign-Extension

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

0F BE /r

MOVSX r16, r/m8

RM

Valid

Valid

Move byte to word with sign-extension.

0F BE /r

MOVSX r32, r/m8

RM

Valid

Valid

Move byte to doubleword with sign-

extension.

REX.W + 0F BE /r

MOVSX r64, r/m8

RM

Valid

N.E.

Move byte to quadword with sign-extension.

0F BF /r

MOVSX r32, r/m16

RM

Valid

Valid

Move word to doubleword, with sign-

extension.

REX.W + 0F BF /r

MOVSX r64, r/m16

RM

Valid

N.E.

Move word to quadword with sign-extension.

63 /r¹

MOVSXD r16, r/m16

RM

Valid

N.E.

Move word to word with sign-extension.

63 /r¹

MOVSXD r32, r/m32

RM

Valid

N.E.

Move doubleword to doubleword with sign-

extension.

REX.W + 63 /r

MOVSXD r64, r/m32

RM

Valid

N.E.

Move doubleword to quadword with sign-

extension.

NOTES:

1. The use of MOVSXD without REX.W in 64-bit mode is discouraged. Regular MOV should be used instead of using MOVSXD without

REX.W.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Copies the contents of the source operand (register or memory location) to the destination operand (register) and

sign extends the value to 16 or 32 bits (see Figure 7-6 in the Intel® 64 and IA-32 Architectures Software Devel-

oper’s Manual, Volume 1). The size of the converted value depends on the operand-size attribute.

In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to addi-

tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the

beginning of this section for encoding data and limits.

Operation

DEST := SignExtend(SRC);

Flags Affected

None.

Protected Mode Exceptions

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register contains a NULL segment selector.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used.

4-130

Vol. 2B

MOVSX/MOVSXD—Move With Sign-Extension

INSTRUCTION SET REFERENCE, M-U

MOVUPD—Move Unaligned Packed Double Precision Floating-Point Values

Opcode/

Op / En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

66 0F 10 /r

A

V/V

SSE2

Move unaligned packed double precision floating-

MOVUPD xmm1, xmm2/m128

point from xmm2/mem to xmm1.

66 0F 11 /r

B

V/V

SSE2

Move unaligned packed double precision floating-

MOVUPD xmm2/m128, xmm1

point from xmm1 to xmm2/mem.

VEX.128.66.0F.WIG 10 /r

A

V/V

AVX

Move unaligned packed double precision floating-

VMOVUPD xmm1, xmm2/m128

point from xmm2/mem to xmm1.

VEX.128.66.0F.WIG 11 /r

B

V/V

AVX

Move unaligned packed double precision floating-

VMOVUPD xmm2/m128, xmm1

point from xmm1 to xmm2/mem.

VEX.256.66.0F.WIG 10 /r

A

V/V

AVX

Move unaligned packed double precision floating-

VMOVUPD ymm1, ymm2/m256

point from ymm2/mem to ymm1.

VEX.256.66.0F.WIG 11 /r

B

V/V

AVX

Move unaligned packed double precision floating-

VMOVUPD ymm2/m256, ymm1

point from ymm1 to ymm2/mem.

EVEX.128.66.0F.W1 10 /r

C

V/V

AVX512VL

Move unaligned packed double precision floating-

VMOVUPD xmm1 {k1}{z}, xmm2/m128

AVX512F

point from xmm2/m128 to xmm1 using

writemask k1.

EVEX.128.66.0F.W1 11 /r

D

V/V

AVX512VL

Move unaligned packed double precision floating-

VMOVUPD xmm2/m128 {k1}{z}, xmm1

AVX512F

point from xmm1 to xmm2/m128 using

writemask k1.

EVEX.256.66.0F.W1 10 /r

C

V/V

AVX512VL

Move unaligned packed double precision floating-

VMOVUPD ymm1 {k1}{z}, ymm2/m256

AVX512F

point from ymm2/m256 to ymm1 using

writemask k1.

EVEX.256.66.0F.W1 11 /r

D

V/V

AVX512VL

Move unaligned packed double precision floating-

VMOVUPD ymm2/m256 {k1}{z}, ymm1

AVX512F

point from ymm1 to ymm2/m256 using

writemask k1.

EVEX.512.66.0F.W1 10 /r

C

V/V

AVX512F

Move unaligned packed double precision floating-

VMOVUPD zmm1 {k1}{z}, zmm2/m512

point values from zmm2/m512 to zmm1 using

writemask k1.

EVEX.512.66.0F.W1 11 /r

D

V/V

AVX512F

Move unaligned packed double precision floating-

VMOVUPD zmm2/m512 {k1}{z}, zmm1

point values from zmm1 to zmm2/m512 using

writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:r/m (w)

ModRM:reg (r)

N/A

N/A

C

Full Mem

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

D

Full Mem

ModRM:r/m (w)

ModRM:reg (r)

N/A

N/A

Description

Note: VEX.vvvv and EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

EVEX.512 encoded version:

Moves 512 bits of packed double precision floating-point values from the source operand (second operand) to the

destination operand (first operand). This instruction can be used to load a ZMM register from a float64 memory

location, to store the contents of a ZMM register into a memory. The destination operand is updated according to

the writemask.

4-132

Vol. 2B

MOVUPD—Move Unaligned Packed Double Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

MOVUPS—Move Unaligned Packed Single Precision Floating-Point Values

Opcode/

Op / En

64/32

CPUID

Description

Instruction

bit Mode

Feature

Support

Flag

NP 0F 10 /r

A

V/V

SSE

Move unaligned packed single precision

MOVUPS xmm1, xmm2/m128

floating-point from xmm2/mem to xmm1.

NP 0F 11 /r

B

V/V

SSE

Move unaligned packed single precision

MOVUPS xmm2/m128, xmm1

floating-point from xmm1 to xmm2/mem.

VEX.128.0F.WIG 10 /r

A

V/V

AVX

Move unaligned packed single precision

VMOVUPS xmm1, xmm2/m128

floating-point from xmm2/mem to xmm1.

VEX.128.0F.WIG 11 /r

B

V/V

AVX

Move unaligned packed single precision

VMOVUPS xmm2/m128, xmm1

floating-point from xmm1 to xmm2/mem.

VEX.256.0F.WIG 10 /r

A

V/V

AVX

Move unaligned packed single precision

VMOVUPS ymm1, ymm2/m256

floating-point from ymm2/mem to ymm1.

VEX.256.0F.WIG 11 /r

B

V/V

AVX

Move unaligned packed single precision

VMOVUPS ymm2/m256, ymm1

floating-point from ymm1 to ymm2/mem.

EVEX.128.0F.W0 10 /r

C

V/V

AVX512VL

Move unaligned packed single precision

VMOVUPS xmm1 {k1}{z}, xmm2/m128

AVX512F

floating-point values from xmm2/m128 to

xmm1 using writemask k1.

EVEX.256.0F.W0 10 /r

C

V/V

AVX512VL

Move unaligned packed single precision

VMOVUPS ymm1 {k1}{z}, ymm2/m256

AVX512F

floating-point values from ymm2/m256 to

ymm1 using writemask k1.

EVEX.512.0F.W0 10 /r

C

V/V

AVX512F

Move unaligned packed single precision

VMOVUPS zmm1 {k1}{z}, zmm2/m512

floating-point values from zmm2/m512 to

zmm1 using writemask k1.

EVEX.128.0F.W0 11 /r

D

V/V

AVX512VL

Move unaligned packed single precision

VMOVUPS xmm2/m128 {k1}{z}, xmm1

AVX512F

floating-point values from xmm1 to

xmm2/m128 using writemask k1.

EVEX.256.0F.W0 11 /r

D

V/V

AVX512VL

Move unaligned packed single precision

VMOVUPS ymm2/m256 {k1}{z}, ymm1

AVX512F

floating-point values from ymm1 to

ymm2/m256 using writemask k1.

EVEX.512.0F.W0 11 /r

D

V/V

AVX512F

Move unaligned packed single precision

VMOVUPS zmm2/m512 {k1}{z}, zmm1

floating-point values from zmm1 to

zmm2/m512 using writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:r/m (w)

ModRM:reg (r)

N/A

N/A

C

Full Mem

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

D

Full Mem

ModRM:r/m (w)

ModRM:reg (r)

N/A

N/A

Description

Note: VEX.vvvv and EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

EVEX.512 encoded version:

Moves 512 bits of packed single precision floating-point values from the source operand (second operand) to the

destination operand (first operand). This instruction can be used to load a ZMM register from a 512-bit float32

memory location, to store the contents of a ZMM register into memory. The destination operand is updated

according to the writemask.

4-136

Vol. 2B

MOVUPS—Move Unaligned Packed Single Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

MOVZX—Move With Zero-Extend

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

0F B6 /r

MOVZX r16, r/m8

RM

Valid

Valid

Move byte to word with zero-extension.

0F B6 /r

MOVZX r32, r/m8

RM

Valid

Valid

Move byte to doubleword, zero-extension.

REX.W + 0F B6 /r

MOVZX r64, r/m8¹

RM

Valid

N.E.

Move byte to quadword, zero-extension.

0F B7 /r

MOVZX r32, r/m16

RM

Valid

Valid

Move word to doubleword, zero-extension.

REX.W + 0F B7 /r

MOVZX r64, r/m16

RM

Valid

N.E.

Move word to quadword, zero-extension.

NOTES:

1. In 64-bit mode, r/m8 can not be encoded to access the following byte registers if the REX prefix is used: AH, BH, CH, DH.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RM

ModRM:reg (w)

ModRM:r/m (r)

N/A

N/A

Description

Copies the contents of the source operand (register or memory location) to the destination operand (register) and

zero extends the value. The size of the converted value depends on the operand-size attribute.

In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to addi-

tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bit operands. See the summary chart

at the beginning of this section for encoding data and limits.

Operation

DEST := ZeroExtend(SRC);

Flags Affected

None.

Protected Mode Exceptions

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register contains a NULL segment selector.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

#GP

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS

If a memory operand effective address is outside the SS segment limit.

#UD

If the LOCK prefix is used.

4-140

Vol. 2B

MOVZX—Move With Zero-Extend

INSTRUCTION SET REFERENCE, M-U

MPSADBW—Compute Multiple Packed Sums of Absolute Difference

Opcode/

Op/

64/32-bit

CPUID

Description

Instruction

En

Mode

Feature

Flag

66 0F 3A 42 /r ib

RMI

V/V

SSE4_1

Sums absolute 8-bit integer difference of

adjacent groups of 4 byte integers in xmm1

MPSADBW xmm1, xmm2/m128, imm8

and xmm2/m128 and writes the results in

xmm1. Starting offsets within xmm1 and

xmm2/m128 are determined by imm8.

VEX.128.66.0F3A.WIG 42 /r ib

RVMI

V/V

AVX

Sums absolute 8-bit integer difference of

adjacent groups of 4 byte integers in xmm2

VMPSADBW xmm1, xmm2, xmm3/m128, imm8

and xmm3/m128 and writes the results in

xmm1. Starting offsets within xmm2 and

xmm3/m128 are determined by imm8.

VEX.256.66.0F3A.WIG 42 /r ib

RVMI

V/V

AVX2

Sums absolute 8-bit integer difference of

adjacent groups of 4 byte integers in xmm2

VMPSADBW ymm1, ymm2, ymm3/m256, imm8

and ymm3/m128 and writes the results in

ymm1. Starting offsets within ymm2 and

xmm3/m128 are determined by imm8.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RMI

ModRM:reg (r, w)

ModRM:r/m (r)

imm8

N/A

RVMI

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

(V)MPSADBW calculates packed word results of sum-absolute-difference (SAD) of unsigned bytes from two blocks

of 32-bit dword elements, using two select fields in the immediate byte to select the offsets of the two blocks within

the first source operand and the second operand. Packed SAD word results are calculated within each 128-bit lane.

Each SAD word result is calculated between a stationary block_2 (whose offset within the second source operand

is selected by a two bit select control, multiplied by 32 bits) and a sliding block_1 at consecutive byte-granular posi-

tion within the first source operand. The offset of the first 32-bit block of block_1 is selectable using a one bit select

control, multiplied by 32 bits.

128-bit Legacy SSE version: Imm8[1:0]*32 specifies the bit offset of block_2 within the second source operand.

Imm[2]*32 specifies the initial bit offset of the block_1 within the first source operand. The first source operand

and destination operand are the same. The first source and destination operands are XMM registers. The second

source operand is either an XMM register or a 128-bit memory location. Bits (MAXVL-1:128) of the corresponding

YMM destination register remain unchanged. Bits 7:3 of the immediate byte are ignored.

VEX.128 encoded version: Imm8[1:0]*32 specifies the bit offset of block_2 within the second source operand.

Imm[2]*32 specifies the initial bit offset of the block_1 within the first source operand. The first source and desti-

nation operands are XMM registers. The second source operand is either an XMM register or a 128-bit memory

location. Bits (127:128) of the corresponding YMM register are zeroed. Bits 7:3 of the immediate byte are ignored.

VEX.256 encoded version: The sum-absolute-difference (SAD) operation is repeated 8 times for MPSADW between

the same block_2 (fixed offset within the second source operand) and a variable block_1 (offset is shifted by 8 bits

for each SAD operation) in the first source operand. Each 16-bit result of eight SAD operations between block_2

and block_1 is written to the respective word in the lower 128 bits of the destination operand.

Additionally, VMPSADBW performs another eight SAD operations on block_4 of the second source operand and

block_3 of the first source operand. (Imm8[4:3]*32 + 128) specifies the bit offset of block_4 within the second

source operand. (Imm[5]*32+128) specifies the initial bit offset of the block_3 within the first source operand.

Each 16-bit result of eight SAD operations between block_4 and block_3 is written to the respective word in the

upper 128 bits of the destination operand.

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MPSADBW—Compute Multiple Packed Sums of Absolute Difference

INSTRUCTION SET REFERENCE, M-U

The first source operand is a YMM register. The second source register can be a YMM register or a 256-bit memory

location. The destination operand is a YMM register. Bits 7:6 of the immediate byte are ignored.

Note: If VMPSADBW is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will

cause an #UD exception.

Imm[4:3]*32+128

255

224

192

128

Src2

Abs. Diff.

Imm[5]*32+128

Src1

Sum

255

144

128

Destination

Imm[1:0]*32

127

96

64

0

Src2

Abs. Diff.

Imm[2]*32

Src1

Sum

127

16

0

Destination

Figure 4-5. 256-bit VMPSADBW Operation

MPSADBW—Compute Multiple Packed Sums of Absolute Difference

Vol. 2B

4-143

INSTRUCTION SET REFERENCE, M-U

MUL—Unsigned Multiply

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

F6 /4

MUL r/m8

M

Valid

Valid

Unsigned multiply (AX := AL ∗ r/m8).

REX + F6 /4

MUL r/m8¹

M

Valid

N.E.

Unsigned multiply (AX := AL ∗ r/m8).

F7 /4

MUL r/m16

M

Valid

Valid

Unsigned multiply (DX:AX := AX ∗ r/m16).

F7 /4

MUL r/m32

M

Valid

Valid

Unsigned multiply (EDX:EAX := EAX ∗ r/m32).

REX.W + F7 /4

MUL r/m64

M

Valid

N.E.

Unsigned multiply (RDX:RAX := RAX ∗ r/m64).

NOTES:

1. In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

M

ModRM:r/m (r)

N/A

N/A

N/A

Description

Performs an unsigned multiplication of the first operand (destination operand) and the second operand (source

operand) and stores the result in the destination operand. The destination operand is an implied operand located in

register AL, AX or EAX (depending on the size of the operand); the source operand is located in a general-purpose

register or a memory location. The action of this instruction and the location of the result depends on the opcode

and the operand size as shown in Table 4-9.

The result is stored in register AX, register pair DX:AX, or register pair EDX:EAX (depending on the operand size),

with the high-order bits of the product contained in register AH, DX, or EDX, respectively. If the high-order bits of

the product are 0, the CF and OF flags are cleared; otherwise, the flags are set.

In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to addi-

tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.

See the summary chart at the beginning of this section for encoding data and limits.

Table 4-9. MUL Results

Operand Size

Source 1

Source 2

Destination

Byte

AL

r/m8

AX

Word

AX

r/m16

DX:AX

Doubleword

EAX

r/m32

EDX:EAX

Quadword

RAX

r/m64

RDX:RAX

4-150

Vol. 2B

MUL—Unsigned Multiply

INSTRUCTION SET REFERENCE, M-U

MULPD—Multiply Packed Double Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

66 0F 59 /r

A

V/V

SSE2

Multiply packed double precision floating-point values

MULPD xmm1, xmm2/m128

in xmm2/m128 with xmm1 and store result in xmm1.

VEX.128.66.0F.WIG 59 /r

B

V/V

AVX

Multiply packed double precision floating-point values

VMULPD xmm1,xmm2, xmm3/m128

in xmm3/m128 with xmm2 and store result in xmm1.

VEX.256.66.0F.WIG 59 /r

B

V/V

AVX

Multiply packed double precision floating-point values

VMULPD ymm1, ymm2, ymm3/m256

in ymm3/m256 with ymm2 and store result in ymm1.

EVEX.128.66.0F.W1 59 /r

C

V/V

AVX512VL

Multiply packed double precision floating-point values

VMULPD xmm1 {k1}{z}, xmm2,

AVX512F

from xmm3/m128/m64bcst to xmm2 and store result

xmm3/m128/m64bcst

in xmm1.

EVEX.256.66.0F.W1 59 /r

C

V/V

AVX512VL

Multiply packed double precision floating-point values

VMULPD ymm1 {k1}{z}, ymm2,

AVX512F

from ymm3/m256/m64bcst to ymm2 and store result

ymm3/m256/m64bcst

in ymm1.

EVEX.512.66.0F.W1 59 /r

C

V/V

AVX512F

Multiply packed double precision floating-point values

VMULPD zmm1 {k1}{z}, zmm2,

in zmm3/m512/m64bcst with zmm2 and store result

zmm3/m512/m64bcst{er}

in zmm1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Multiply packed double precision floating-point values from the first source operand with corresponding values in

the second source operand, and stores the packed double precision floating-point results in the destination

operand.

EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second

source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector

broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally

updated with writemask k1.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM

register or a 256-bit memory location. The destination operand is a YMM register. Bits (MAXVL-1:256) of the corre-

sponding destination ZMM register are zeroed.

VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM

register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of

the destination YMM register destination are zeroed.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

ZMM register destination are unmodified.

4-152

Vol. 2B

MULPD—Multiply Packed Double Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

MULPS—Multiply Packed Single Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

NP 0F 59 /r

A

V/V

SSE

Multiply packed single precision floating-point values in

MULPS xmm1, xmm2/m128

xmm2/m128 with xmm1 and store result in xmm1.

VEX.128.0F.WIG 59 /r

B

V/V

AVX

Multiply packed single precision floating-point values in

VMULPS xmm1,xmm2, xmm3/m128

xmm3/m128 with xmm2 and store result in xmm1.

VEX.256.0F.WIG 59 /r

B

V/V

AVX

Multiply packed single precision floating-point values in

VMULPS ymm1, ymm2, ymm3/m256

ymm3/m256 with ymm2 and store result in ymm1.

EVEX.128.0F.W0 59 /r

C

V/V

AVX512VL

Multiply packed single precision floating-point values

VMULPS xmm1 {k1}{z}, xmm2,

AVX512F

from xmm3/m128/m32bcst to xmm2 and store result in

xmm3/m128/m32bcst

xmm1.

EVEX.256.0F.W0 59 /r

C

V/V

AVX512VL

Multiply packed single precision floating-point values

VMULPS ymm1 {k1}{z}, ymm2,

AVX512F

from ymm3/m256/m32bcst to ymm2 and store result in

ymm3/m256/m32bcst

ymm1.

EVEX.512.0F.W0 59 /r

C

V/V

AVX512F

Multiply packed single precision floating-point values in

VMULPS zmm1 {k1}{z}, zmm2,

zmm3/m512/m32bcst with zmm2 and store result in

zmm3/m512/m32bcst {er}

zmm1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Multiply the packed single precision floating-point values from the first source operand with the corresponding

values in the second source operand, and stores the packed double precision floating-point results in the destina-

tion operand.

EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second

source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector

broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally

updated with writemask k1.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM

register or a 256-bit memory location. The destination operand is a YMM register. Bits (MAXVL-1:256) of the corre-

sponding destination ZMM register are zeroed.

VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM

register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAXVL-1:128) of

the destination YMM register destination are zeroed.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

ZMM register destination are unmodified.

MULPS—Multiply Packed Single Precision Floating-Point Values

Vol. 2B

4-155

INSTRUCTION SET REFERENCE, M-U

MULSD—Multiply Scalar Double Precision Floating-Point Value

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

F2 0F 59 /r

A

V/V

SSE2

Multiply the low double precision floating-point value in

MULSD xmm1,xmm2/m64

xmm2/m64 by low double precision floating-point

value in xmm1.

VEX.LIG.F2.0F.WIG 59 /r

B

V/V

AVX

Multiply the low double precision floating-point value in

VMULSD xmm1,xmm2, xmm3/m64

xmm3/m64 by low double precision floating-point

value in xmm2.

EVEX.LLIG.F2.0F.W1 59 /r

C

V/V

AVX512F

Multiply the low double precision floating-point value in

VMULSD xmm1 {k1}{z}, xmm2,

xmm3/m64 by low double precision floating-point

xmm3/m64 {er}

value in xmm2.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Multiplies the low double precision floating-point value in the second source operand by the low double precision

floating-point value in the first source operand, and stores the double precision floating-point result in the destina-

tion operand. The second source operand can be an XMM register or a 64-bit memory location. The first source

operand and the destination operands are XMM registers.

128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL-

1:64) of the corresponding destination register remain unchanged.

VEX.128 and EVEX encoded version: The quadword at bits 127:64 of the destination operand is copied from the

same bits of the first source operand. Bits (MAXVL-1:128) of the destination register are zeroed.

EVEX encoded version: The low quadword element of the destination operand is updated according to the

writemask.

Software should ensure VMULSD is encoded with VEX.L=0. Encoding VMULSD with VEX.L=1 may encounter unpre-

dictable behavior across different processor generations.

4-158

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MULSD—Multiply Scalar Double Precision Floating-Point Value

INSTRUCTION SET REFERENCE, M-U

MULSS—Multiply Scalar Single Precision Floating-Point Values

Opcode/

Op /

64/32

CPUID

Description

Instruction

En

bit Mode

Feature

Support

Flag

F3 0F 59 /r

A

V/V

SSE

Multiply the low single precision floating-point value in

MULSS xmm1,xmm2/m32

xmm2/m32 by the low single precision floating-point

value in xmm1.

VEX.LIG.F3.0F.WIG 59 /r

B

V/V

AVX

Multiply the low single precision floating-point value in

VMULSS xmm1,xmm2, xmm3/m32

xmm3/m32 by the low single precision floating-point

value in xmm2.

EVEX.LLIG.F3.0F.W0 59 /r

C

V/V

AVX512F

Multiply the low single precision floating-point value in

VMULSS xmm1 {k1}{z}, xmm2,

xmm3/m32 by the low single precision floating-point

xmm3/m32 {er}

value in xmm2.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

A

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

N/A

B

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

C

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Multiplies the low single precision floating-point value from the second source operand by the low single precision

floating-point value in the first source operand, and stores the single precision floating-point result in the destina-

tion operand. The second source operand can be an XMM register or a 32-bit memory location. The first source

operand and the destination operands are XMM registers.

128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL-

1:32) of the corresponding YMM destination register remain unchanged.

VEX.128 and EVEX encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The three

high-order doublewords of the destination operand are copied from the first source operand. Bits (MAXVL-1:128)

of the destination register are zeroed.

EVEX encoded version: The low doubleword element of the destination operand is updated according to the

writemask.

Software should ensure VMULSS is encoded with VEX.L=0. Encoding VMULSS with VEX.L=1 may encounter unpre-

dictable behavior across different processor generations.

4-160

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MULSS—Multiply Scalar Single Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

MULX—Unsigned Multiply Without Affecting Flags

Opcode/

Op/

64/32-

CPUID

Description

Instruction

En

bit

Feature

Mode

Flag

VEX.LZ.F2.0F38.W0 F6 /r

RVM

V/V

BMI2

Unsigned multiply of r/m32 with EDX without affecting arithmetic

MULX r32a, r32b, r/m32

flags.

VEX.LZ.F2.0F38.W1 F6 /r

RVM

V/N.E.

BMI2

Unsigned multiply of r/m64 with RDX without affecting arithmetic

MULX r64a, r64b, r/m64

flags.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RDX/EDX is implied 64/32 bits

RVM

ModRM:reg (w)

VEX.vvvv (w)

ModRM:r/m (r)

source

Description

Performs an unsigned multiplication of the implicit source operand (EDX/RDX) and the specified source operand

(the third operand) and stores the low half of the result in the second destination (second operand), the high half

of the result in the first destination operand (first operand), without reading or writing the arithmetic flags. This

enables efficient programming where the software can interleave add with carry operations and multiplications.

If the first and second operand are identical, it will contain the high half of the multiplication result.

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in

64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt

to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation

// DEST1: ModRM:reg

// DEST2: VEX.vvvv

IF (OperandSize = 32)

SRC1 := EDX;

DEST2 := (SRC1*SRC2)[31:0];

DEST1 := (SRC1*SRC2)[63:32];

ELSE IF (OperandSize = 64)

SRC1 := RDX;

DEST2 := (SRC1*SRC2)[63:0];

DEST1 := (SRC1*SRC2)[127:64];

FI

Flags Affected

None

Intel C/C++ Compiler Intrinsic Equivalent

Auto-generated from high-level language when possible.

unsigned int mulx_u32(unsigned int a, unsigned int b, unsigned int * hi);

unsigned __int64 mulx_u64(unsigned __int64 a, unsigned __int64 b, unsigned __int64 * hi);

SIMD Floating-Point Exceptions

None

4-162

Vol. 2B

MULX—Unsigned Multiply Without Affecting Flags

INSTRUCTION SET REFERENCE, M-U

MWAIT—Monitor Wait

Opcode

Instruction

Op/

64-Bit

Compat/

Description

En

Mode

Leg Mode

0F 01 C9

MWAIT

ZO

Valid

Valid

A hint that allows the processor to stop

instruction execution and enter an

implementation-dependent optimized state

until occurrence of a class of events.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ZO

N/A

N/A

N/A

N/A

Description

MWAIT instruction provides hints to allow the processor to enter an implementation-dependent optimized state.

There are two principal targeted usages: address-range monitor and advanced power management. Both usages

of MWAIT require the use of the MONITOR instruction.

CPUID.01H:ECX.MONITOR[bit 3] indicates the availability of MONITOR and MWAIT in the processor. When set,

MWAIT may be executed only at privilege level 0 (use at any other privilege level results in an invalid-opcode

exception). The operating system or system BIOS may disable this instruction by using the IA32_MISC_ENABLE

MSR; disabling MWAIT clears the CPUID feature flag and causes execution to generate an invalid-opcode excep-

tion.

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

ECX specifies optional extensions for the MWAIT instruction. EAX may contain hints such as the preferred optimized

state the processor should enter. The first processors to implement MWAIT supported only the zero value for EAX

and ECX. Later processors allowed setting ECX[0] to enable masked interrupts as break events for MWAIT (see

below). Software can use the CPUID instruction to determine the extensions and hints supported by the processor.

MWAIT for Address Range Monitoring

For address-range monitoring, the MWAIT instruction operates with the MONITOR instruction. The two instructions

allow the definition of an address at which to wait (MONITOR) and a implementation-dependent-optimized opera-

tion to commence at the wait address (MWAIT). The execution of MWAIT is a hint to the processor that it can enter

an implementation-dependent-optimized state while waiting for an event or a store operation to the address range

armed by MONITOR.

The following cause the processor to exit the implementation-dependent-optimized state: a store to the address

range armed by the MONITOR instruction, an NMI or SMI, a debug exception, a machine check exception, the

BINIT# signal, the INIT# signal, and the RESET# signal. Other implementation-dependent events may also cause

the processor to exit the implementation-dependent-optimized state.

In addition, an external interrupt causes the processor to exit the implementation-dependent-optimized state

either (1) if the interrupt would be delivered to software (e.g., as it would be if HLT had been executed instead of

MWAIT); or (2) if ECX[0] = 1. Software can execute MWAIT with ECX[0] = 1 only if CPUID.05H:ECX[bit 1] = 1.

(Implementation-specific conditions may result in an interrupt causing the processor to exit the implementation-

dependent-optimized state even if interrupts are masked and ECX[0] = 0.)

Following exit from the implementation-dependent-optimized state, control passes to the instruction following the

MWAIT instruction. A pending interrupt that is not masked (including an NMI or an SMI) may be delivered before

execution of that instruction. Unlike the HLT instruction, the MWAIT instruction does not support a restart at the

MWAIT instruction following the handling of an SMI.

If the preceding MONITOR instruction did not successfully arm an address range or if the MONITOR instruction has

not been executed prior to executing MWAIT, then the processor will not enter the implementation-dependent-opti-

mized state. Execution will resume at the instruction following the MWAIT.

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MWAIT—Monitor Wait

INSTRUCTION SET REFERENCE, M-U

MWAIT for Power Management

MWAIT accepts a hint and optional extension to the processor that it can enter a specified target C state while

waiting for an event or a store operation to the address range armed by MONITOR. Support for MWAIT extensions

for power management is indicated by CPUID.05H:ECX[bit 0] reporting 1.

EAX and ECX are used to communicate the additional information to the MWAIT instruction, such as the kind of

optimized state the processor should enter. ECX specifies optional extensions for the MWAIT instruction. EAX may

contain hints such as the preferred optimized state the processor should enter. Implementation-specific conditions

may cause a processor to ignore the hint and enter a different optimized state. Future processor implementations

may implement several optimized “waiting” states and will select among those states based on the hint argument.

Table 4-10 describes the meaning of ECX and EAX registers for MWAIT extensions.

Table 4-10. MWAIT Extension Register (ECX)

Bits

Description

0

Treat interrupts as break events even if masked (e.g., even if EFLAGS.IF=0). May be set only if

CPUID.05H:ECX[bit 1] = 1.

31: 1

Reserved

Table 4-11. MWAIT Hints Register (EAX)

Bits

Description

3 : 0

Sub C-state within a C-state, indicated by bits [7:4]

7 : 4

Target C-state*

Value of 0 means C1; 1 means C2 and so on

Value of 01111B means C0

Note: Target C states for MWAIT extensions are processor-specific C-states, not ACPI C-states

31: 8

Reserved

Note that if MWAIT is used to enter any of the C-states that are numerically higher than C1, a store to the address

range armed by the MONITOR instruction will cause the processor to exit MWAIT only if the store was originated by

other processor agents. A store from non-processor agent might not cause the processor to exit MWAIT in such

cases.

For additional details of MWAIT extensions, see Chapter 15, “Power and Thermal Management,” of Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A.

Operation

(* MWAIT takes the argument in EAX as a hint extension and is architected to take the argument in ECX as an instruction extension

MWAIT EAX, ECX *)

{

WHILE ( (“Monitor Hardware is in armed state”)) {

implementation_dependent_optimized_state(EAX, ECX); }

Set the state of Monitor Hardware as triggered;

}

Intel C/C++ Compiler Intrinsic Equivalent

MWAIT:

void _mm_mwait(unsigned extensions, unsigned hints)

MWAIT—Monitor Wait

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