Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)

Bit Description

Scope

MSR_C4_PMON_EVNTSEL0

Uncore C-box 4 Perfmon Event Select for C-box 4 Counter 0

Package

MSR_C4_PMON_EVNTSEL1

Uncore C-box 4 Perfmon Event Select for C-box 4 Counter 1

Package

MSR_C4_PMON_EVNTSEL2

Uncore C-box 4 Perfmon Event Select for C-box 4 Counter 2

Package

MSR_C4_PMON_EVNTSEL3

Uncore C-box 4 Perfmon Event Select for C-box 4 Counter 3

Package

MSR_C4_PMON_BOX_FILTER

Uncore C-box 4 Perfmon Box Wide Filter

Package

MSR_C4_PMON_CTR0

Uncore C-box 4 Perfmon Counter 0

Package

MSR_C4_PMON_CTR1

Uncore C-box 4 Perfmon Counter 1

Package

MSR_C4_PMON_CTR2

Uncore C-box 4 Perfmon Counter 2

Package

MSR_C4_PMON_CTR3

Uncore C-box 4 Perfmon Counter 3

Package

MSR_C5_PMON_BOX_CTL

Uncore C-box 5 Perfmon Local Box Wide Control

Package

MSR_C5_PMON_EVNTSEL0

Uncore C-box 5 Perfmon Event Select for C-box 5 Counter 0

Package

MSR_C5_PMON_EVNTSEL1

Uncore C-box 5 Perfmon Event Select for C-box 5 Counter 1

Package

MSR_C5_PMON_EVNTSEL2

Uncore C-box 5 Perfmon Event Select for C-box 5 Counter 2

Package

MSR_C5_PMON_EVNTSEL3

Uncore C-box 5 Perfmon Event Select for C-box 5 Counter 3

Package

MSR_C5_PMON_BOX_FILTER

Uncore C-box 5 Perfmon Box Wide Filter

Package

MSR_C5_PMON_CTR0

Uncore C-box 5 Perfmon Counter 0

Package

MSR_C5_PMON_CTR1

Uncore C-box 5 Perfmon Counter 1

Package

MSR_C5_PMON_CTR2

Uncore C-box 5 Perfmon Counter 2

Package

MSR_C5_PMON_CTR3

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)

Bit Description

Scope

Uncore C-box 5 Perfmon Counter 3

Package

MSR_C6_PMON_BOX_CTL

Uncore C-box 6 Perfmon Local Box Wide Control

Package

MSR_C6_PMON_EVNTSEL0

Uncore C-box 6 Perfmon Event Select for C-box 6 Counter 0

Package

MSR_C6_PMON_EVNTSEL1

Uncore C-box 6 Perfmon Event Select for C-box 6 Counter 1

Package

MSR_C6_PMON_EVNTSEL2

Uncore C-box 6 Perfmon Event Select for C-box 6 Counter 2

Package

MSR_C6_PMON_EVNTSEL3

Uncore C-box 6 Perfmon Event Select for C-box 6 Counter 3

Package

MSR_C6_PMON_BOX_FILTER

Uncore C-box 6 Perfmon Box Wide Filter

Package

MSR_C6_PMON_CTR0

Uncore C-box 6 Perfmon Counter 0

Package

MSR_C6_PMON_CTR1

Uncore C-box 6 Perfmon Counter 1

Package

MSR_C6_PMON_CTR2

Uncore C-box 6 Perfmon Counter 2

Package

MSR_C6_PMON_CTR3

Uncore C-box 6 Perfmon Counter 3

Package

MSR_C7_PMON_BOX_CTL

Uncore C-box 7 Perfmon Local Box Wide Control

Package

MSR_C7_PMON_EVNTSEL0

Uncore C-box 7 Perfmon Event Select for C-box 7 Counter 0

Package

MSR_C7_PMON_EVNTSEL1

Uncore C-box 7 Perfmon Event Select for C-box 7 Counter 1

Package

MSR_C7_PMON_EVNTSEL2

Uncore C-box 7 Perfmon Event Select for C-box 7 Counter 2

Package

MSR_C7_PMON_EVNTSEL3

Uncore C-box 7 Perfmon Event Select for C-box 7 Counter 3

Package

MSR_C7_PMON_BOX_FILTER

Uncore C-box 7 Perfmon Box Wide Filter

Package

MSR_C7_PMON_CTR0

Uncore C-box 7 Perfmon Counter 0

Package

MSR_C7_PMON_CTR1

Uncore C-box 7 Perfmon Counter 1

Package

2-234 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)

Bit Description

Scope

MSR_C7_PMON_CTR2

Uncore C-box 7 Perfmon Counter 2

Package

MSR_C7_PMON_CTR3

Uncore C-box 7 Perfmon Counter 3

Package

2.12

MSRS IN THE 3RD GENERATION INTEL® CORE™ PROCESSOR FAMILY BASED

ON IVY BRIDGE MICROARCHITECTURE

The 3rd generation Intel^® Core™ processor family and the Intel^® Xeon^® processor E3-1200v2 product family

based on Ivy Bridge microarchitecture support the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-22, and

Table 2-25. These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_3AH.

Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge

Microarchitecture

Bit Description

Scope

MSR_PLATFORM_INFO

Platform Information

Package

Contains power management and other model specific features enumeration. See http://biosbits.org.

7:0

Reserved.

15:8

Maximum Non-Turbo Ratio (R/O)

Package

This is the ratio of the frequency that invariant TSC runs at. Frequency =

ratio * 100 MHz.

27:16

Reserved.

Programmable Ratio Limit for Turbo Mode (R/O)

Package

When set to 1, indicates that Programmable Ratio Limit for Turbo mode is

enabled. When set to 0, indicates Programmable Ratio Limit for Turbo

mode is disabled.

Programmable TDP Limit for Turbo Mode (R/O)

Package

When set to 1, indicates that TDP Limit for Turbo mode is programmable.

When set to 0, indicates that TDP Limit for Turbo mode is not

programmable.

31:30

Reserved.

Low Power Mode Support (LPM) (R/O)

Package

When set to 1, indicates that LPM is supported. When set to 0, indicates

LPM is not supported.

34:33

Number of ConfigTDP Levels (R/O)

Package

00: Only Base TDP level available.

01: One additional TDP level available.

02: Two additional TDP level available.

03: Reserved

39:35

Reserved.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge

Microarchitecture (Contd.)

Bit Description

Scope

47:40

Maximum Efficiency Ratio (R/O)

Package

This is the minimum ratio (maximum efficiency) that the processor can

operate, in units of 100MHz.

55:48

Minimum Operating Ratio (R/O)

Package

Contains the minimum supported operating ratio in units of 100 MHz.

63:56

Reserved.

MSR_PKG_CST_CONFIG_CONTROL

C-State Configuration Control (R/W)

Core

Note: C-state values are processor specific C-state code names, unrelated

to MWAIT extension C-state parameters or ACPI C-States.

See http://biosbits.org.

2:0

Package C-State Limit (R/W)

Specifies the lowest processor-specific C-state code name (consuming the

least power) for the package. The default is set as factory-configured

package C-state limit.

The following C-state code name encodings are supported:

000b: C0/C1 (no package C-sate support)

001b: C2

010b: C6 no retention

011b: C6 retention

100b: C7

101b: C7s

111: No package C-state limit.

Note: This field cannot be used to limit package C-state to C3.

9:3

Reserved.

I/O MWAIT Redirection Enable (R/W)

When set, will map IO_read instructions sent to IO register specified by

MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.

14:11

Reserved.

CFG Lock (R/WO)

When set, locks bits 15:0 of this register until next reset.

24:16

Reserved

C3 State Auto Demotion Enable (R/W)

When set, the processor will conditionally demote C6/C7 requests to C3

based on uncore auto-demote information.

C1 State Auto Demotion Enable (R/W)

When set, the processor will conditionally demote C3/C6/C7 requests to

C1 based on uncore auto-demote information.

Enable C3 Undemotion (R/W)

When set, enables undemotion from demoted C3.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge

Microarchitecture (Contd.)

Bit Description

Scope

Enable C1 Undemotion (R/W)

When set, enables undemotion from demoted C1.

63:29

Reserved.

MSR_PP0_ENERGY_STATUS

PP0 Energy Status (R/O)

Package

See Section 15.10.4, “PP0/PP1 RAPL Domains.”

MSR_CONFIG_TDP_NOMINAL

Base TDP Ratio (R/O)

Package

7:0

Config_TDP_Base

Base TDP level ratio to be used for this specific processor (in units of 100

MHz).

63:8

Reserved.

MSR_CONFIG_TDP_LEVEL1

ConfigTDP Level 1 ratio and power level (R/O)

Package

14:0

PKG_TDP_LVL1

Power setting for ConfigTDP Level 1.

Reserved.

23:16

Config_TDP_LVL1_Ratio

ConfigTDP level 1 ratio to be used for this specific processor.

31:24

Reserved.

46:32

PKG_MAX_PWR_LVL1

Max Power setting allowed for ConfigTDP Level 1.

Reserved.

62:48

PKG_MIN_PWR_LVL1

MIN Power setting allowed for ConfigTDP Level 1.

Reserved.

MSR_CONFIG_TDP_LEVEL2

ConfigTDP Level 2 ratio and power level (R/O)

Package

14:0

PKG_TDP_LVL2

Power setting for ConfigTDP Level 2.

Reserved.

23:16

Config_TDP_LVL2_Ratio

ConfigTDP level 2 ratio to be used for this specific processor.

31:24

Reserved.

46:32

PKG_MAX_PWR_LVL2

Max Power setting allowed for ConfigTDP Level 2.

Reserved.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge

Microarchitecture (Contd.)

Bit Description

Scope

62:48

PKG_MIN_PWR_LVL2

MIN Power setting allowed for ConfigTDP Level 2.

Reserved.

MSR_CONFIG_TDP_CONTROL

ConfigTDP Control (R/W)

Package

1:0

TDP_LEVEL (RW/L)

System BIOS can program this field.

30:2

Reserved.

Config_TDP_Lock (RW/L)

When this bit is set, the content of this register is locked until a reset.

63:32

Reserved.

MSR_TURBO_ACTIVATION_RATIO

ConfigTDP Control (R/W)

Package

7:0

MAX_NON_TURBO_RATIO (RW/L)

System BIOS can program this field.

30:8

Reserved.

TURBO_ACTIVATION_RATIO_Lock (RW/L)

When this bit is set, the content of this register is locked until a reset.

63:32

Reserved.

See Table 2-20, Table 2-21, and Table 2-22 for other MSR definitions applicable to processors with a CPUID Signature

DisplayFamily_DisplayModel value of 06_3AH.

2.12.1 MSRs in the Intel® Xeon® Processor E5 v2 Product Family Based on Ivy Bridge-E

Microarchitecture

Table 2-26 lists model-specific registers (MSRs) that are specific to the Intel^® Xeon^® Processor E5 v2 Product

Family (based on Ivy Bridge-E microarchitecture). These processors have a CPUID Signature

DisplayFamily_DisplayModel value of 06_3EH; see Table 2-1. These processors supports the MSR interfaces listed

in Table 2-20 and Table 2-26.

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Bit Description

Scope

IA32_PPIN_CTL (MSR_PPIN_CTL)

Protected Processor Inventory Number Enable Control (R/W)

Package

LockOut (R/WO)

See Table 2-2.

Enable_PPIN (R/W)

See Table 2-2.

63:2

Reserved.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Bit Description

Scope

IA32_PPIN (MSR_PPIN)

Protected Processor Inventory Number (R/O)

Package

63:0

Protected Processor Inventory Number (R/O)

See Table 2-2.

MSR_PLATFORM_INFO

Platform Information

Package

Contains power management and other model specific features enumeration. See http://biosbits.org.

7:0

Reserved.

15:8

Maximum Non-Turbo Ratio (R/O)

Package

This is the ratio of the frequency that invariant TSC runs at. Frequency =

ratio * 100 MHz.

22:16

Reserved.

PPIN_CAP (R/O)

Package

When set to 1, indicates that Protected Processor Inventory Number (PPIN)

capability can be enabled for a privileged system inventory agent to read

PPIN from MSR_PPIN.

When set to 0, PPIN capability is not supported. An attempt to access

MSR_PPIN_CTL or MSR_PPIN will cause #GP.

27:24

Reserved.

Programmable Ratio Limit for Turbo Mode (R/O)

Package

When set to 1, indicates that Programmable Ratio Limit for Turbo mode is

enabled. When set to 0, indicates Programmable Ratio Limit for Turbo mode

is disabled.

Programmable TDP Limit for Turbo Mode (R/O)

Package

When set to 1, indicates that TDP Limit for Turbo mode is programmable.

When set to 0, indicates TDP Limit for Turbo mode is not programmable.

Programmable TJ OFFSET (R/O)

Package

When set to 1, indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid

and writable to specify a temperature offset.

39:31

Reserved.

47:40

Maximum Efficiency Ratio (R/O)

Package

This is the minimum ratio (maximum efficiency) that the processor can

operate, in units of 100MHz.

63:48

Reserved.

MSR_PKG_CST_CONFIG_CONTROL

C-State Configuration Control (R/W)

Core

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

ACPI C-states. See http://biosbits.org.

Vol. 4

2-239

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Bit Description

Scope

2:0

Package C-State Limit (R/W)

Specifies the lowest processor-specific C-state code name (consuming the

least power) for the package. The default is set as factory-configured

package C-state limit.

The following C-state code name encodings are supported:

000b: C0/C1 (no package C-sate support)

001b: C2

010b: C6 no retention

011b: C6 retention

100b: C7

101b: C7s

111: No package C-state limit.

Note: This field cannot be used to limit package C-state to C3.

9:3

Reserved.

I/O MWAIT Redirection Enable (R/W)

When set, will map IO_read instructions sent to IO register specified by

MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.

14:11

Reserved.

CFG Lock (R/WO)

When set, locks bits 15:0 of this register until next reset.

63:16

Reserved.

IA32_MCG_CAP

Global Machine Check Capability (R/O)

Thread

7:0

Count

MCG_CTL_P

MCG_EXT_P

MCP_CMCI_P

MCG_TES_P

15:12

Reserved.

23:16

MCG_EXT_CNT

MCG_SER_P

Reserved.

MCG_ELOG_P

63:27

Reserved.

MSR_ERROR_CONTROL

MC Bank Error Configuration (R/W)

Package

Reserved.

MemError Log Enable (R/W)

When set, enables IMC status bank to log additional info in bits 36:32.

63:2

Reserved.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Bit Description

Scope

MSR_TEMPERATURE_TARGET

Temperature Target

Package

15:0

Reserved.

23:16

Temperature Target (R/O)

The minimum temperature at which PROCHOT# will be asserted. The value

is degrees C.

27:24

TCC Activation Offset (R/W)

Specifies a temperature offset in degrees C from the temperature target

(bits 23:16). PROCHOT# will assert at the offset target temperature. Write

is permitted only if MSR_PLATFORM_INFO.[30] is set.

63:28

Reserved.

MSR_TURBO_RATIO_LIMIT1

Maximum Ratio Limit of Turbo Mode

Package

R/O if MSR_PLATFORM_INFO.[28] = 0. R/W if MSR_PLATFORM_INFO.[28] = 1.

7:0

Maximum Ratio Limit for 9C

Package

Maximum turbo ratio limit of 9 core active.

15:8

Maximum Ratio Limit for 10C

Package

Maximum turbo ratio limit of 10 core active.

23:16

Maximum Ratio Limit for 11C

Package

Maximum turbo ratio limit of 11 core active.

31:24

Maximum Ratio Limit for 12C

Package

Maximum turbo ratio limit of 12 core active.

63:32

Reserved.

IA32_MC5_CTL2

See Table 2-2.

Package

IA32_MC6_CTL2

See Table 2-2.

Package

IA32_MC7_CTL2

See Table 2-2.

Package

IA32_MC8_CTL2

See Table 2-2.

Package

IA32_MC9_CTL2

See Table 2-2.

Package

IA32_MC10_CTL2

See Table 2-2.

Package

IA32_MC11_CTL2

See Table 2-2.

Package

IA32_MC12_CTL2

See Table 2-2.

Package

Vol. 4

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Bit Description

Scope

IA32_MC13_CTL2

See Table 2-2.

Package

IA32_MC14_CTL2

See Table 2-2.

Package

IA32_MC15_CTL2

See Table 2-2.

Package

IA32_MC16_CTL2

See Table 2-2.

Package

IA32_MC17_CTL2

See Table 2-2.

Package

IA32_MC18_CTL2

See Table 2-2.

Package

IA32_MC19_CTL2

See Table 2-2.

Package

IA32_MC20_CTL2

See Table 2-2.

Package

IA32_MC21_CTL2

See Table 2-2.

Package

IA32_MC22_CTL2

See Table 2-2.

Package

IA32_MC23_CTL2IA32_MC23_CTL2

See Table 2-2.

Package

IA32_MC24_CTL2

See Table 2-2.

Package

IA32_MC25_CTL2

See Table 2-2.

Package

IA32_MC26_CTL2

See Table 2-2.

Package

IA32_MC27_CTL2

See Table 2-2.

Package

IA32_MC28_CTL2

See Table 2-2.

Package

IA32_MC5_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC5 reports MC errors from the Intel QPI module.

IA32_MC5_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC5 reports MC errors from the Intel QPI module.

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Bit Description

Scope

IA32_MC5_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC5 reports MC errors from the Intel QPI module.

IA32_MC5_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC5 reports MC errors from the Intel QPI module.

IA32_MC6_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC6 reports MC errors from the integrated I/O module.

IA32_MC6_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC6 reports MC errors from the integrated I/O module.

IA32_MC6_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC6 reports MC errors from the integrated I/O module.

IA32_MC6_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC6 reports MC errors from the integrated I/O module.

IA32_MC7_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC7 and MC 8 report MC errors from the two home agents.

IA32_MC7_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC7 and MC 8 report MC errors from the two home agents.

IA32_MC7_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC7 and MC 8 report MC errors from the two home agents.

IA32_MC7_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC7 and MC 8 report MC errors from the two home agents.

IA32_MC8_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC7 and MC 8 report MC errors from the two home agents.

IA32_MC8_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC7 and MC 8 report MC errors from the two home agents.

IA32_MC8_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC7 and MC 8 report MC errors from the two home agents.

Vol. 4

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Bit Description

Scope

IA32_MC8_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC7 and MC 8 report MC errors from the two home agents.

IA32_MC9_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC9_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC9_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC9_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC10_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC10_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC10_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC10_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC11_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

Bank MC11 reports MC errors from a specific channel of the integrated memory controller.

IA32_MC11_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

Bank MC11 reports MC errors from a specific channel of the integrated memory controller.

IA32_MC11_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

Bank MC11 reports MC errors from a specific channel of the integrated memory controller.

IA32_MC11_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

Bank MC11 reports MC errors from a specific channel of the integrated memory controller.

2-244 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Bit Description

Scope

IA32_MC12_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC12_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC12_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC12_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC13_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC13_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC13_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC13_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC14_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC14_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC14_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC14_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC15_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

Vol. 4

2-245

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Bit Description

Scope

IA32_MC15_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC15_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC15_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC16_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC16_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC16_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC16_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.

IA32_MC17_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC17 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC17_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC17 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC17_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC17 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC17_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC17 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC18_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC18 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC18_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC18 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

2-246 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Bit Description

Scope

IA32_MC18_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC18 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC18_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC18 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC19_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC19 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC19_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC19 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC19_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC19 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC19_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC19 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC20_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

Bank MC20 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC20_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

Bank MC20 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC20_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

Bank MC20 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC20_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

Bank MC20 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC21_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC21 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC21_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC21 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC21_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC21 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

Vol. 4

2-247

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Bit Description

Scope

IA32_MC21_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC21 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC22_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC22 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC22_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC22 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC22_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC22 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC22_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC22 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC23_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC23 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC23_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC23 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC23_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC23 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC23_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC23 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC24_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC24 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC24_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC24 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC24_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC24 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC24_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC24 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

2-248 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Bit Description

Scope

IA32_MC25_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC25 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC25_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC25 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC25_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC25 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC2MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC25 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC26_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC26 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC26_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC26 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC26_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC26 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC26_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC26 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC27_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC27 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC27_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC27 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC27_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC27 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC27_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC27 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC28_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC28 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

Vol. 4

2-249

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)

Bit Description

Scope

IA32_MC28_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC28 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC28_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC28 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC28_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC28 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

MSR_PKG_PERF_STATUS

Package RAPL Perf Status (R/O)

Package

MSR_DRAM_POWER_LIMIT

DRAM RAPL Power Limit Control (R/W)

Package

See Section 15.10.5, “DRAM RAPL Domain.”

MSR_DRAM_ENERGY_STATUS

DRAM Energy Status (R/O)

Package

See Section 15.10.5, “DRAM RAPL Domain.”

MSR_DRAM_PERF_STATUS

DRAM Performance Throttling Status (R/O)

Package

See Section 15.10.5, “DRAM RAPL Domain.”

MSR_DRAM_POWER_INFO

DRAM RAPL Parameters (R/W)

Package

See Section 15.10.5, “DRAM RAPL Domain.”

MSR_PP0_ENERGY_STATUS

PP0 Energy Status (R/O)

Package

See Section 15.10.4, “PP0/PP1 RAPL Domains.”

See Table 2-20, for other MSR definitions applicable to Intel Xeon processor E5 v2 with a CPUID Signature

DisplayFamily_DisplayModel value of 06_3EH.

2.12.2 Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family

The Intel^® Xeon^® processor E7 v2 family (based on Ivy Bridge-E microarchitecture) with a CPUID Signature

DisplayFamily_DisplayModel value of 06_3EH supports the MSR interfaces listed in Table 2-20, Table 2-26, and

Table 2-27.

Table 2-27. Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_3EH

Bit Description

Scope

IA32_FEATURE_CONTROL

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-27. Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_3EH (Contd.)

Bit Description

Scope

Control Features in Intel 64 Processor (R/W)

Thread

See Table 2-2.

Lock (R/WL)

Enable VMX Inside SMX Operation (R/WL)

Enable VMX Outside SMX Operation (R/WL)

14:8

SENTER Local Functions Enables (R/WL)

SENTER Global Functions Enable (R/WL)

63:16

Reserved.

IA32_MCG_CAP

Global Machine Check Capability (R/O)

Thread

7:0

Count

MCG_CTL_P

MCG_EXT_P

MCP_CMCI_P

MCG_TES_P

15:12

Reserved.

23:16

MCG_EXT_CNT

MCG_SER_P

63:25

Reserved.

IA32_MCG_STATUS

Global Machine Check Status (R/W)

Thread

RIPV

EIPV

MCIP

LMCE Signaled

63:4

Reserved.

MSR_TURBO_RATIO_LIMIT1

Maximum Ratio Limit of Turbo Mode

Package

R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.

7:0

Maximum Ratio Limit for 9C

Package

Maximum turbo ratio limit of 9 core active.

15:8

Maximum Ratio Limit for 10C

Package

Maximum turbo ratio limit of 10core active.

23:16

Maximum Ratio Limit for 11C

Package

Maximum turbo ratio limit of 11 core active.

31:24

Maximum Ratio Limit for 12C

Package

Maximum turbo ratio limit of 12 core active.

Vol. 4

2-251

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-27. Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_3EH (Contd.)

Bit Description

Scope

39:32

Maximum Ratio Limit for 13C

Package

Maximum turbo ratio limit of 13 core active.

47:40

Maximum Ratio Limit for 14C

Package

Maximum turbo ratio limit of 14 core active.

55:48

Maximum Ratio Limit for 15C

Package

Maximum turbo ratio limit of 15 core active.

62:56

Reserved.

Semaphore for Turbo Ratio Limit Configuration

Package

If 1, the processor uses override configuration¹ specified in

MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1.

If 0, the processor uses factory-set configuration (Default).

IA32_MC29_CTL2

See Table 2-2.

Package

IA32_MC30_CTL2

See Table 2-2.

Package

IA32_MC31_CTL2

See Table 2-2.

Package

IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)

See Section 20.3.1.1.1, “Processor Event Based Sampling (PEBS).”

Thread

n:0

Enable PEBS on IA32_PMCx. (R/W)

31:n+1

Reserved.

32+m:32

Enable Load Latency on IA32_PMCx. (R/W)

63:33+m

Reserved.

IA32_MC6_MISC

Misc MAC Information of Integrated I/O (R/O)

Package

See Section 16.3.2.4.

5:0

Recoverable Address LSB

8:6

Address Mode

15:9

Reserved.

31:16

PCI Express Requestor ID

39:32

PCI Express Segment Number

63:32

Reserved.

IA32_MC29_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC29 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC29_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC29 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

2-252 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-27. Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature

DisplayFamily_DisplayModel Value of 06_3EH (Contd.)

Bit Description

Scope

IA32_MC29_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC29 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC29_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC29 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC30_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC30 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC30_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC30 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC30_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC30 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC30_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC30 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC31_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC31 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC31_STATUS

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC31 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC31_ADDR

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC31 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

IA32_MC31_MISC

See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

Bank MC31 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.

See Table 2-20, Table 2-26 for other MSR definitions applicable to Intel Xeon processor E7 v2 with a CPUID Signature

DisplayFamily_DisplayModel value of 06_3AH.

NOTES:

1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the

factory-set configuration is dependent on features specific to the processor and the platform.

2.12.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families

Intel Xeon Processor E5 v2 and E7 v2 families are based on the Ivy Bridge-E microarchitecture. The MSR-based

uncore PMU interfaces are listed in Table 2-24 and Table 2-28. For complete detail of the uncore PMU, refer to Intel

Vol. 4

2-253

MODEL-SPECIFIC REGISTERS (MSRS)

Xeon Processor E5 v2 Product Family Uncore Performance Monitoring Guide. These processors have a CPUID

Signature DisplayFamily_DisplayModel value of 06_3EH.

Table 2-28. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families

Bit Description

Scope

MSR_PMON_GLOBAL_CTL

Uncore Perfmon Per-Socket Global Control

Package

MSR_PMON_GLOBAL_STATUS

Uncore Perfmon Per-Socket Global Status

Package

MSR_PMON_GLOBAL_CONFIG

Uncore Perfmon Per-Socket Global Configuration

Package

MSR_U_PMON_BOX_STATUS

Uncore U-box Perfmon U-Box Wide Status

Package

MSR_PCU_PMON_BOX_STATUS

Uncore PCU Perfmon Box Wide Status

Package

MSR_C0_PMON_BOX_FILTER1

Uncore C-Box 0 Perfmon Box Wide Filter1

Package

MSR_C1_PMON_BOX_FILTER1

Uncore C-Box 1 Perfmon Box Wide Filter1

Package

MSR_C2_PMON_BOX_FILTER1

Uncore C-Box 2 Perfmon Box Wide Filter1

Package

MSR_C3_PMON_BOX_FILTER1

Uncore C-Box 3 Perfmon Box Wide Filter1

Package

MSR_C4_PMON_BOX_FILTER1

Uncore C-Box 4 Perfmon Box Wide Filter1

Package

MSR_C5_PMON_BOX_FILTER1

Uncore C-Box 5 Perfmon Box Wide Filter1

Package

MSR_C6_PMON_BOX_FILTER1

Uncore C-Box 6 Perfmon Box Wide Filter1

Package

MSR_C7_PMON_BOX_FILTER1

Uncore C-Box 7 Perfmon Box Wide Filter1

Package

MSR_C8_PMON_BOX_CTL

Uncore C-Box 8 Perfmon Local Box Wide Control

Package

MSR_C8_PMON_EVNTSEL0

Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 0

Package

MSR_C8_PMON_EVNTSEL1

Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 1

Package

MSR_C8_PMON_EVNTSEL2

Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 2

Package

MSR_C8_PMON_EVNTSEL3

2-254 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-28. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families (Contd.)

Bit Description

Scope

Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 3

Package

MSR_C8_PMON_BOX_FILTER

Uncore C-Box 8 Perfmon Box Wide Filter

Package

MSR_C8_PMON_CTR0

Uncore C-Box 8 Perfmon Counter 0

Package

MSR_C8_PMON_CTR1

Uncore C-Box 8 Perfmon Counter 1

Package

MSR_C8_PMON_CTR2

Uncore C-Box 8 Perfmon Counter 2

Package

MSR_C8_PMON_CTR3

Uncore C-Box 8 Perfmon Counter 3

Package

MSR_C8_PMON_BOX_FILTER1

Uncore C-Box 8 Perfmon Box Wide Filter1

Package

MSR_C9_PMON_BOX_CTL

Uncore C-Box 9 Perfmon Local Box Wide Control

Package

MSR_C9_PMON_EVNTSEL0

Uncore C-Box 9 Perfmon Event Select for C-box 9 Counter 0

Package

MSR_C9_PMON_EVNTSEL1

Uncore C-Box 9 Perfmon Event Select for C-box 9 Counter 1

Package

MSR_C9_PMON_EVNTSEL2

Uncore C-Box 9 Perfmon Event Select for C-box 9 Counter 2

Package

MSR_C9_PMON_EVNTSEL3

Uncore C-Box 9 Perfmon Event Select for C-box 9 Counter 3

Package

MSR_C9_PMON_BOX_FILTER

Uncore C-Box 9 Perfmon Box Wide Filter

Package

MSR_C9_PMON_CTR0

Uncore C-Box 9 Perfmon Counter 0

Package

MSR_C9_PMON_CTR1

Uncore C-Box 9 Perfmon Counter 1

Package

MSR_C9_PMON_CTR2

Uncore C-Box 9 Perfmon Counter 2

Package

MSR_C9_PMON_CTR3

Uncore C-Box 9 Perfmon Counter 3

Package

MSR_C9_PMON_BOX_FILTER1

Uncore C-Box 9 Perfmon Box Wide Filter1

Package

MSR_C10_PMON_BOX_CTL

Uncore C-Box 10 Perfmon Local Box Wide Control

Package

Vol. 4

2-255

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-28. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families (Contd.)

Bit Description

Scope

MSR_C10_PMON_EVNTSEL0

Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 0

Package

MSR_C10_PMON_EVNTSEL1

Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 1

Package

MSR_C10_PMON_EVNTSEL2

Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 2

Package

MSR_C10_PMON_EVNTSEL3

Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 3

Package

MSR_C10_PMON_BOX_FILTER

Uncore C-Box 10 Perfmon Box Wide Filter

Package

MSR_C10_PMON_CTR0

Uncore C-Box 10 Perfmon Counter 0

Package

MSR_C10_PMON_CTR1

Uncore C-Box 10 Perfmon Counter 1

Package

MSR_C10_PMON_CTR2

Uncore C-Box 10 Perfmon Counter 2

Package

MSR_C10_PMON_CTR3

Uncore C-Box 10 Perfmon Counter 3

Package

MSR_C10_PMON_BOX_FILTER1

Uncore C-Box 10 Perfmon Box Wide Filter1

Package

MSR_C11_PMON_BOX_CTL

Uncore C-Box 11 Perfmon Local Box Wide Control

Package

MSR_C11_PMON_EVNTSEL0

Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 0

Package

MSR_C11_PMON_EVNTSEL1

Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 1

Package

MSR_C11_PMON_EVNTSEL2

Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 2

Package

MSR_C11_PMON_EVNTSEL3

Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 3

Package

MSR_C11_PMON_BOX_FILTER

Uncore C-Box 11 Perfmon Box Wide Filter

Package

MSR_C11_PMON_CTR0

Uncore C-Box 11 Perfmon Counter 0

Package

MSR_C11_PMON_CTR1

Uncore C-Box 11 Perfmon Counter 1

Package

MSR_C11_PMON_CTR2

2-256 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-28. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families (Contd.)

Bit Description

Scope

Uncore C-Box 11 Perfmon Counter 2

Package

MSR_C11_PMON_CTR3

Uncore C-Box 11 Perfmon Counter 3

Package

MSR_C11_PMON_BOX_FILTER1

Uncore C-Box 11 Perfmon Box Wide Filter1

Package

MSR_C12_PMON_BOX_CTL

Uncore C-Box 12 Perfmon Local Box Wide Control

Package

MSR_C12_PMON_EVNTSEL0

Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 0

Package

MSR_C12_PMON_EVNTSEL1

Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 1

Package

MSR_C12_PMON_EVNTSEL2

Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 2

Package

MSR_C12_PMON_EVNTSEL3

Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 3

Package

MSR_C12_PMON_BOX_FILTER

Uncore C-Box 12 Perfmon Box Wide Filter

Package

MSR_C12_PMON_CTR0

Uncore C-Box 12 Perfmon Counter 0

Package

MSR_C12_PMON_CTR1

Uncore C-Box 12 Perfmon Counter 1

Package

MSR_C12_PMON_CTR2

Uncore C-Box 12 Perfmon Counter 2

Package

MSR_C12_PMON_CTR3

Uncore C-Box 12 Perfmon Counter 3

Package

MSR_C12_PMON_BOX_FILTER1

Uncore C-Box 12 Perfmon Box Wide Filter1

Package

MSR_C13_PMON_BOX_CTL

Uncore C-Box 13 Perfmon Local Box Wide Control

Package

MSR_C13_PMON_EVNTSEL0

Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 0

Package

MSR_C13_PMON_EVNTSEL1

Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 1

Package

MSR_C13_PMON_EVNTSEL2

Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 2

Package

MSR_C13_PMON_EVNTSEL3

Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 3

Package

Vol. 4

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-28. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families (Contd.)

Bit Description

Scope

MSR_C13_PMON_BOX_FILTER

Uncore C-Box 13 Perfmon Box Wide Filter

Package

MSR_C13_PMON_CTR0

Uncore C-Box 13 Perfmon Counter 0

Package

MSR_C13_PMON_CTR1

Uncore C-Box 13 Perfmon Counter 1

Package

MSR_C13_PMON_CTR2

Uncore C-Box 13 Perfmon Counter 2

Package

MSR_C13_PMON_CTR3

Uncore C-Box 13 Perfmon Counter 3

Package

MSR_C13_PMON_BOX_FILTER1

Uncore C-Box 13 Perfmon Box Wide Filter1

Package

MSR_C14_PMON_BOX_CTL

Uncore C-Box 14 Perfmon Local Box Wide Control

Package

MSR_C14_PMON_EVNTSEL0

Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 0

Package

MSR_C14_PMON_EVNTSEL1

Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 1

Package

MSR_C14_PMON_EVNTSEL2

Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 2

Package

MSR_C14_PMON_EVNTSEL3

Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 3

Package

MSR_C14_PMON_BOX_FILTER

Uncore C-Box 14 Perfmon Box Wide Filter

Package

MSR_C14_PMON_CTR0

Uncore C-Box 14 Perfmon Counter 0

Package

MSR_C14_PMON_CTR1

Uncore C-Box 14 Perfmon Counter 1

Package

MSR_C14_PMON_CTR2

Uncore C-Box 14 Perfmon Counter 2

Package

MSR_C14_PMON_CTR3

Uncore C-Box 14 Perfmon Counter 3

Package

MSR_C14_PMON_BOX_FILTER1

Uncore C-Box 14 Perfmon Box Wide Filter1

Package

2-258 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

2.13

MSRS IN THE 4TH GENERATION INTEL® CORE™ PROCESSORS BASED ON

HASWELL MICROARCHITECTURE

The 4th generation Intel^® Core™ processor family and the Intel^® Xeon^® processor E3-1200v3 product family

(based on Haswell microarchitecture), with a CPUID Signature DisplayFamily_DisplayModel value of 06_3CH,

06_45H, or 06_46H, support the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-22, and Table 2-29. For

an MSR listed in Table 2-20 that also appears in Table 2-29, Table 2-29 supersedes Table 2-20.

The MSRs listed in Table 2-29 also apply to processors based on Haswell-E microarchitecture (see Section 2.14).

Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures

Bit Description

Scope

IA32_TSC_ADJUST

Per-Logical-Processor TSC ADJUST (R/W)

Thread

See Table 2-2.

MSR_PLATFORM_INFO

Platform Information

Package

Contains power management and other model specific features enumeration. See http://biosbits.org.

7:0

Reserved.

15:8

Maximum Non-Turbo Ratio (R/O)

Package

This is the ratio of the frequency that invariant TSC runs at. Frequency =

ratio * 100 MHz.

27:16

Reserved.

Programmable Ratio Limit for Turbo Mode (R/O)

Package

When set to 1, indicates that Programmable Ratio Limit for Turbo mode is

enabled. When set to 0, indicates Programmable Ratio Limit for Turbo

mode is disabled.

Programmable TDP Limit for Turbo Mode (R/O)

Package

When set to 1, indicates that TDP Limit for Turbo mode is programmable.

When set to 0, indicates TDP Limit for Turbo mode is not programmable.

31:30

Reserved.

Low Power Mode Support (LPM) (R/O)

Package

When set to 1, indicates that LPM is supported. When set to 0, indicates

LPM is not supported.

34:33

Number of ConfigTDP Levels (R/O)

Package

00: Only Base TDP level available.

01: One additional TDP level available.

02: Two additional TDP level available.

03: Reserved.

39:35

Reserved.

47:40

Maximum Efficiency Ratio (R/O)

Package

This is the minimum ratio (maximum efficiency) that the processor can

operate, in units of 100MHz.

55:48

Minimum Operating Ratio (R/O)

Package

Contains the minimum supported operating ratio in units of 100 MHz.

63:56

Reserved.

Vol. 4

2-259

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures

Bit Description

Scope

IA32_PERFEVTSEL0

Performance Event Select for Counter 0 (R/W)

Thread

Supports all fields described inTable 2-2 and the fields below.

IN_TX: See Section 20.3.6.5.1.

When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to

prevent incorrect results.

IA32_PERFEVTSEL1

Performance Event Select for Counter 1 (R/W)

Thread

Supports all fields described inTable 2-2 and the fields below.

IN_TX: See Section 20.3.6.5.1.

When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to

prevent incorrect results.

IA32_PERFEVTSEL2

Performance Event Select for Counter 2 (R/W)

Thread

Supports all fields described inTable 2-2 and the fields below.

IN_TX: See Section 20.3.6.5.1.

When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to

prevent incorrect results.

IN_TXCP: See Section 20.3.6.5.1.

When IN_TXCP=1 & IN_TX=1 and in sampling, a spurious PMI may occur

and transactions may continuously abort near overflow conditions.

Software should favor using IN_TXCP for counting over sampling. If

sampling, software should use large “sample-after” value after clearing

the counter configured to use IN_TXCP and also always reset the counter

even when no overflow condition was reported.

IA32_PERFEVTSEL3

Performance Event Select for Counter 3 (R/W)

Thread

Supports all fields described inTable 2-2 and the fields below.

IN_TX: See Section 20.3.6.5.1

When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to

prevent incorrect results.

MSR_LBR_SELECT

Last Branch Record Filtering Select Register (R/W)

Thread

CPL_EQ_0

CPL_NEQ_0

JCC

NEAR_REL_CALL

NEAR_IND_CALL

NEAR_RET

NEAR_IND_JMP

NEAR_REL_JMP

2-260 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures

Bit Description

Scope

FAR_BRANCH

EN_CALL_STACK

63:9

Reserved.

IA32_DEBUGCTL

Debug Control (R/W)

Thread

See Table 2-2.

LBR: Last Branch Record

BTF

5:2

Reserved.

TR: Branch Trace

BTS: Log Branch Trace Message to BTS Buffer

BTINT

BTS_OFF_OS

BTS_OFF_USER

FREEZE_LBR_ON_PMI

FREEZE_PERFMON_ON_PMI

ENABLE_UNCORE_PMI

FREEZE_WHILE_SMM

RTM_DEBUG

63:15

Reserved.

IA32_VMX_VMFUNC

Capability Reporting Register of VM-Function Controls (R/O)

Thread

See Table 2-2.

MSR_PKGC_IRTL1

Package C6/C7 Interrupt Response Limit 1 (R/W)

Package

This MSR defines the interrupt response time limit used by the processor to manage a transition to a package C6 or

C7 state. The latency programmed in this register is for the shorter-latency sub C-states used by an MWAIT hint to a

C6 or C7 state.

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

ACPI C-States.

9:0

Interrupt Response Time Limit (R/W)

Specifies the limit that should be used to decide if the package should be

put into a package C6 or C7 state.

12:10

Time Unit (R/W)

Specifies the encoding value of time unit of the interrupt response time

limit. See Table 2-20 for supported time unit encodings.

14:13

Reserved.

Valid (R/W)

Indicates whether the values in bits 12:0 are valid and can be used by

the processor for package C-sate management.

Vol. 4

2-261

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures

Bit Description

Scope

63:16

Reserved.

MSR_PKGC_IRTL2

Package C6/C7 Interrupt Response Limit 2 (R/W)

Package

This MSR defines the interrupt response time limit used by the processor to manage a transition to a package C6 or

C7 state. The latency programmed in this register is for the longer-latency sub C-states used by an MWAIT hint to a C6

or C7 state.

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

ACPI C-States.

9:0

Interrupt response time limit (R/W)

Specifies the limit that should be used to decide if the package should be

put into a package C6 or C7 state.

12:10

Time Unit (R/W)

Specifies the encoding value of time unit of the interrupt response time

limit. See Table 2-20 for supported time unit encodings.

14:13

Reserved.

Valid (R/W)

Indicates whether the values in bits 12:0 are valid and can be used by

the processor for package C-sate management.

63:16

Reserved.

MSR_PKG_PERF_STATUS

PKG Perf Status (R/O)

Package

See Section 15.10.3, “Package RAPL Domain.”

MSR_DRAM_ENERGY_STATUS

DRAM Energy Status (R/O)

Package

See Section 15.10.5, “DRAM RAPL Domain.”

MSR_DRAM_PERF_STATUS

DRAM Performance Throttling Status (R/O)

Package

See Section 15.10.5, “DRAM RAPL Domain.”

MSR_CONFIG_TDP_NOMINAL

Base TDP Ratio (R/O)

Package

7:0

Config_TDP_Base

Base TDP level ratio to be used for this specific processor (in units of 100

MHz).

63:8

Reserved.

MSR_CONFIG_TDP_LEVEL1

ConfigTDP Level 1 Ratio and Power Level (R/O)

Package

14:0

PKG_TDP_LVL1

Power setting for ConfigTDP Level 1.

Reserved.

23:16

Config_TDP_LVL1_Ratio

ConfigTDP level 1 ratio to be used for this specific processor.

2-262 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures

Bit Description

Scope

31:24

Reserved.

46:32

PKG_MAX_PWR_LVL1

Max Power setting allowed for ConfigTDP Level 1.

62:47

PKG_MIN_PWR_LVL1

MIN Power setting allowed for ConfigTDP Level 1.

Reserved.

MSR_CONFIG_TDP_LEVEL2

ConfigTDP Level 2 Ratio and Power Level (R/O)

Package

14:0

PKG_TDP_LVL2

Power setting for ConfigTDP Level 2.

Reserved.

23:16

Config_TDP_LVL2_Ratio

ConfigTDP level 2 ratio to be used for this specific processor.

31:24

Reserved.

46:32

PKG_MAX_PWR_LVL2

Max Power setting allowed for ConfigTDP Level 2.

62:47

PKG_MIN_PWR_LVL2

MIN Power setting allowed for ConfigTDP Level 2.

Reserved.

MSR_CONFIG_TDP_CONTROL

ConfigTDP Control (R/W)

Package

1:0

TDP_LEVEL (RW/L)

System BIOS can program this field.

30:2

Reserved.

Config_TDP_Lock (RW/L)

When this bit is set, the content of this register is locked until a reset.

63:32

Reserved.

MSR_TURBO_ACTIVATION_RATIO

ConfigTDP Control (R/W)

Package

7:0

MAX_NON_TURBO_RATIO (RW/L)

System BIOS can program this field.

30:8

Reserved.

TURBO_ACTIVATION_RATIO_Lock (RW/L)

When this bit is set, the content of this register is locked until a reset.

63:32

Reserved.

IA32_DEBUG_INTERFACE

Silicon Debug Feature Control (R/W)

Package

See Table 2-2.

Vol. 4

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MODEL-SPECIFIC REGISTERS (MSRS)

2.13.1 MSRs in the 4th Generation Intel® Core™ Processor Family Based on Haswell

Microarchitecture

Table 2-30 lists model-specific registers (MSRs) that are specific to the 4th generation Intel^® Core™ processor

family and the Intel^® Xeon^® processor E3-1200 v3 product family (based on Haswell microarchitecture). These

processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_3CH, 06_45H, or 06_46H; see Table

2-1.

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture)

Bit Description

Scope

MSR_PKG_CST_CONFIG_CONTROL

C-State Configuration Control (R/W)

Core

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

ACPI C-states. See http://biosbits.org.

3:0

Package C-State Limit (R/W)

Specifies the lowest processor-specific C-state code name

(consuming the least power) for the package. The default is set

as factory-configured package C-state limit.

The following C-state code name encodings are supported:

0000b: C0/C1 (no package C-state support)

0001b: C2

0010b: C3

0011b: C6

0100b: C7

0101b: C7s

Package C states C7 are not available to processors with a

CPUID Signature DisplayFamily_DisplayModel value of 06_3CH.

9:4

Reserved.

I/O MWAIT Redirection Enable (R/W)

14:11

Reserved

CFG Lock (R/WO)

24:16

Reserved.

C3 State Auto Demotion Enable (R/W)

C1 State Auto Demotion Enable (R/W)

Enable C3 Undemotion (R/W)

Enable C1 Undemotion (R/W)

63:29

Reserved.

MSR_SMM_MCA_CAP

Enhanced SMM Capabilities (SMM-RO)

Thread

Reports SMM capability Enhancement. Accessible only while in SMM.

57:0

Reserved.

SMM_Code_Access_Chk (SMM-RO)

If set to 1, indicates that the SMM code access restriction is

supported and the MSR_SMM_FEATURE_CONTROL is

supported.

2-264 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Bit Description

Scope

Long_Flow_Indication (SMM-RO)

If set to 1, indicates that the SMM long flow indicator is

supported and the MSR_SMM_DELAYED is supported.

63:60

Reserved.

MSR_TURBO_RATIO_LIMIT

Maximum Ratio Limit of Turbo Mode

Package

R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.

7:0

Maximum Ratio Limit for 1C

Package

Maximum turbo ratio limit of 1 core active.

15:8

Maximum Ratio Limit for 2C

Package

Maximum turbo ratio limit of 2 core active.

23:16

Maximum Ratio Limit for 3C

Package

Maximum turbo ratio limit of 3 core active.

31:24

Maximum Ratio Limit for 4C

Package

Maximum turbo ratio limit of 4 core active.

63:32

Reserved.

MSR_UNC_PERF_GLOBAL_CTRL

Uncore PMU Global Control

Package

Core 0 select.

Core 1 select.

Core 2 select.

Core 3 select.

18:4

Reserved.

Enable all uncore counters.

Enable wake on PMI.

Enable Freezing counter when overflow.

63:32

Reserved.

MSR_UNC_PERF_GLOBAL_STATUS

Uncore PMU Main Status

Package

Fixed counter overflowed.

An ARB counter overflowed.

Reserved.

A CBox counter overflowed (on any slice).

63:4

Reserved.

MSR_UNC_PERF_FIXED_CTRL

Uncore Fixed Counter Control (R/W)

Package

19:0

Reserved.

Enable overflow propagation.

Reserved.

Vol. 4

2-265

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Bit Description

Scope

Enable counting.

63:23

Reserved.

MSR_UNC_PERF_FIXED_CTR

Uncore Fixed Counter

Package

47:0

Current count.

63:48

Reserved.

MSR_UNC_CBO_CONFIG

Uncore C-Box Configuration Information (R/O)

Package

3:0

Encoded number of C-Box, derive value by “-1“.

63:4

Reserved.

MSR_UNC_ARB_PERFCTR0

Uncore Arb Unit, Performance Counter 0

Package

MSR_UNC_ARB_PERFCTR1

Uncore Arb Unit, Performance Counter 1

Package

MSR_UNC_ARB_PERFEVTSEL0

Uncore Arb Unit, Counter 0 Event Select MSR

Package

MSR_UNC_ARB_PERFEVTSEL1

Uncore Arb Unit, Counter 1 Event Select MSR

Package

MSR_UNC_PERF_GLOBAL_CTRL

Uncore PMU Global Control

Package

Core 0 select.

Core 1 select.

Core 2 select.

Core 3 select.

18:4

Reserved.

Enable all uncore counters.

Enable wake on PMI.

Enable Freezing counter when overflow.

63:32

Reserved.

MSR_UNC_PERF_FIXED_CTR

Uncore Fixed Counter

Package

47:0

Current count.

63:48

Reserved.

MSR_UNC_ARB_PERFEVTSEL1

Uncore Arb Unit, Counter 1 Event Select MSR

Package

MSR_SMM_FEATURE_CONTROL

Enhanced SMM Feature Control (SMM-RW)

Package

Reports SMM capability Enhancement. Accessible only while in SMM.

2-266 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Bit Description

Scope

Lock (SMM-RWO)

When set to ‘1’ locks this register from further changes.

Reserved.

SMM_Code_Chk_En (SMM-RW)

This control bit is available only if MSR_SMM_MCA_CAP[58] ==

1. When set to ‘0’ (default) none of the logical processors are

prevented from executing SMM code outside the ranges defined

by the SMRR.

When set to ‘1’ any logical processor in the package that

attempts to execute SMM code not within the ranges defined

by the SMRR will assert an unrecoverable MCE.

63:3

Reserved.

MSR_SMM_DELAYED

SMM Delayed (SMM-RO)

Package

Reports the interruptible state of all logical processors in the package. Available only while in SMM and

MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.

N-1:0

LOG_PROC_STATE (SMM-RO)

Each bit represents a logical processor of its state in a long flow

of internal operation which delays servicing an interrupt. The

corresponding bit will be set at the start of long events such as:

Microcode Update Load, C6, WBINVD, Ratio Change, Throttle.

The bit is automatically cleared at the end of each long event.

The reset value of this field is 0.

Only bit positions below N = CPUID.(EAX=0BH,

ECX=PKG_LVL):EBX[15:0] can be updated.

63:N

Reserved.

MSR_SMM_BLOCKED

SMM Blocked (SMM-RO)

Package

Reports the blocked state of all logical processors in the package. Available only while in SMM.

N-1:0

LOG_PROC_STATE (SMM-RO)

Each bit represents a logical processor of its blocked state to

service an SMI. The corresponding bit will be set if the logical

processor is in one of the following states: Wait For SIPI or

SENTER Sleep.

The reset value of this field is 0FFFH.

Only bit positions below N = CPUID.(EAX=0BH,

ECX=PKG_LVL):EBX[15:0] can be updated.

63:N

Reserved.

MSR_RAPL_POWER_UNIT

Unit Multipliers Used in RAPL Interfaces (R/O)

Package

3:0

Power Units

Package

See Section 15.10.1, “RAPL Interfaces.”

7:4

Reserved.

Package

Vol. 4

2-267

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Bit Description

Scope

12:8

Energy Status Units

Package

Energy related information (in Joules) is based on the multiplier,

1/2^ESU; where ESU is an unsigned integer represented by bits

12:8. Default value is 0EH (or 61 micro-joules).

15:13

Reserved.

Package

19:16

Time Units

Package

See Section 15.10.1, “RAPL Interfaces.”

63:20

Reserved.

MSR_PP0_ENERGY_STATUS

PP0 Energy Status (R/O)

Package

See Section 15.10.4, “PP0/PP1 RAPL Domains.”

MSR_PP1_POWER_LIMIT

PP1 RAPL Power Limit Control (R/W)

Package

See Section 15.10.4, “PP0/PP1 RAPL Domains.”

MSR_PP1_ENERGY_STATUS

PP1 Energy Status (R/O)

Package

See Section 15.10.4, “PP0/PP1 RAPL Domains.”

MSR_PP1_POLICY

PP1 Balance Policy (R/W)

Package

See Section 15.10.4, “PP0/PP1 RAPL Domains.”

MSR_CORE_PERF_LIMIT_REASONS

Indicator of Frequency Clipping in Processor Cores (R/W)

Package

(Frequency refers to processor core frequency.)

PROCHOT Status (R0)

When set, processor core frequency is reduced below the

operating system request due to assertion of external

PROCHOT.

Thermal Status (R0)

When set, frequency is reduced below the operating system

request due to a thermal event.

3:2

Reserved.

Graphics Driver Status (R0)

When set, frequency is reduced below the operating system

request due to Processor Graphics driver override.

Autonomous Utilization-Based Frequency Control Status (R0)

When set, frequency is reduced below the operating system

request because the processor has detected that utilization is

low.

VR Therm Alert Status (R0)

When set, frequency is reduced below the operating system

request due to a thermal alert from the Voltage Regulator.

Reserved.

2-268 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Bit Description

Scope

Electrical Design Point Status (R0)

When set, frequency is reduced below the operating system

request due to electrical design point constraints (e.g.,

maximum electrical current consumption).

Core Power Limiting Status (R0)

When set, frequency is reduced below the operating system

request due to domain-level power limiting.

Package-Level Power Limiting PL1 Status (R0)

When set, frequency is reduced below the operating system

request due to package-level power limiting PL1.

Package-Level PL2 Power Limiting Status (R0)

When set, frequency is reduced below the operating system

request due to package-level power limiting PL2.

Max Turbo Limit Status (R0)

When set, frequency is reduced below the operating system

request due to multi-core turbo limits.

Turbo Transition Attenuation Status (R0)

When set, frequency is reduced below the operating system

request due to Turbo transition attenuation. This prevents

performance degradation due to frequent operating ratio

changes.

15:14

Reserved.

PROCHOT Log

When set, indicates that the PROCHOT Status bit has asserted

since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Thermal Log

When set, indicates that the Thermal Status bit has asserted

since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

19:18

Reserved.

Graphics Driver Log

When set, indicates that the Graphics Driver Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Autonomous Utilization-Based Frequency Control Log

When set, indicates that the Autonomous Utilization-Based

Frequency Control Status bit has asserted since the log bit was

last cleared.

This log bit will remain set until cleared by software writing 0.

VR Therm Alert Log

When set, indicates that the VR Therm Alert Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Vol. 4

2-269

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Bit Description

Scope

Reserved.

Electrical Design Point Log

When set, indicates that the EDP Status bit has asserted since

the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Core Power Limiting Log

When set, indicates that the Core Power Limiting Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Package-Level PL1 Power Limiting Log

When set, indicates that the Package Level PL1 Power Limiting

Status bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Package-Level PL2 Power Limiting Log

When set, indicates that the Package Level PL2 Power Limiting

Status bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Max Turbo Limit Log

When set, indicates that the Max Turbo Limit Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Turbo Transition Attenuation Log

When set, indicates that the Turbo Transition Attenuation

Status bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

63:30

Reserved.

MSR_GRAPHICS_PERF_LIMIT_REASONS

Indicator of Frequency Clipping in the Processor Graphics (R/W)

Package

(Frequency refers to processor graphics frequency.)

PROCHOT Status (R0)

When set, frequency is reduced below the operating system

request due to assertion of external PROCHOT.

Thermal Status (R0)

When set, frequency is reduced below the operating system

request due to a thermal event.

3:2

Reserved.

Graphics Driver Status (R0)

When set, frequency is reduced below the operating system

request due to Processor Graphics driver override.

Autonomous Utilization-Based Frequency Control Status (R0)

When set, frequency is reduced below the operating system

request because the processor has detected that utilization is

low.

2-270 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Bit Description

Scope

VR Therm Alert Status (R0)

When set, frequency is reduced below the operating system

request due to a thermal alert from the Voltage Regulator.

Reserved.

Electrical Design Point Status (R0)

When set, frequency is reduced below the operating system

request due to electrical design point constraints (e.g.,

maximum electrical current consumption).

Graphics Power Limiting Status (R0)

When set, frequency is reduced below the operating system

request due to domain-level power limiting.

Package-Level Power Limiting PL1 Status (R0)

When set, frequency is reduced below the operating system

request due to package-level power limiting PL1.

Package-Level PL2 Power Limiting Status (R0)

When set, frequency is reduced below the operating system

request due to package-level power limiting PL2.

15:12

Reserved.

PROCHOT Log

When set, indicates that the PROCHOT Status bit has asserted

since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Thermal Log

When set, indicates that the Thermal Status bit has asserted

since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

19:18

Reserved.

Graphics Driver Log

When set, indicates that the Graphics Driver Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Autonomous Utilization-Based Frequency Control Log

When set, indicates that the Autonomous Utilization-Based

Frequency Control Status bit has asserted since the log bit was

last cleared.

This log bit will remain set until cleared by software writing 0.

VR Therm Alert Log

When set, indicates that the VR Therm Alert Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Reserved.

Vol. 4

2-271

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Bit Description

Scope

Electrical Design Point Log

When set, indicates that the EDP Status bit has asserted since

the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Core Power Limiting Log

When set, indicates that the Core Power Limiting Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Package-Level PL1 Power Limiting Log

When set, indicates that the Package Level PL1 Power Limiting

Status bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Package-Level PL2 Power Limiting Log

When set, indicates that the Package Level PL2 Power Limiting

Status bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Max Turbo Limit Log

When set, indicates that the Max Turbo Limit Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Turbo Transition Attenuation Log

When set, indicates that the Turbo Transition Attenuation

Status bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

63:30

Reserved.

MSR_RING_PERF_LIMIT_REASONS

Indicator of Frequency Clipping in the Ring Interconnect (R/W)

Package

(Frequency refers to ring interconnect in the uncore.)

PROCHOT Status (R0)

When set, frequency is reduced below the operating system

request due to assertion of external PROCHOT.

Thermal Status (R0)

When set, frequency is reduced below the operating system

request due to a thermal event.

5:2

Reserved.

VR Therm Alert Status (R0)

When set, frequency is reduced below the operating system

request due to a thermal alert from the Voltage Regulator.

Reserved.

Electrical Design Point Status (R0)

When set, frequency is reduced below the operating system

request due to electrical design point constraints (e.g.,

maximum electrical current consumption).

2-272 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Bit Description

Scope

Reserved.

Package-Level Power Limiting PL1 Status (R0)

When set, frequency is reduced below the operating system

request due to package-level power limiting PL1.

Package-Level PL2 Power Limiting Status (R0)

When set, frequency is reduced below the operating system

request due to package-level power limiting PL2.

15:12

Reserved.

PROCHOT Log

When set, indicates that the PROCHOT Status bit has asserted

since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Thermal Log

When set, indicates that the Thermal Status bit has asserted

since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

19:18

Reserved.

Graphics Driver Log

When set, indicates that the Graphics Driver Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Autonomous Utilization-Based Frequency Control Log

When set, indicates that the Autonomous Utilization-Based

Frequency Control Status bit has asserted since the log bit was

last cleared.

This log bit will remain set until cleared by software writing 0.

VR Therm Alert Log

When set, indicates that the VR Therm Alert Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Reserved.

Electrical Design Point Log

When set, indicates that the EDP Status bit has asserted since

the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Core Power Limiting Log

When set, indicates that the Core Power Limiting Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Package-Level PL1 Power Limiting Log

When set, indicates that the Package Level PL1 Power Limiting

Status bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Vol. 4

2-273

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Bit Description

Scope

Package-Level PL2 Power Limiting Log

When set, indicates that the Package Level PL2 Power Limiting

Status bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Max Turbo Limit Log

When set, indicates that the Max Turbo Limit Status bit has

asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

Turbo Transition Attenuation Log

When set, indicates that the Turbo Transition Attenuation

Status bit has asserted since the log bit was last cleared.

This log bit will remain set until cleared by software writing 0.

63:30

Reserved.

MSR_UNC_CBO_0_PERFEVTSEL0

Uncore C-Box 0, Counter 0 Event Select MSR

Package

MSR_UNC_CBO_0_PERFEVTSEL1

Uncore C-Box 0, Counter 1 Event Select MSR

Package

MSR_UNC_CBO_0_PERFCTR0

Uncore C-Box 0, Performance Counter 0

Package

MSR_UNC_CBO_0_PERFCTR1

Uncore C-Box 0, Performance Counter 1

Package

MSR_UNC_CBO_1_PERFEVTSEL0

Uncore C-Box 1, Counter 0 Event Select MSR

Package

MSR_UNC_CBO_1_PERFEVTSEL1

Uncore C-Box 1, Counter 1 Event Select MSR

Package

MSR_UNC_CBO_1_PERFCTR0

Uncore C-Box 1, Performance Counter 0

Package

MSR_UNC_CBO_1_PERFCTR1

Uncore C-Box 1, Performance Counter 1

Package

MSR_UNC_CBO_2_PERFEVTSEL0

Uncore C-Box 2, Counter 0 Event Select MSR

Package

MSR_UNC_CBO_2_PERFEVTSEL1

Uncore C-Box 2, Counter 1 Event Select MSR

Package

MSR_UNC_CBO_2_PERFCTR0

Uncore C-Box 2, Performance Counter 0

Package

MSR_UNC_CBO_2_PERFCTR1

Uncore C-Box 2, Performance Counter 1

Package

MSR_UNC_CBO_3_PERFEVTSEL0

Uncore C-Box 3, Counter 0 Event Select MSR

Package

2-274 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)

Bit Description

Scope

MSR_UNC_CBO_3_PERFEVTSEL1

Uncore C-Box 3, Counter 1 Event Select MSR

Package

MSR_UNC_CBO_3_PERFCTR0

Uncore C-Box 3, Performance Counter 0

Package

MSR_UNC_CBO_3_PERFCTR1

Uncore C-Box 3, Performance Counter 1

Package

See Table 2-20, Table 2-21, Table 2-22, Table 2-25, and Table 2-29 for other MSR definitions applicable to processors with a CPUID

Signature DisplayFamily_DisplayModel value of 063CH or 06_46H.

2.13.2 Additional Residency MSRs Supported in 4th Generation Intel® Core™ Processors

The 4th generation Intel^® Core™ processor family (based on Haswell microarchitecture) with a CPUID Signature

DisplayFamily_DisplayModel value of 06_45H supports the MSR interfaces listed in Table 2-20, Table 2-21, Table

2-29, Table 2-30, and Table 2-31.

Table 2-31. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with a

CPUID Signature DisplayFamily_DisplayModel Value of 06_45H

Bit Description

Scope

MSR_PKG_CST_CONFIG_CONTROL

C-State Configuration Control (R/W)

Core

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

ACPI C-states. See http://biosbits.org.

3:0

Package C-State Limit (R/W)

Specifies the lowest processor-specific C-state code name (consuming the

least power) for the package. The default is set as factory-configured

package C-state limit.

The following C-state code name encodings are supported:

0000b: C0/C1 (no package C-state support)

0001b: C2

0010b: C3

0011b: C6

0100b: C7

0101b: C7s

0110b: C8

0111b: C9

1000b: C10

9:4

Reserved.

I/O MWAIT Redirection Enable (R/W)

14:11

Reserved.

CFG Lock (R/WO)

24:16

Reserved.

Vol. 4

2-275

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-31. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with a

CPUID Signature DisplayFamily_DisplayModel Value of 06_45H

Bit Description

Scope

C3 State Auto Demotion Enable (R/W)

C1 State Auto Demotion Enable (R/W)

Enable C3 Undemotion (R/W)

Enable C1 Undemotion (R/W)

63:29

Reserved.

MSR_PKG_C8_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Package

ACPI C-States.

59:0

Package C8 Residency Counter (R/O)

Value since last reset that this package is in processor-specific C8 states.

Count at the same frequency as the TSC.

63:60

Reserved.

MSR_PKG_C9_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Package

ACPI C-States.

59:0

Package C9 Residency Counter (R/O)

Value since last reset that this package is in processor-specific C9 states.

Count at the same frequency as the TSC.

63:60

Reserved.

MSR_PKG_C10_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Package

ACPI C-States.

59:0

Package C10 Residency Counter (R/O)

Value since last reset that this package is in processor-specific C10 states.

Count at the same frequency as the TSC.

63:60

Reserved.

See Table 2-20, Table 2-21, Table 2-22, Table 2-29, and Table 2-30 for other MSR definitions applicable to processors with a CPUID

Signature DisplayFamily_DisplayModel value of 06_45H.

2.14

MSRS IN THE INTEL® XEON® PROCESSOR E5 V3 AND E7 V3 PRODUCT

FAMILY

The Intel^® Xeon^® processor E5 v3 family and the Intel^® Xeon^® processor E7 v3 family are based on Haswell-E

microarchitecture (CPUID Signature DisplayFamily_DisplayModel value of 06_3F). These processors support the

MSR interfaces listed in Table 2-20, Table 2-29, and Table 2-32.

Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family

Bit Description

Scope

MSR_CORE_THREAD_COUNT

2-276 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family

Bit Description

Scope

Configured State of Enabled Processor Core Count and Logical Processor Count (R/O)

Package

• After a Power-On RESET, enumerates factory configuration of the number of processor cores and logical

processors in the physical package.

• Following the sequence of (i) BIOS modified a Configuration Mask which selects a subset of processor cores to be

active post RESET and (ii) a RESET event after the modification, enumerates the current configuration of enabled

processor core count and logical processor count in the physical package.

15:0

THREAD_COUNT (R/O)

The number of logical processors that are currently enabled (by either

factory configuration or BIOS configuration) in the physical package.

31:16

Core_COUNT (R/O)

The number of processor cores that are currently enabled (by either factory

configuration or BIOS configuration) in the physical package.

63:32

Reserved.

MSR_THREAD_ID_INFO

A Hardware Assigned ID for the Logical Processor (R/O)

Thread

7:0

Logical_Processor_ID (R/O)

An implementation-specific numerical value physically assigned to each

logical processor. This ID is not related to Initial APIC ID or x2APIC ID, it is

unique within a physical package.

63:8

Reserved.

MSR_PKG_CST_CONFIG_CONTROL

C-State Configuration Control (R/W)

Core

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

ACPI C-states.

See http://biosbits.org.

2:0

Package C-State Limit (R/W)

Specifies the lowest processor-specific C-state code name (consuming the

least power) for the package. The default is set as factory-configured

package C-state limit.

The following C-state code name encodings are supported:

000b: C0/C1 (no package C-state support)

001b: C2

010b: C6 (non-retention)

011b: C6 (retention)

111b: No Package C state limits. All C states supported by the processor are

available.

9:3

Reserved.

I/O MWAIT Redirection Enable (R/W)

14:11

Reserved.

CFG Lock (R/WO)

24:16

Reserved.

C3 State Auto Demotion Enable (R/W)

C1 State Auto Demotion Enable (R/W)

Vol. 4

2-277

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family

Bit Description

Scope

Enable C3 Undemotion (R/W)

Enable C1 Undemotion (R/W)

Package C State Demotion Enable (R/W)

Package C State Undemotion Enable (R/W)

63:31

Reserved.

IA32_MCG_CAP

Global Machine Check Capability (R/O)

Thread

7:0

Count

MCG_CTL_P

MCG_EXT_P

MCP_CMCI_P

MCG_TES_P

15:12

Reserved.

23:16

MCG_EXT_CNT

MCG_SER_P

MCG_EM_P

MCG_ELOG_P

63:27

Reserved.

MSR_SMM_MCA_CAP

Enhanced SMM Capabilities (SMM-RO)

Thread

Reports SMM capability Enhancement. Accessible only while in SMM.

57:0

Reserved.

SMM_Code_Access_Chk (SMM-RO)

If set to 1, indicates that the SMM code access restriction is supported and a

host-space interface available to SMM handler.

Long_Flow_Indication (SMM-RO)

If set to 1, indicates that the SMM long flow indicator is supported and a

host-space interface available to SMM handler.

63:60

Reserved.

MSR_ERROR_CONTROL

MC Bank Error Configuration (R/W)

Package

Reserved.

MemError Log Enable (R/W)

When set, enables IMC status bank to log additional info in bits 36:32.

63:2

Reserved.

MSR_TURBO_RATIO_LIMIT

Maximum Ratio Limit of Turbo Mode

Package

R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.

2-278 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family

Bit Description

Scope

7:0

Maximum Ratio Limit for 1C

Package

Maximum turbo ratio limit of 1 core active.

15:8

Maximum Ratio Limit for 2C

Package

Maximum turbo ratio limit of 2 core active.