Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

63:16

Reserved.

IA32_PERF_CTL

See Table 2-2.

Thread

IA32_CLOCK_MODULATION

Clock Modulation (R/W)

Thread

See Table 2-2.

IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR.

Reserved.

3:1

On demand Clock Modulation Duty Cycle (R/W)

On demand Clock Modulation Enable (R/W)

63:5

Reserved.

IA32_THERM_INTERRUPT

Thermal Interrupt Control (R/W)

Core

See Table 2-2.

IA32_THERM_STATUS

Thermal Monitor Status (R/W)

Core

See Table 2-2.

IA32_MISC_ENABLE

Enable Misc. Processor Features (R/W)

Allows a variety of processor functions to be enabled and disabled.

Fast-Strings Enable

Thread

See Table 2-2.

2:1

Reserved.

Automatic Thermal Control Circuit Enable (R/W)

Thread

See Table 2-2. Default value is 1.

6:4

Reserved.

Performance Monitoring Available (R)

Thread

See Table 2-2.

10:8

Reserved.

Branch Trace Storage Unavailable (R/O)

Thread

See Table 2-2.

Processor Event Based Sampling Unavailable (R/O)

Thread

See Table 2-2.

15:13

Reserved.

Enhanced Intel SpeedStep Technology Enable (R/W)

Package

See Table 2-2.

ENABLE MONITOR FSM. (R/W) See Table 2-2.

Thread

21:19

Reserved.

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2-153

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

Limit CPUID Maxval (R/W)

Thread

See Table 2-2.

xTPR Message Disable (R/W)

Thread

See Table 2-2.

33:24

Reserved.

XD Bit Disable (R/W)

Thread

See Table 2-3.

37:35

Reserved.

Turbo Mode Disable (R/W)

Package

When set to 1 on processors that support Intel Turbo Boost Technology,

the turbo mode feature is disabled and the IDA_Enable feature flag will be

clear (CPUID.06H: EAX[1]=0).

When set to a 0 on processors that support IDA, CPUID.06H: EAX[1]

reports the processor’s support of turbo mode is enabled.

Note: The power-on default value is used by BIOS to detect hardware

support of turbo mode. If the power-on default value is 1, turbo mode is

available in the processor. If the power-on default value is 0, turbo mode is

not available.

63:39

Reserved.

MSR_TEMPERATURE_TARGET

Temperature Target

Thread

15:0

Reserved.

23:16

Temperature Target (R)

The minimum temperature at which PROCHOT# will be asserted. The value

is degrees C.

63:24

Reserved.

MSR_MISC_FEATURE_CONTROL

Miscellaneous Feature Control (R/W)

L2 Hardware Prefetcher Disable (R/W)

Core

If 1, disables the L2 hardware prefetcher, which fetches additional lines of

code or data into the L2 cache.

L2 Adjacent Cache Line Prefetcher Disable (R/W)

Core

If 1, disables the adjacent cache line prefetcher, which fetches the cache

line that comprises a cache line pair (128 bytes).

DCU Hardware Prefetcher Disable (R/W)

Core

If 1, disables the L1 data cache prefetcher, which fetches the next cache

line into L1 data cache.

DCU IP Prefetcher Disable (R/W)

Core

If 1, disables the L1 data cache IP prefetcher, which uses sequential load

history (based on instruction pointer of previous loads) to determine

whether to prefetch additional lines.

63:4

Reserved.

MSR_OFFCORE_RSP_0

2-154 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

Offcore Response Event Select Register (R/W)

Thread

MSR_MISC_PWR_MGMT

Miscellaneous Power Management Control

Various model specific features enumeration. See http://biosbits.org.

EIST Hardware Coordination Disable (R/W)

Package

When 0, enables hardware coordination of Enhanced Intel Speedstep

Technology request from processor cores. When 1, disables hardware

coordination of Enhanced Intel Speedstep Technology requests.

Energy/Performance Bias Enable (R/W)

Thread

This bit makes the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible

to software with Ring 0 privileges. This bit’s status (1 or 0) is also reflected

by CPUID.(EAX=06h):ECX[3].

63:2

Reserved.

MSR_TURBO_POWER_CURRENT_LIMIT

See http://biosbits.org.

14:0

TDP Limit (R/W)

Package

TDP limit in 1/8 Watt granularity.

TDP Limit Override Enable (R/W)

Package

A value = 0 indicates override is not active; a value = 1 indicates override is

active.

30:16

TDC Limit (R/W)

Package

TDC limit in 1/8 Amp granularity.

TDC Limit Override Enable (R/W)

Package

A value = 0 indicates override is not active; a value = 1 indicates override is

active.

63:32

Reserved.

MSR_TURBO_RATIO_LIMIT

Maximum Ratio Limit of Turbo Mode

Package

R/O if MSR_PLATFORM_INFO.[28] = 0.

R/W if MSR_PLATFORM_INFO.[28] = 1.

7:0

Maximum Ratio Limit for 1C

Package

Maximum turbo ratio limit of 1 core active.

15:8

Maximum Ratio Limit for 2C

Package

Maximum turbo ratio limit of 2 core active.

23:16

Maximum Ratio Limit for 3C

Package

Maximum turbo ratio limit of 3 core active.

31:24

Maximum Ratio Limit for 4C

Package

Maximum turbo ratio limit of 4 core active.

63:32

Reserved.

MSR_LBR_SELECT

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2-155

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

Last Branch Record Filtering Select Register (R/W)

Core

See Section 18.9.2, “Filtering of Last Branch Records.”

CPL_EQ_0

CPL_NEQ_0

JCC

NEAR_REL_CALL

NEAR_IND_CALL

NEAR_RET

NEAR_IND_JMP

NEAR_REL_JMP

FAR_BRANCH

63:9

Reserved.

MSR_LASTBRANCH_TOS

Last Branch Record Stack TOS (R/W)

Thread

Contains an index (bits 0-3) that points to the MSR containing the most recent branch record.

See MSR_LASTBRANCH_0_FROM_IP (at 680H).

IA32_DEBUGCTL

Debug Control (R/W)

Thread

See Table 2-2.

MSR_LER_FROM_LIP

Last Exception Record From Linear IP (R)

Thread

Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was

generated or the last interrupt that was handled.

MSR_LER_TO_LIP

Last Exception Record To Linear IP (R)

Thread

This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last

exception that was generated or the last interrupt that was handled.

IA32_SMRR_PHYSBASE

See Table 2-2.

Core

IA32_SMRR_PHYSMASK

See Table 2-2.

Core

MSR_POWER_CTL

Power Control Register

Core

See http://biosbits.org.

Reserved.

C1E Enable (R/W)

Package

When set to ‘1’, will enable the CPU to switch to the Minimum Enhanced

Intel SpeedStep Technology operating point when all execution cores enter

MWAIT (C1).

63:2

Reserved.

2-156 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

IA32_MTRR_PHYSBASE0

See Table 2-2.

Thread

IA32_MTRR_PHYSMASK0

See Table 2-2.

Thread

IA32_MTRR_PHYSBASE1

See Table 2-2.

Thread

IA32_MTRR_PHYSMASK1

See Table 2-2.

Thread

IA32_MTRR_PHYSBASE2

See Table 2-2.

Thread

IA32_MTRR_PHYSMASK2

See Table 2-2.

Thread

IA32_MTRR_PHYSBASE3

See Table 2-2.

Thread

IA32_MTRR_PHYSMASK3

See Table 2-2.

Thread

IA32_MTRR_PHYSBASE4

See Table 2-2.

Thread

IA32_MTRR_PHYSMASK4

See Table 2-2.

Thread

IA32_MTRR_PHYSBASE5

See Table 2-2.

Thread

IA32_MTRR_PHYSMASK5

See Table 2-2.

Thread

IA32_MTRR_PHYSBASE6

See Table 2-2.

Thread

IA32_MTRR_PHYSMASK6

See Table 2-2.

Thread

IA32_MTRR_PHYSBASE7

See Table 2-2.

Thread

IA32_MTRR_PHYSMASK7

See Table 2-2.

Thread

IA32_MTRR_PHYSBASE8

See Table 2-2.

Thread

IA32_MTRR_PHYSMASK8

See Table 2-2.

Thread

IA32_MTRR_PHYSBASE9

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2-157

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

See Table 2-2.

Thread

IA32_MTRR_PHYSMASK9

See Table 2-2.

Thread

IA32_MTRR_FIX64K_00000

See Table 2-2.

Thread

IA32_MTRR_FIX16K_80000

See Table 2-2.

Thread

IA32_MTRR_FIX16K_A0000

See Table 2-2.

Thread

IA32_MTRR_FIX4K_C0000

See Table 2-2.

Thread

IA32_MTRR_FIX4K_C8000

See Table 2-2.

Thread

IA32_MTRR_FIX4K_D0000

See Table 2-2.

Thread

IA32_MTRR_FIX4K_D8000

See Table 2-2.

Thread

IA32_MTRR_FIX4K_E0000

See Table 2-2.

Thread

IA32_MTRR_FIX4K_E8000

See Table 2-2.

Thread

IA32_MTRR_FIX4K_F0000

See Table 2-2.

Thread

IA32_MTRR_FIX4K_F8000

See Table 2-2.

Thread

IA32_PAT

See Table 2-2.

Thread

IA32_MC0_CTL2

See Table 2-2.

Package

IA32_MC1_CTL2

See Table 2-2.

Package

IA32_MC2_CTL2

See Table 2-2.

Core

IA32_MC3_CTL2

See Table 2-2.

Core

IA32_MC4_CTL2

See Table 2-2.

Core

2-158 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

IA32_MC5_CTL2

See Table 2-2.

Core

IA32_MC6_CTL2

See Table 2-2.

Package

IA32_MC7_CTL2

See Table 2-2.

Package

IA32_MC8_CTL2

See Table 2-2.

Package

IA32_MTRR_DEF_TYPE

Default Memory Types (R/W)

Thread

See Table 2-2.

IA32_FIXED_CTR0

Fixed-Function Performance Counter Register 0 (R/W)

Thread

See Table 2-2.

IA32_FIXED_CTR1

Fixed-Function Performance Counter Register 1 (R/W)

Thread

See Table 2-2.

IA32_FIXED_CTR2

Fixed-Function Performance Counter Register 2 (R/W)

Thread

See Table 2-2.

IA32_PERF_CAPABILITIES

See Table 2-2. See Section 18.4.1, “IA32_DEBUGCTL MSR.”

Thread

5:0

LBR Format

See Table 2-2.

PEBS Record Format

PEBSSaveArchRegs

See Table 2-2.

11:8

PEBS_REC_FORMAT

See Table 2-2.

SMM_FREEZE

See Table 2-2.

63:13

Reserved.

IA32_FIXED_CTR_CTRL

Fixed-Function-Counter Control Register (R/W)

Thread

See Table 2-2.

IA32_PERF_GLOBAL_STATUS

See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.”

Thread

MSR_PERF_GLOBAL_STATUS

Provides single-bit status used by software to query the overflow condition of each performance counter. (R/O)

Thread

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

UNC_Ovf

Uncore overflowed if 1.

IA32_PERF_GLOBAL_CTRL

See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.”

Thread

IA32_PERF_GLOBAL_OVF_CTRL

See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.” Allows software to clear counter overflow

Thread

conditions on any combination of fixed-function PMCs (IA32_FIXED_CTRx) or general-purpose PMCs via a single

WRMSR.

MSR_PERF_GLOBAL_OVF_CTRL

(R/W)

Thread

CLR_UNC_Ovf

Set 1 to clear UNC_Ovf.

IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)

See Section 20.3.1.1.1, “Processor Event Based Sampling (PEBS).”

Thread

Enable PEBS on IA32_PMC0 (R/W)

Enable PEBS on IA32_PMC1 (R/W)

Enable PEBS on IA32_PMC2 (R/W)

Enable PEBS on IA32_PMC3 (R/W)

31:4

Reserved.

Enable Load Latency on IA32_PMC0 (R/W)

Enable Load Latency on IA32_PMC1 (R/W)

Enable Load Latency on IA32_PMC2 (R/W)

Enable Load Latency on IA32_PMC3 (R/W)

63:36

Reserved.

MSR_PEBS_LD_LAT

See Section 20.3.1.1.2, “Load Latency Performance Monitoring Facility.”

Thread

15:0

Minimum threshold latency value of tagged load operation that will be

counted. (R/W)

63:36

Reserved.

MSR_PKG_C3_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Package

ACPI C-States.

63:0

Package C3 Residency Counter (R/O)

Value since last reset that this package is in processor-specific C3 states.

Count at the same frequency as the TSC.

MSR_PKG_C6_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Package

ACPI C-States.

2-160 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

63:0

Package C6 Residency Counter (R/O)

Value since last reset that this package is in processor-specific C6 states.

Count at the same frequency as the TSC.

MSR_PKG_C7_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Package

ACPI C-States.

63:0

Package C7 Residency Counter (R/O)

Value since last reset that this package is in processor-specific C7 states.

Count at the same frequency as the TSC.

MSR_CORE_C3_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Core

ACPI C-States.

63:0

CORE C3 Residency Counter (R/O)

Value since last reset that this core is in processor-specific C3 states. Count

at the same frequency as the TSC.

MSR_CORE_C6_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or

Core

ACPI C-States.

63:0

CORE C6 Residency Counter (R/O)

Value since last reset that this core is in processor-specific C6 states. Count

at the same frequency as the TSC.

IA32_MC0_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC0_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

Package

IA32_MC0_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC0_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC0_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

IA32_MC1_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC1_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

Package

IA32_MC1_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC1_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

Vol. 4

2-161

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

IA32_MC1_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

IA32_MC2_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Core

IA32_MC2_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

Core

IA32_MC2_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Core

The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the

IA32_MC2_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC2_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Core

IA32_MC3_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Core

IA32_MC3_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

Core

IA32_MC3_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Core

The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the

MSR_MC4_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC3_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Core

IA32_MC4_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Core

IA32_MC4_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

Core

IA32_MC4_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Core

The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the

MSR_MC3_STATUS register is clear.

When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC4_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Core

IA32_MC5_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Core

IA32_MC5_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”

Core

2-162 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

IA32_MC5_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Core

IA32_MC5_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Core

IA32_MC6_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC6_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17.

Package

IA32_MC6_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

IA32_MC6_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

IA32_MC7_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC7_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17.

Package

IA32_MC7_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

IA32_MC7_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

IA32_MC8_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC8_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17.

Package

IA32_MC8_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

IA32_MC8_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

IA32_VMX_BASIC

Reporting Register of Basic VMX Capabilities (R/O)

Thread

See Table 2-2 and Appendix A.1, “Basic VMX Information.”

IA32_VMX_PINBASED_CTLS

Capability Reporting Register of Pin-based VM-execution Controls (R/O)

Thread

See Table 2-2 and Appendix A.3, “VM-Execution Controls.”

IA32_VMX_PROCBASED_CTLS

Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)

Thread

See Appendix A.3, “VM-Execution Controls.”

IA32_VMX_EXIT_CTLS

Vol. 4

2-163

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

Capability Reporting Register of VM-Exit Controls (R/O)

Thread

See Table 2-2 and Appendix A.4, “VM-Exit Controls.”

IA32_VMX_ENTRY_CTLS

Capability Reporting Register of VM-Entry Controls (R/O)

Thread

See Table 2-2 and Appendix A.5, “VM-Entry Controls.”

IA32_VMX_MISC

Reporting Register of Miscellaneous VMX Capabilities (R/O)

Thread

See Table 2-2 and Appendix A.6, “Miscellaneous Data.”

IA32_VMX_CR0_FIXED0

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)

Thread

See Table 2-2 and Appendix A.7, “VMX-Fixed Bits in CR0.”

IA32_VMX_CR0_FIXED1

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)

Thread

See Table 2-2 and Appendix A.7, “VMX-Fixed Bits in CR0.”

IA32_VMX_CR4_FIXED0

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)

Thread

See Table 2-2 and Appendix A.8, “VMX-Fixed Bits in CR4.”

IA32_VMX_CR4_FIXED1

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)

Thread

See Table 2-2 and Appendix A.8, “VMX-Fixed Bits in CR4.”

IA32_VMX_VMCS_ENUM

Capability Reporting Register of VMCS Field Enumeration (R/O)

Thread

See Table 2-2 and Appendix A.9, “VMCS Enumeration.”

IA32_VMX_PROCBASED_CTLS2

Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)

Thread

See Appendix A.3, “VM-Execution Controls.”

IA32_DS_AREA

DS Save Area (R/W)

Thread

See Table 2-2 and Section 20.6.3.4, “Debug Store (DS) Mechanism.”

MSR_LASTBRANCH_0_FROM_IP

Last Branch Record 0 From IP (R/W)

Thread

One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack

contains pointers to the source instruction. See also:

• Last Branch Record Stack TOS at 1C9H.

• See Section 18.9.1 and record format in Section 18.4.8.1.

MSR_LASTBRANCH_1_FROM_IP

Last Branch Record 1 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_2_FROM_IP

2-164 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

Last Branch Record 2 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_3_FROM_IP

Last Branch Record 3 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_4_FROM_IP

Last Branch Record 4 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_5_FROM_IP

Last Branch Record 5 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_6_FROM_IP

Last Branch Record 6 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_7_FROM_IP

Last Branch Record 7 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_8_FROM_IP

Last Branch Record 8 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_9_FROM_IP

Last Branch Record 9 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_10_FROM_IP

Last Branch Record 10 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_11_FROM_IP

Last Branch Record 11 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_12_FROM_IP

Last Branch Record 12 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_13_FROM_IP

Last Branch Record 13 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_14_FROM_IP

Last Branch Record 14 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_15_FROM_IP

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2-165

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

Last Branch Record 15 From IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_0_TO_IP

Last Branch Record 0 To IP (R/W)

Thread

One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains

pointers to the destination instruction.

MSR_LASTBRANCH_1_TO_IP

Last Branch Record 1 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_2_TO_IP

Last Branch Record 2 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_3_TO_IP

Last Branch Record 3 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_4_TO_IP

Last Branch Record 4 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_5_TO_IP

Last Branch Record 5 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_6_TO_IP

Last Branch Record 6 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_7_TO_IP

Last Branch Record 7 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_8_TO_IP

Last Branch Record 8 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_9_TO_IP

Last Branch Record 9 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_10_TO_IP

Last Branch Record 10 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_11_TO_IP

Last Branch Record 11 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

2-166 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

MSR_LASTBRANCH_12_TO_IP

Last Branch Record 12 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_13_TO_IP

Last Branch Record 13 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_14_TO_IP

Last Branch Record 14 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_15_TO_IP

Last Branch Record 15 To IP (R/W)

Thread

See description of MSR_LASTBRANCH_0_TO_IP.

IA32_X2APIC_APICID

x2APIC ID Register (R/O)

Thread

IA32_X2APIC_VERSION

x2APIC Version Register (R/O)

Thread

IA32_X2APIC_TPR

x2APIC Task Priority Register (R/W)

Thread

IA32_X2APIC_PPR

x2APIC Processor Priority Register (R/O)

Thread

IA32_X2APIC_EOI

x2APIC EOI Register (W/O)

Thread

IA32_X2APIC_LDR

x2APIC Logical Destination Register (R/O)

Thread

IA32_X2APIC_SIVR

x2APIC Spurious Interrupt Vector Register (R/W)

Thread

IA32_X2APIC_ISR0

x2APIC In-Service Register Bits [31:0] (R/O)

Thread

IA32_X2APIC_ISR1

x2APIC In-Service Register Bits [63:32] (R/O)

Thread

IA32_X2APIC_ISR2

x2APIC In-Service Register Bits [95:64] (R/O)

Thread

IA32_X2APIC_ISR3

x2APIC In-Service Register Bits [127:96] (R/O)

Thread

IA32_X2APIC_ISR4

x2APIC In-Service Register Bits [159:128] (R/O)

Thread

IA32_X2APIC_ISR5

x2APIC In-Service Register Bits [191:160] (R/O)

Thread

Vol. 4

2-167

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

IA32_X2APIC_ISR6

x2APIC In-Service Register Bits [223:192] (R/O)

Thread

IA32_X2APIC_ISR7

x2APIC In-Service Register Bits [255:224] (R/O)

Thread

IA32_X2APIC_TMR0

x2APIC Trigger Mode Register Bits [31:0] (R/O)

Thread

IA32_X2APIC_TMR1

x2APIC Trigger Mode Register Bits [63:32] (R/O)

Thread

IA32_X2APIC_TMR2

x2APIC Trigger Mode Register Bits [95:64] (R/O)

Thread

IA32_X2APIC_TMR3

x2APIC Trigger Mode Register Bits [127:96] (R/O)

Thread

IA32_X2APIC_TMR4

x2APIC Trigger Mode Register Bits [159:128] (R/O)

Thread

IA32_X2APIC_TMR5

x2APIC Trigger Mode Register Bits [191:160] (R/O)

Thread

IA32_X2APIC_TMR6

x2APIC Trigger Mode Register Bits [223:192] (R/O)

Thread

IA32_X2APIC_TMR7

x2APIC Trigger Mode Register Bits [255:224] (R/O)

Thread

IA32_X2APIC_IRR0

x2APIC Interrupt Request Register Bits [31:0] (R/O)

Thread

IA32_X2APIC_IRR1

x2APIC Interrupt Request Register Bits [63:32] (R/O)

Thread

IA32_X2APIC_IRR2

x2APIC Interrupt Request Register Bits [95:64] (R/O)

Thread

IA32_X2APIC_IRR3

x2APIC Interrupt Request Register Bits [127:96] (R/O)

Thread

IA32_X2APIC_IRR4

x2APIC Interrupt Request Register Bits [159:128] (R/O)

Thread

IA32_X2APIC_IRR5

x2APIC Interrupt Request Register Bits [191:160] (R/O)

Thread

IA32_X2APIC_IRR6

x2APIC Interrupt Request Register Bits [223:192] (R/O)

Thread

IA32_X2APIC_IRR7

x2APIC Interrupt Request Register Bits [255:224] (R/O)

Thread

IA32_X2APIC_ESR

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

x2APIC Error Status Register (R/W)

Thread

IA32_X2APIC_LVT_CMCI

x2APIC LVT Corrected Machine Check Interrupt Register (R/W)

Thread

IA32_X2APIC_ICR

x2APIC Interrupt Command Register (R/W)

Thread

IA32_X2APIC_LVT_TIMER

x2APIC LVT Timer Interrupt Register (R/W)

Thread

IA32_X2APIC_LVT_THERMAL

x2APIC LVT Thermal Sensor Interrupt Register (R/W)

Thread

IA32_X2APIC_LVT_PMI

x2APIC LVT Performance Monitor Register (R/W)

Thread

IA32_X2APIC_LVT_LINT0

x2APIC LVT LINT0 Register (R/W)

Thread

IA32_X2APIC_LVT_LINT1

x2APIC LVT LINT1 Register (R/W)

Thread

IA32_X2APIC_LVT_ERROR

x2APIC LVT Error Register (R/W)

Thread

IA32_X2APIC_INIT_COUNT

x2APIC Initial Count Register (R/W)

Thread

IA32_X2APIC_CUR_COUNT

x2APIC Current Count Register (R/O)

Thread

IA32_X2APIC_DIV_CONF

x2APIC Divide Configuration Register (R/W)

Thread

IA32_X2APIC_SELF_IPI

x2APIC Self IPI Register (W/O)

Thread

IA32_EFER

Extended Feature Enables

Thread

See Table 2-2.

IA32_STAR

System Call Target Address (R/W)

Thread

See Table 2-2.

IA32_LSTAR

IA-32e Mode System Call Target Address (R/W)

Thread

See Table 2-2.

IA32_FMASK

System Call Flag Mask (R/W)

Thread

See Table 2-2.

IA32_FS_BASE

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)

Bit Description

Scope

Map of BASE Address of FS (R/W)

Thread

See Table 2-2.

IA32_GS_BASE

Map of BASE Address of GS (R/W)

Thread

See Table 2-2.

IA32_KERNEL_GS_BASE

Swap Target of BASE Address of GS (R/W)

Thread

See Table 2-2.

IA32_TSC_AUX

AUXILIARY TSC Signature (R/W)

Thread

See Table 2-2 and Section 18.17.2, “IA32_TSC_AUX Register and RDTSCP Support.”

2.8.1

Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series

The Intel Xeon Processor 5500 and 3400 series supports additional model-specific registers listed in Table 2-16.

These MSRs also apply to the Intel Core i7 and i5 processor family with a CPUID Signature

DisplayFamily_DisplayModel value of 06_1AH, 06_1EH, or 06_1FH; see Table 2-1.

Table 2-16. Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series

Bit Description

Scope

MSR_TURBO_RATIO_LIMIT

Actual maximum turbo frequency is multiplied by 133.33MHz.

Package

(Not available in model 06_2EH.)

7:0

Maximum Turbo Ratio Limit 1C (R/O)

Maximum Turbo mode ratio limit with 1 core active.

15:8

Maximum Turbo Ratio Limit 2C (R/O)

Maximum Turbo mode ratio limit with 2 cores active.

23:16

Maximum Turbo Ratio Limit 3C (R/O)

Maximum Turbo mode ratio limit with 3 cores active.

31:24

Maximum Turbo Ratio Limit 4C (R/O)

Maximum Turbo mode ratio limit with 4 cores active.

63:32

Reserved.

MSR_GQ_SNOOP_MESF

Package

From M to S (R/W)

From E to S (R/W)

From S to S (R/W)

From F to S (R/W)

From M to I (R/W)

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-16. Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series (Contd.)

Bit Description

Scope

From E to I (R/W)

From S to I (R/W)

From F to I (R/W)

63:8

Reserved.

MSR_UNCORE_PERF_GLOBAL_CTRL

See Section 20.3.1.2.1, “Uncore Performance Monitoring Management Facility.”

Package

MSR_UNCORE_PERF_GLOBAL_STATUS

See Section 20.3.1.2.1, “Uncore Performance Monitoring Management Facility.”

Package

MSR_UNCORE_PERF_GLOBAL_OVF_CTRL

See Section 20.3.1.2.1, “Uncore Performance Monitoring Management Facility.”

Package

MSR_UNCORE_FIXED_CTR0

See Section 20.3.1.2.1, “Uncore Performance Monitoring Management Facility.”

Package

MSR_UNCORE_FIXED_CTR_CTRL

See Section 20.3.1.2.1, “Uncore Performance Monitoring Management Facility.”

Package

MSR_UNCORE_ADDR_OPCODE_MATCH

See Section 20.3.1.2.3, “Uncore Address/Opcode Match MSR.”

Package

MSR_UNCORE_PMC0

See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

MSR_UNCORE_PMC1

See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

MSR_UNCORE_PMC2

See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

MSR_UNCORE_PMC3

See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

MSR_UNCORE_PMC4

See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

MSR_UNCORE_PMC5

See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

MSR_UNCORE_PMC6

See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

MSR_UNCORE_PMC7

See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

MSR_UNCORE_PERFEVTSEL0

See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

MSR_UNCORE_PERFEVTSEL1

See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

MSR_UNCORE_PERFEVTSEL2

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-16. Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series (Contd.)

Bit Description

Scope

See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

MSR_UNCORE_PERFEVTSEL3

See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

MSR_UNCORE_PERFEVTSEL4

See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

MSR_UNCORE_PERFEVTSEL5

See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

MSR_UNCORE_PERFEVTSEL6

See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

MSR_UNCORE_PERFEVTSEL7

See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

2.8.2

Additional MSRs in the Intel® Xeon® Processor 7500 Series

The Intel Xeon Processor 7500 series supports MSRs listed in Table 2-15 (except MSR address 1ADH) and additional

model-specific registers listed in Table 2-17. These processors have a CPUID Signature

DisplayFamily_DisplayModel value of 06_2EH.

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series

Bit Description

Scope

MSR_TURBO_RATIO_LIMIT

Reserved. Attempt to read/write will cause #UD.

Package

IA32_MC9_CTL2

See Table 2-2.

Package

IA32_MC10_CTL2

See Table 2-2.

Package

IA32_MC11_CTL2

See Table 2-2.

Package

IA32_MC12_CTL2

See Table 2-2.

Package

IA32_MC13_CTL2

See Table 2-2.

Package

IA32_MC14_CTL2

See Table 2-2.

Package

IA32_MC15_CTL2

See Table 2-2.

Package

IA32_MC16_CTL2

See Table 2-2.

Package

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

IA32_MC17_CTL2

See Table 2-2.

Package

IA32_MC18_CTL2

See Table 2-2.

Package

IA32_MC19_CTL2

See Table 2-2.

Package

IA32_MC20_CTL2

See Table 2-2.

Package

IA32_MC21_CTL2

See Table 2-2.

Package

MSR_W_PMON_FIXED_CTR

Uncore W-box perfmon fixed counter.

Package

MSR_W_PMON_FIXED_CTR_CTL

Uncore U-box perfmon fixed counter control MSR.

Package

IA32_MC9_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC9_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17.

Package

IA32_MC9_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

IA32_MC9_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

IA32_MC10_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC10_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17.

Package

IA32_MC10_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

IA32_MC10_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

IA32_MC11_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC11_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17.

Package

IA32_MC11_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

IA32_MC11_MISC

Vol. 4

2-173

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

IA32_MC12_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC12_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17.

Package

IA32_MC12_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

IA32_MC12_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

IA32_MC13_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC13_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17.

Package

IA32_MC13_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

IA32_MC13_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

IA32_MC14_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC14_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17.

Package

IA32_MC14_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

IA32_MC14_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

IA32_MC15_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC15_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17.

Package

IA32_MC15_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

IA32_MC15_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

IA32_MC16_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC16_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17.

Package

2-174 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

IA32_MC16_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

IA32_MC16_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

IA32_MC17_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC17_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17.

Package

IA32_MC17_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

IA32_MC17_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

IA32_MC18_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC18_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17.

Package

IA32_MC18_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

IA32_MC18_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

IA32_MC19_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC19_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17.

Package

IA32_MC19_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

IA32_MC19_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

IA32_MC20_CTL

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC20_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17.

Package

IA32_MC20_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

IA32_MC20_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

IA32_MC21_CTL

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MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”

Package

IA32_MC21_STATUS

See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17.

Package

IA32_MC21_ADDR

See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”

Package

IA32_MC21_MISC

See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”

Package

MSR_U_PMON_GLOBAL_CTRL

Uncore U-box perfmon global control MSR.

Package

MSR_U_PMON_GLOBAL_STATUS

Uncore U-box perfmon global status MSR.

Package

MSR_U_PMON_GLOBAL_OVF_CTRL

Uncore U-box perfmon global overflow control MSR.

Package

MSR_U_PMON_EVNT_SEL

Uncore U-box perfmon event select MSR.

Package

MSR_U_PMON_CTR

Uncore U-box perfmon counter MSR.

Package

MSR_B0_PMON_BOX_CTRL

Uncore B-box 0 perfmon local box control MSR.

Package

MSR_B0_PMON_BOX_STATUS

Uncore B-box 0 perfmon local box status MSR.

Package

MSR_B0_PMON_BOX_OVF_CTRL

Uncore B-box 0 perfmon local box overflow control MSR.

Package

MSR_B0_PMON_EVNT_SEL0

Uncore B-box 0 perfmon event select MSR.

Package

MSR_B0_PMON_CTR0

Uncore B-box 0 perfmon counter MSR.

Package

MSR_B0_PMON_EVNT_SEL1

Uncore B-box 0 perfmon event select MSR.

Package

MSR_B0_PMON_CTR1

Uncore B-box 0 perfmon counter MSR.

Package

MSR_B0_PMON_EVNT_SEL2

Uncore B-box 0 perfmon event select MSR.

Package

MSR_B0_PMON_CTR2

Uncore B-box 0 perfmon counter MSR.

Package

MSR_B0_PMON_EVNT_SEL3

Uncore B-box 0 perfmon event select MSR.

Package

2-176 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

MSR_B0_PMON_CTR3

Uncore B-box 0 perfmon counter MSR.

Package

MSR_S0_PMON_BOX_CTRL

Uncore S-box 0 perfmon local box control MSR.

Package

MSR_S0_PMON_BOX_STATUS

Uncore S-box 0 perfmon local box status MSR.

Package

MSR_S0_PMON_BOX_OVF_CTRL

Uncore S-box 0 perfmon local box overflow control MSR.

Package

MSR_S0_PMON_EVNT_SEL0

Uncore S-box 0 perfmon event select MSR.

Package

MSR_S0_PMON_CTR0

Uncore S-box 0 perfmon counter MSR.

Package

MSR_S0_PMON_EVNT_SEL1

Uncore S-box 0 perfmon event select MSR.

Package

MSR_S0_PMON_CTR1

Uncore S-box 0 perfmon counter MSR.

Package

MSR_S0_PMON_EVNT_SEL2

Uncore S-box 0 perfmon event select MSR.

Package

MSR_S0_PMON_CTR2

Uncore S-box 0 perfmon counter MSR.

Package

MSR_S0_PMON_EVNT_SEL3

Uncore S-box 0 perfmon event select MSR.

Package

MSR_S0_PMON_CTR3

Uncore S-box 0 perfmon counter MSR.

Package

MSR_B1_PMON_BOX_CTRL

Uncore B-box 1 perfmon local box control MSR.

Package

MSR_B1_PMON_BOX_STATUS

Uncore B-box 1 perfmon local box status MSR.

Package

MSR_B1_PMON_BOX_OVF_CTRL

Uncore B-box 1 perfmon local box overflow control MSR.

Package

MSR_B1_PMON_EVNT_SEL0

Uncore B-box 1 perfmon event select MSR.

Package

MSR_B1_PMON_CTR0

Uncore B-box 1 perfmon counter MSR.

Package

MSR_B1_PMON_EVNT_SEL1

Uncore B-box 1 perfmon event select MSR.

Package

MSR_B1_PMON_CTR1

Vol. 4

2-177

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

Uncore B-box 1 perfmon counter MSR.

Package

MSR_B1_PMON_EVNT_SEL2

Uncore B-box 1 perfmon event select MSR.

Package

MSR_B1_PMON_CTR2

Uncore B-box 1 perfmon counter MSR.

Package

MSR_B1_PMON_EVNT_SEL3

Uncore B-box 1vperfmon event select MSR.

Package

MSR_B1_PMON_CTR3

Uncore B-box 1 perfmon counter MSR.

Package

MSR_W_PMON_BOX_CTRL

Uncore W-box perfmon local box control MSR.

Package

MSR_W_PMON_BOX_STATUS

Uncore W-box perfmon local box status MSR.

Package

MSR_W_PMON_BOX_OVF_CTRL

Uncore W-box perfmon local box overflow control MSR.

Package

MSR_W_PMON_EVNT_SEL0

Uncore W-box perfmon event select MSR.

Package

MSR_W_PMON_CTR0

Uncore W-box perfmon counter MSR.

Package

MSR_W_PMON_EVNT_SEL1

Uncore W-box perfmon event select MSR.

Package

MSR_W_PMON_CTR1

Uncore W-box perfmon counter MSR.

Package

MSR_W_PMON_EVNT_SEL2

Uncore W-box perfmon event select MSR.

Package

MSR_W_PMON_CTR2

Uncore W-box perfmon counter MSR.

Package

MSR_W_PMON_EVNT_SEL3

Uncore W-box perfmon event select MSR.

Package

MSR_W_PMON_CTR3

Uncore W-box perfmon counter MSR.

Package

MSR_M0_PMON_BOX_CTRL

Uncore M-box 0 perfmon local box control MSR.

Package

MSR_M0_PMON_BOX_STATUS

Uncore M-box 0 perfmon local box status MSR.

Package

MSR_M0_PMON_BOX_OVF_CTRL

Uncore M-box 0 perfmon local box overflow control MSR.

Package

2-178 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

MSR_M0_PMON_TIMESTAMP

Uncore M-box 0 perfmon time stamp unit select MSR.

Package

MSR_M0_PMON_DSP

Uncore M-box 0 perfmon DSP unit select MSR.

Package

MSR_M0_PMON_ISS

Uncore M-box 0 perfmon ISS unit select MSR.

Package

MSR_M0_PMON_MAP

Uncore M-box 0 perfmon MAP unit select MSR.

Package

MSR_M0_PMON_MSC_THR

Uncore M-box 0 perfmon MIC THR select MSR.

Package

MSR_M0_PMON_PGT

Uncore M-box 0 perfmon PGT unit select MSR.

Package

MSR_M0_PMON_PLD

Uncore M-box 0 perfmon PLD unit select MSR.

Package

MSR_M0_PMON_ZDP

Uncore M-box 0 perfmon ZDP unit select MSR.

Package

MSR_M0_PMON_EVNT_SEL0

Uncore M-box 0 perfmon event select MSR.

Package

MSR_M0_PMON_CTR0

Uncore M-box 0 perfmon counter MSR.

Package

MSR_M0_PMON_EVNT_SEL1

Uncore M-box 0 perfmon event select MSR.

Package

MSR_M0_PMON_CTR1

Uncore M-box 0 perfmon counter MSR.

Package

MSR_M0_PMON_EVNT_SEL2

Uncore M-box 0 perfmon event select MSR.

Package

MSR_M0_PMON_CTR2

Uncore M-box 0 perfmon counter MSR.

Package

MSR_M0_PMON_EVNT_SEL3

Uncore M-box 0 perfmon event select MSR.

Package

MSR_M0_PMON_CTR3

Uncore M-box 0 perfmon counter MSR.

Package

MSR_M0_PMON_EVNT_SEL4

Uncore M-box 0 perfmon event select MSR.

Package

MSR_M0_PMON_CTR4

Uncore M-box 0 perfmon counter MSR.

Package

MSR_M0_PMON_EVNT_SEL5

Vol. 4

2-179

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

Uncore M-box 0 perfmon event select MSR.

Package

MSR_M0_PMON_CTR5

Uncore M-box 0 perfmon counter MSR.

Package

MSR_S1_PMON_BOX_CTRL

Uncore S-box 1 perfmon local box control MSR.

Package

MSR_S1_PMON_BOX_STATUS

Uncore S-box 1 perfmon local box status MSR.

Package

MSR_S1_PMON_BOX_OVF_CTRL

Uncore S-box 1 perfmon local box overflow control MSR.

Package

MSR_S1_PMON_EVNT_SEL0

Uncore S-box 1 perfmon event select MSR.

Package

MSR_S1_PMON_CTR0

Uncore S-box 1 perfmon counter MSR.

Package

MSR_S1_PMON_EVNT_SEL1

Uncore S-box 1 perfmon event select MSR.

Package

MSR_S1_PMON_CTR1

Uncore S-box 1 perfmon counter MSR.

Package

MSR_S1_PMON_EVNT_SEL2

Uncore S-box 1 perfmon event select MSR.

Package

MSR_S1_PMON_CTR2

Uncore S-box 1 perfmon counter MSR.

Package

MSR_S1_PMON_EVNT_SEL3

Uncore S-box 1 perfmon event select MSR.

Package

MSR_S1_PMON_CTR3

Uncore S-box 1 perfmon counter MSR.

Package

MSR_M1_PMON_BOX_CTRL

Uncore M-box 1 perfmon local box control MSR.

Package

MSR_M1_PMON_BOX_STATUS

Uncore M-box 1 perfmon local box status MSR.

Package

MSR_M1_PMON_BOX_OVF_CTRL

Uncore M-box 1 perfmon local box overflow control MSR.

Package

MSR_M1_PMON_TIMESTAMP

Uncore M-box 1 perfmon time stamp unit select MSR.

Package

MSR_M1_PMON_DSP

Uncore M-box 1 perfmon DSP unit select MSR.

Package

MSR_M1_PMON_ISS

Uncore M-box 1 perfmon ISS unit select MSR.

Package

2-180 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

MSR_M1_PMON_MAP

Uncore M-box 1 perfmon MAP unit select MSR.

Package

MSR_M1_PMON_MSC_THR

Uncore M-box 1 perfmon MIC THR select MSR.

Package

MSR_M1_PMON_PGT

Uncore M-box 1 perfmon PGT unit select MSR.

Package

MSR_M1_PMON_PLD

Uncore M-box 1 perfmon PLD unit select MSR.

Package

MSR_M1_PMON_ZDP

Uncore M-box 1 perfmon ZDP unit select MSR.

Package

MSR_M1_PMON_EVNT_SEL0

Uncore M-box 1 perfmon event select MSR.

Package

MSR_M1_PMON_CTR0

Uncore M-box 1 perfmon counter MSR.

Package

MSR_M1_PMON_EVNT_SEL1

Uncore M-box 1 perfmon event select MSR.

Package

MSR_M1_PMON_CTR1

Uncore M-box 1 perfmon counter MSR.

Package

MSR_M1_PMON_EVNT_SEL2

Uncore M-box 1 perfmon event select MSR.

Package

MSR_M1_PMON_CTR2

Uncore M-box 1 perfmon counter MSR.

Package

MSR_M1_PMON_EVNT_SEL3

Uncore M-box 1 perfmon event select MSR.

Package

MSR_M1_PMON_CTR3

Uncore M-box 1 perfmon counter MSR.

Package

MSR_M1_PMON_EVNT_SEL4

Uncore M-box 1 perfmon event select MSR.

Package

MSR_M1_PMON_CTR4

Uncore M-box 1 perfmon counter MSR.

Package

MSR_M1_PMON_EVNT_SEL5

Uncore M-box 1 perfmon event select MSR.

Package

MSR_M1_PMON_CTR5

Uncore M-box 1 perfmon counter MSR.

Package

MSR_C0_PMON_BOX_CTRL

Uncore C-box 0 perfmon local box control MSR.

Package

MSR_C0_PMON_BOX_STATUS

Vol. 4

2-181

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

Uncore C-box 0 perfmon local box status MSR.

Package

MSR_C0_PMON_BOX_OVF_CTRL

Uncore C-box 0 perfmon local box overflow control MSR.

Package

MSR_C0_PMON_EVNT_SEL0

Uncore C-box 0 perfmon event select MSR.

Package

MSR_C0_PMON_CTR0

Uncore C-box 0 perfmon counter MSR.

Package

MSR_C0_PMON_EVNT_SEL1

Uncore C-box 0 perfmon event select MSR.

Package

MSR_C0_PMON_CTR1

Uncore C-box 0 perfmon counter MSR.

Package

MSR_C0_PMON_EVNT_SEL2

Uncore C-box 0 perfmon event select MSR.

Package

MSR_C0_PMON_CTR2

Uncore C-box 0 perfmon counter MSR.

Package

MSR_C0_PMON_EVNT_SEL3

Uncore C-box 0 perfmon event select MSR.

Package

MSR_C0_PMON_CTR3

Uncore C-box 0 perfmon counter MSR.

Package

MSR_C0_PMON_EVNT_SEL4

Uncore C-box 0 perfmon event select MSR.

Package

MSR_C0_PMON_CTR4

Uncore C-box 0 perfmon counter MSR.

Package

MSR_C0_PMON_EVNT_SEL5

Uncore C-box 0 perfmon event select MSR.

Package

MSR_C0_PMON_CTR5

Uncore C-box 0 perfmon counter MSR.

Package

MSR_C4_PMON_BOX_CTRL

Uncore C-box 4 perfmon local box control MSR.

Package

MSR_C4_PMON_BOX_STATUS

Uncore C-box 4 perfmon local box status MSR.

Package

MSR_C4_PMON_BOX_OVF_CTRL

Uncore C-box 4 perfmon local box overflow control MSR.

Package

MSR_C4_PMON_EVNT_SEL0

Uncore C-box 4 perfmon event select MSR.

Package

MSR_C4_PMON_CTR0

Uncore C-box 4 perfmon counter MSR.

Package

2-182 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

MSR_C4_PMON_EVNT_SEL1

Uncore C-box 4 perfmon event select MSR.

Package

MSR_C4_PMON_CTR1

Uncore C-box 4 perfmon counter MSR.

Package

MSR_C4_PMON_EVNT_SEL2

Uncore C-box 4 perfmon event select MSR.

Package

MSR_C4_PMON_CTR2

Uncore C-box 4 perfmon counter MSR.

Package

MSR_C4_PMON_EVNT_SEL3

Uncore C-box 4 perfmon event select MSR.

Package

MSR_C4_PMON_CTR3

Uncore C-box 4 perfmon counter MSR.

Package

MSR_C4_PMON_EVNT_SEL4

Uncore C-box 4 perfmon event select MSR.

Package

MSR_C4_PMON_CTR4

Uncore C-box 4 perfmon counter MSR.

Package

MSR_C4_PMON_EVNT_SEL5

Uncore C-box 4 perfmon event select MSR.

Package

MSR_C4_PMON_CTR5

Uncore C-box 4 perfmon counter MSR.

Package

MSR_C2_PMON_BOX_CTRL

Uncore C-box 2 perfmon local box control MSR.

Package

MSR_C2_PMON_BOX_STATUS

Uncore C-box 2 perfmon local box status MSR.

Package

MSR_C2_PMON_BOX_OVF_CTRL

Uncore C-box 2 perfmon local box overflow control MSR.

Package

MSR_C2_PMON_EVNT_SEL0

Uncore C-box 2 perfmon event select MSR.

Package

MSR_C2_PMON_CTR0

Uncore C-box 2 perfmon counter MSR.

Package

MSR_C2_PMON_EVNT_SEL1

Uncore C-box 2 perfmon event select MSR.

Package

MSR_C2_PMON_CTR1

Uncore C-box 2 perfmon counter MSR.

Package

MSR_C2_PMON_EVNT_SEL2

Uncore C-box 2 perfmon event select MSR.

Package

MSR_C2_PMON_CTR2

Vol. 4

2-183

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

Uncore C-box 2 perfmon counter MSR.

Package

MSR_C2_PMON_EVNT_SEL3

Uncore C-box 2 perfmon event select MSR.

Package

MSR_C2_PMON_CTR3

Uncore C-box 2 perfmon counter MSR.

Package

MSR_C2_PMON_EVNT_SEL4

Uncore C-box 2 perfmon event select MSR.

Package

MSR_C2_PMON_CTR4

Uncore C-box 2 perfmon counter MSR.

Package

MSR_C2_PMON_EVNT_SEL5

Uncore C-box 2 perfmon event select MSR.

Package

MSR_C2_PMON_CTR5

Uncore C-box 2 perfmon counter MSR.

Package

MSR_C6_PMON_BOX_CTRL

Uncore C-box 6 perfmon local box control MSR.

Package

MSR_C6_PMON_BOX_STATUS

Uncore C-box 6 perfmon local box status MSR.

Package

MSR_C6_PMON_BOX_OVF_CTRL

Uncore C-box 6 perfmon local box overflow control MSR.

Package

MSR_C6_PMON_EVNT_SEL0

Uncore C-box 6 perfmon event select MSR.

Package

MSR_C6_PMON_CTR0

Uncore C-box 6 perfmon counter MSR.

Package

MSR_C6_PMON_EVNT_SEL1

Uncore C-box 6 perfmon event select MSR.

Package

MSR_C6_PMON_CTR1

Uncore C-box 6 perfmon counter MSR.

Package

MSR_C6_PMON_EVNT_SEL2

Uncore C-box 6 perfmon event select MSR.

Package

MSR_C6_PMON_CTR2

Uncore C-box 6 perfmon counter MSR.

Package

MSR_C6_PMON_EVNT_SEL3

Uncore C-box 6 perfmon event select MSR.

Package

MSR_C6_PMON_CTR3

Uncore C-box 6 perfmon counter MSR.

Package

MSR_C6_PMON_EVNT_SEL4

Uncore C-box 6 perfmon event select MSR.

Package

2-184 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

MSR_C6_PMON_CTR4

Uncore C-box 6 perfmon counter MSR.

Package

MSR_C6_PMON_EVNT_SEL5

Uncore C-box 6 perfmon event select MSR.

Package

MSR_C6_PMON_CTR5

Uncore C-box 6 perfmon counter MSR.

Package

MSR_C1_PMON_BOX_CTRL

Uncore C-box 1 perfmon local box control MSR.

Package

MSR_C1_PMON_BOX_STATUS

Uncore C-box 1 perfmon local box status MSR.

Package

MSR_C1_PMON_BOX_OVF_CTRL

Uncore C-box 1 perfmon local box overflow control MSR.

Package

MSR_C1_PMON_EVNT_SEL0

Uncore C-box 1 perfmon event select MSR.

Package

MSR_C1_PMON_CTR0

Uncore C-box 1 perfmon counter MSR.

Package

MSR_C1_PMON_EVNT_SEL1

Uncore C-box 1 perfmon event select MSR.

Package

MSR_C1_PMON_CTR1

Uncore C-box 1 perfmon counter MSR.

Package

MSR_C1_PMON_EVNT_SEL2

Uncore C-box 1 perfmon event select MSR.

Package

MSR_C1_PMON_CTR2

Uncore C-box 1 perfmon counter MSR.

Package

MSR_C1_PMON_EVNT_SEL3

Uncore C-box 1 perfmon event select MSR.

Package

MSR_C1_PMON_CTR3

Uncore C-box 1 perfmon counter MSR.

Package

MSR_C1_PMON_EVNT_SEL4

Uncore C-box 1 perfmon event select MSR.

Package

MSR_C1_PMON_CTR4

Uncore C-box 1 perfmon counter MSR.

Package

MSR_C1_PMON_EVNT_SEL5

Uncore C-box 1 perfmon event select MSR.

Package

MSR_C1_PMON_CTR5

Uncore C-box 1 perfmon counter MSR.

Package

MSR_C5_PMON_BOX_CTRL

Vol. 4

2-185

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

Uncore C-box 5 perfmon local box control MSR.

Package

MSR_C5_PMON_BOX_STATUS

Uncore C-box 5 perfmon local box status MSR.

Package

MSR_C5_PMON_BOX_OVF_CTRL

Uncore C-box 5 perfmon local box overflow control MSR.

Package

MSR_C5_PMON_EVNT_SEL0

Uncore C-box 5 perfmon event select MSR.

Package

MSR_C5_PMON_CTR0

Uncore C-box 5 perfmon counter MSR.

Package

MSR_C5_PMON_EVNT_SEL1

Uncore C-box 5 perfmon event select MSR.

Package

MSR_C5_PMON_CTR1

Uncore C-box 5 perfmon counter MSR.

Package

MSR_C5_PMON_EVNT_SEL2

Uncore C-box 5 perfmon event select MSR.

Package

MSR_C5_PMON_CTR2

Uncore C-box 5 perfmon counter MSR.

Package

MSR_C5_PMON_EVNT_SEL3

Uncore C-box 5 perfmon event select MSR.

Package

MSR_C5_PMON_CTR3

Uncore C-box 5 perfmon counter MSR.

Package

MSR_C5_PMON_EVNT_SEL4

Uncore C-box 5 perfmon event select MSR.

Package

MSR_C5_PMON_CTR4

Uncore C-box 5 perfmon counter MSR.

Package

MSR_C5_PMON_EVNT_SEL5

Uncore C-box 5 perfmon event select MSR.

Package

MSR_C5_PMON_CTR5

Uncore C-box 5 perfmon counter MSR.

Package

MSR_C3_PMON_BOX_CTRL

Uncore C-box 3 perfmon local box control MSR.

Package

MSR_C3_PMON_BOX_STATUS

Uncore C-box 3 perfmon local box status MSR.

Package

MSR_C3_PMON_BOX_OVF_CTRL

Uncore C-box 3 perfmon local box overflow control MSR.

Package

MSR_C3_PMON_EVNT_SEL0

Uncore C-box 3 perfmon event select MSR.

Package

2-186 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

MSR_C3_PMON_CTR0

Uncore C-box 3 perfmon counter MSR.

Package

MSR_C3_PMON_EVNT_SEL1

Uncore C-box 3 perfmon event select MSR.

Package

MSR_C3_PMON_CTR1

Uncore C-box 3 perfmon counter MSR.

Package

MSR_C3_PMON_EVNT_SEL2

Uncore C-box 3 perfmon event select MSR.

Package

MSR_C3_PMON_CTR2

Uncore C-box 3 perfmon counter MSR.

Package

MSR_C3_PMON_EVNT_SEL3

Uncore C-box 3 perfmon event select MSR.

Package

MSR_C3_PMON_CTR3

Uncore C-box 3 perfmon counter MSR.

Package

MSR_C3_PMON_EVNT_SEL4

Uncore C-box 3 perfmon event select MSR.

Package

MSR_C3_PMON_CTR4

Uncore C-box 3 perfmon counter MSR.

Package

MSR_C3_PMON_EVNT_SEL5

Uncore C-box 3 perfmon event select MSR.

Package

MSR_C3_PMON_CTR5

Uncore C-box 3 perfmon counter MSR.

Package

MSR_C7_PMON_BOX_CTRL

Uncore C-box 7 perfmon local box control MSR.

Package

MSR_C7_PMON_BOX_STATUS

Uncore C-box 7 perfmon local box status MSR.

Package

MSR_C7_PMON_BOX_OVF_CTRL

Uncore C-box 7 perfmon local box overflow control MSR.

Package

MSR_C7_PMON_EVNT_SEL0

Uncore C-box 7 perfmon event select MSR.

Package

MSR_C7_PMON_CTR0

Uncore C-box 7 perfmon counter MSR.

Package

MSR_C7_PMON_EVNT_SEL1

Uncore C-box 7 perfmon event select MSR.

Package

MSR_C7_PMON_CTR1

Uncore C-box 7 perfmon counter MSR.

Package

MSR_C7_PMON_EVNT_SEL2

Vol. 4

2-187

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

Uncore C-box 7 perfmon event select MSR.

Package

MSR_C7_PMON_CTR2

Uncore C-box 7 perfmon counter MSR.

Package

MSR_C7_PMON_EVNT_SEL3

Uncore C-box 7 perfmon event select MSR.

Package

MSR_C7_PMON_CTR3

Uncore C-box 7 perfmon counter MSR.

Package

MSR_C7_PMON_EVNT_SEL4

Uncore C-box 7 perfmon event select MSR.

Package

MSR_C7_PMON_CTR4

Uncore C-box 7 perfmon counter MSR.

Package

MSR_C7_PMON_EVNT_SEL5

Uncore C-box 7 perfmon event select MSR.

Package

MSR_C7_PMON_CTR5

Uncore C-box 7 perfmon counter MSR.

Package

MSR_R0_PMON_BOX_CTRL

Uncore R-box 0 perfmon local box control MSR.

Package

MSR_R0_PMON_BOX_STATUS

Uncore R-box 0 perfmon local box status MSR.

Package

MSR_R0_PMON_BOX_OVF_CTRL

Uncore R-box 0 perfmon local box overflow control MSR.

Package

MSR_R0_PMON_IPERF0_P0

Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.

Package

MSR_R0_PMON_IPERF0_P1

Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.

Package

MSR_R0_PMON_IPERF0_P2

Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.

Package

MSR_R0_PMON_IPERF0_P3

Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.

Package

MSR_R0_PMON_IPERF0_P4

Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.

Package

MSR_R0_PMON_IPERF0_P5

Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.

Package

MSR_R0_PMON_IPERF0_P6

Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.

Package

MSR_R0_PMON_IPERF0_P7

Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.

Package

2-188 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

MSR_R0_PMON_QLX_P0

Uncore R-box 0 perfmon QLX unit Port 0 select MSR.

Package

MSR_R0_PMON_QLX_P1

Uncore R-box 0 perfmon QLX unit Port 1 select MSR.

Package

MSR_R0_PMON_QLX_P2

Uncore R-box 0 perfmon QLX unit Port 2 select MSR.

Package

MSR_R0_PMON_QLX_P3

Uncore R-box 0 perfmon QLX unit Port 3 select MSR.

Package

MSR_R0_PMON_EVNT_SEL0

Uncore R-box 0 perfmon event select MSR.

Package

MSR_R0_PMON_CTR0

Uncore R-box 0 perfmon counter MSR.

Package

MSR_R0_PMON_EVNT_SEL1

Uncore R-box 0 perfmon event select MSR.

Package

MSR_R0_PMON_CTR1

Uncore R-box 0 perfmon counter MSR.

Package

MSR_R0_PMON_EVNT_SEL2

Uncore R-box 0 perfmon event select MSR.

Package

MSR_R0_PMON_CTR2

Uncore R-box 0 perfmon counter MSR.

Package

MSR_R0_PMON_EVNT_SEL3

Uncore R-box 0 perfmon event select MSR.

Package

MSR_R0_PMON_CTR3

Uncore R-box 0 perfmon counter MSR.

Package

MSR_R0_PMON_EVNT_SEL4

Uncore R-box 0 perfmon event select MSR.

Package

MSR_R0_PMON_CTR4

Uncore R-box 0 perfmon counter MSR.

Package

MSR_R0_PMON_EVNT_SEL5

Uncore R-box 0 perfmon event select MSR.

Package

MSR_R0_PMON_CTR5

Uncore R-box 0 perfmon counter MSR.

Package

MSR_R0_PMON_EVNT_SEL6

Uncore R-box 0 perfmon event select MSR.

Package

MSR_R0_PMON_CTR6

Uncore R-box 0 perfmon counter MSR.

Package

MSR_R0_PMON_EVNT_SEL7

Vol. 4

2-189

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

Uncore R-box 0 perfmon event select MSR.

Package

MSR_R0_PMON_CTR7

Uncore R-box 0 perfmon counter MSR.

Package

MSR_R1_PMON_BOX_CTRL

Uncore R-box 1 perfmon local box control MSR.

Package

MSR_R1_PMON_BOX_STATUS

Uncore R-box 1 perfmon local box status MSR.

Package

MSR_R1_PMON_BOX_OVF_CTRL

Uncore R-box 1 perfmon local box overflow control MSR.

Package

MSR_R1_PMON_IPERF1_P8

Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.

Package

MSR_R1_PMON_IPERF1_P9

Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.

Package

MSR_R1_PMON_IPERF1_P10

Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.

Package

MSR_R1_PMON_IPERF1_P11

Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.

Package

MSR_R1_PMON_IPERF1_P12

Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.

Package

MSR_R1_PMON_IPERF1_P13

Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.

Package

MSR_R1_PMON_IPERF1_P14

Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.

Package

MSR_R1_PMON_IPERF1_P15

Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.

Package

MSR_R1_PMON_QLX_P4

Uncore R-box 1 perfmon QLX unit Port 4 select MSR.

Package

MSR_R1_PMON_QLX_P5

Uncore R-box 1 perfmon QLX unit Port 5 select MSR.

Package

MSR_R1_PMON_QLX_P6

Uncore R-box 1 perfmon QLX unit Port 6 select MSR.

Package

MSR_R1_PMON_QLX_P7

Uncore R-box 1 perfmon QLX unit Port 7 select MSR.

Package

MSR_R1_PMON_EVNT_SEL8

Uncore R-box 1 perfmon event select MSR.

Package

MSR_R1_PMON_CTR8

Uncore R-box 1 perfmon counter MSR.

Package

2-190 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

MSR_R1_PMON_EVNT_SEL9

Uncore R-box 1 perfmon event select MSR.

Package

MSR_R1_PMON_CTR9

Uncore R-box 1 perfmon counter MSR.

Package

MSR_R1_PMON_EVNT_SEL10

Uncore R-box 1 perfmon event select MSR.

Package

MSR_R1_PMON_CTR10

Uncore R-box 1 perfmon counter MSR.

Package

MSR_R1_PMON_EVNT_SEL11

Uncore R-box 1 perfmon event select MSR.

Package

MSR_R1_PMON_CTR11

Uncore R-box 1 perfmon counter MSR.

Package

MSR_R1_PMON_EVNT_SEL12

Uncore R-box 1 perfmon event select MSR.

Package

MSR_R1_PMON_CTR12

Uncore R-box 1 perfmon counter MSR.

Package

MSR_R1_PMON_EVNT_SEL13

Uncore R-box 1 perfmon event select MSR.

Package

MSR_R1_PMON_CTR13

Uncore R-box 1perfmon counter MSR.

Package

MSR_R1_PMON_EVNT_SEL14

Uncore R-box 1 perfmon event select MSR.

Package

MSR_R1_PMON_CTR14

Uncore R-box 1 perfmon counter MSR.

Package

MSR_R1_PMON_EVNT_SEL15

Uncore R-box 1 perfmon event select MSR.

Package

MSR_R1_PMON_CTR15

Uncore R-box 1 perfmon counter MSR.

Package

MSR_B0_PMON_MATCH

Uncore B-box 0 perfmon local box match MSR.

Package

MSR_B0_PMON_MASK

Uncore B-box 0 perfmon local box mask MSR.

Package

MSR_S0_PMON_MATCH

Uncore S-box 0 perfmon local box match MSR.

Package

MSR_S0_PMON_MASK

Uncore S-box 0 perfmon local box mask MSR.

Package

MSR_B1_PMON_MATCH

Vol. 4

2-191

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)

Bit Description

Scope

Uncore B-box 1 perfmon local box match MSR.

Package

MSR_B1_PMON_MASK

Uncore B-box 1 perfmon local box mask MSR.

Package

MSR_M0_PMON_MM_CONFIG

Uncore M-box 0 perfmon local box address match/mask config MSR.

Package

MSR_M0_PMON_ADDR_MATCH

Uncore M-box 0 perfmon local box address match MSR.

Package

MSR_M0_PMON_ADDR_MASK

Uncore M-box 0 perfmon local box address mask MSR.

Package

MSR_S1_PMON_MATCH

Uncore S-box 1 perfmon local box match MSR.

Package

MSR_S1_PMON_MASK

Uncore S-box 1 perfmon local box mask MSR.

Package

MSR_M1_PMON_MM_CONFIG

Uncore M-box 1 perfmon local box address match/mask config MSR.

Package

MSR_M1_PMON_ADDR_MATCH

Uncore M-box 1 perfmon local box address match MSR.

Package

MSR_M1_PMON_ADDR_MASK

Uncore M-box 1 perfmon local box address mask MSR.

Package

MSR_UNCORE_PMC5

See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.”

Package

2.9

MSRS IN THE INTEL® XEON® PROCESSOR 5600 SERIES BASED ON

WESTMERE MICROARCHITECTURE

The Intel^® Xeon^® Processor 5600 Series is based on Westmere microarchitecture and supports the MSR interfaces

listed in Table 2-15, Table 2-16, plus additional MSRs listed in Table 2-18. These MSRs apply to the Intel Core i7, i5,

and i3 processor family with a CPUID Signature DisplayFamily_DisplayModel value of 06_25H or 06_2CH; see Table

2-1.

Table 2-18. Additional MSRs Supported by Intel® Processors Based on Westmere Microarchitecture

Bit Description

Scope

MSR_FEATURE_CONFIG

AES Configuration (RW-L)

Core

Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR.

2-192 Vol. 4

MODEL-SPECIFIC REGISTERS (MSRS)

Table 2-18. Additional MSRs Supported by Intel® Processors Based on Westmere Microarchitecture (Contd.)

Bit Description

Scope

1:0

AES Configuration (RW-L)

Upon a successful read of this MSR, the configuration of AES instruction

set availability is as follows:

11b: AES instructions are not available until next RESET.

Otherwise, AES instructions are available.

Note, AES instruction set is not available if read is unsuccessful. If the

configuration is not 01b, AES instructions can be mis-configured if a

privileged agent unintentionally writes 11b.

63:2

Reserved.

MSR_OFFCORE_RSP_1

Offcore Response Event Select Register (R/W)

Thread

MSR_TURBO_RATIO_LIMIT

Maximum Ratio Limit of Turbo Mode

Package

R/O if MSR_PLATFORM_INFO.[28] = 0.

R/W if MSR_PLATFORM_INFO.[28] = 1.

7:0

Maximum Ratio Limit for 1C

Package

Maximum turbo ratio limit of 1 core active.

15:8

Maximum Ratio Limit for 2C

Package

Maximum turbo ratio limit of 2 core active.