Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

EARLIER GENERATIONS OF INTEL ATOM® MICROARCHITECTURE AND SOFTWARE OPTIMIZATION

Table 6-19. Instructions Latency and Throughput Recent Microarchitectures for Intel Atom® Processors (Contd.)

Instruction

Throughput

Latency

MSROM

06_5CH,

06_37H,

06_5CH,

06_37H,

06_5CH

06_37H,

5FH,

4AH,4CH

5FH,

4AH,4CH,

,5FH,

4AH,4C

7AH

,4DH,5A

7AH

4DH,5AH,

7AH

H,4DH,5

H,5DH

5DH

AH,5DH

ADD/AND/CMP/OR/SUB/XOR/TEST r32, r32

0.33

0.5

ADD/AND/CMP/OR/SUB/XOR/TEST r64, r64

0.33

0.5

ADDPD/ADDSUBPD/MAXPD/MINPD/SUBPD xmm,

xmm

ADDPS/ADDSD/ADDSS/ADDSUBPS/SUBPS/SUBSD/

SUBSS

MAXPS/MAXSD/MAXSS/MINPS/MINSD/MINSS

xmm, xmm

ANDNPD/ANDNPS/ANDPD/ANDPS/ORPD/ORPS/XO

0.5

RPD/XORPS

AESDEC/AESDECLAST/AESENC/AESENCLAST

1 (GLP)

4 (GLP)

AESIMC/AESKEYGEN

1 (GLP)

4 (GLP)

BLENDPD/BLENDPS xmm, xmm, imm8

0.5

BLENDVPD/BLENDVPS xmm, xmm

BSF/BSR r32, r32

BSWAP r32

BT/BTC/BTR/BTS r32, r32

CBW

CDQ/CLC/CMC

CMOVxx r32; r32

CMPPD xmm, xmm, imm

CMPSD/CMPPS/CMPSS xmm, xmm, imm

CMPXCHG r32, r32

CMPXCHG r64, r64

(U)COMISD/(U)COMISS xmm, xmm;

CPUID

CRC32 r32, r32

CRC32 r64, r64

CVTDQ2PD/CVTDQ2PS/CVTPD2DQ/CVTPD2PS

xmm, xmm

CVT(T)PD2PI/CVT(T)PI2PD

CVT(T)PS2DQ/CVTPS2PD xmm, xmm;

CVT(T)SD2SS/CVTSS2SD xmm, xmm

CVTSI2SD/SS xmm, r32

CVTSD2SI/SS2SI r32, xmm

DEC/INC r32

Ref#: 248966-048

6-43

EARLIER GENERATIONS OF INTEL ATOM® MICROARCHITECTURE AND SOFTWARE OPTIMIZATION

Table 6-19. Instructions Latency and Throughput Recent Microarchitectures for Intel Atom® Processors (Contd.)

Instruction

Throughput

Latency

MSROM

06_5CH,

06_37H,

06_5CH,

06_37H,

06_5CH

06_37H,

5FH,

4AH,4CH

5FH,

4AH,4CH,

,5FH,

4AH,4C

7AH

,4DH,5A

7AH

4DH,5AH,

7AH

H,4DH,5

H,5DH

5DH

AH,5DH

DIV r8

11-12

DIV r16

12-17

26-30

12-17

26-30

DIV r32

12-25

26-38

12-25

26-38

DIV r64

12-41

38-123

12-41

38-123

DIVPD¹

12, 65

27-69

13, 66

27-69

18 (GLP)

22 (GLP)

DIVPS¹

12,35

27-39

13, 36

27-39

12 (GLP)

16 (GLP)

DIVSD¹

12,33

11-32

13,34

13-34

10 (GLP)

14 (GLP)

DIVSS¹

12,18

11-17

13,19

13-19

7 (GLP)

11 (GLP)

DPPD xmm, xmm, imm

DPPS xmm, xmm, imm

EMMS

EXTRACTPS

F2XM1

FABS/FCHS

0.5

FCOM

FADD/FSUB

FCOS

154

168

154

168

FDECSTP/FINCSTP

0.5

FDIV

11 (EP

15 (EP

GLP)

FLDZ

280

277

280

277

FMUL

FPATAN/FYL2X/FYL2XP1

303

296

303

296

FPTAN/FSINCOS

287

281

287

281

FRNDINT

FSCALE

FSIN

140

150

140

150

FSQRT

HADDPD/HSUBPD xmm, xmm

HADDPS/HSUBPS xmm, xmm

IDIV r8

11-12

IDIV r16

12-17

35-40

12-17

35-40

Ref#: 248966-048

6-44

EARLIER GENERATIONS OF INTEL ATOM® MICROARCHITECTURE AND SOFTWARE OPTIMIZATION

Table 6-19. Instructions Latency and Throughput Recent Microarchitectures for Intel Atom® Processors (Contd.)

Instruction

Throughput

Latency

MSROM

06_5CH,

06_37H,

06_5CH,

06_37H,

06_5CH

06_37H,

5FH,

4AH,4CH

5FH,

4AH,4CH,

,5FH,

4AH,4C

7AH

,4DH,5A

7AH

4DH,5AH,

7AH

H,4DH,5

H,5DH

5DH

AH,5DH

IDIV r32

12-25

35-47

12-25

35-47

IDIV r64

12-41

49-135

12-41

49-135

IMUL r32, r32 (single dest)

IMUL r32 (dual dest)

3 (4, EDX)

IMUL r64, r64 (single dest)

IMUL r64 (dual dest)

5 (6,RDX)

5 (7,RDX)

INSERTPS

0.5

MASKMOVDQU

MOVAPD/MOVAPS/MOVDQA/MOVDQU/MOVUPD/M

0.33²/0.

0.5

0/1

OVUPS xmm, xmm;

MOVD r32, xmm; MOVQ r64, xmm

MOVD xmm, r32 ; MOVQ xmm, r64

MOVDDUP/MOVHLPS/MOVLHPS/MOVSHDUP/MOV

0.5

SLDUP

MOVDQ2Q/MOVQ/MOVQ2DQ

0.5

MOVSD/MOVSS xmm, xmm;

0.5

MPSADBW

MULPD

MULPS; MULSD

MULSS

NEG/NOT r32

0.33

0.5

PACKSSDW/WB xmm, xmm; PACKUSWB xmm, xmm

0.5

PABSB/D/W xmm, xmm

0.5

PADDB/D/W xmm, xmm; PSUBB/D/W xmm, xmm

0.5

PADDQ/PSUBQ/PCMPEQQ xmm, xmm

PADDSB/W; PADDUSB/W; PSUBSB/W; PSUBUSB/W

0.5

PALIGNR xmm, xmm

0.5

PAND/PANDN/POR/PXOR xmm, xmm

0.5

PAVGB/W xmm, xmm

0.5

PBLENDW xmm, xmm, imm

0.5

PBLENDVB xmm, xmm

PCLMULQDQ xmm, xmm, imm

PCMPEQB/D/W xmm, xmm

0.5

PCMPESTRI xmm, xmm, imm

19(C)/

21(C)/

26(F)3

28(F)

PCMPESTRM xmm, xmm, imm

15(X)/

17(X)/

25(F)1

24(F)

Ref#: 248966-048

6-45

EARLIER GENERATIONS OF INTEL ATOM® MICROARCHITECTURE AND SOFTWARE OPTIMIZATION

Table 6-19. Instructions Latency and Throughput Recent Microarchitectures for Intel Atom® Processors (Contd.)

Instruction

Throughput

Latency

MSROM

06_5CH,

06_37H,

06_5CH,

06_37H,

06_5CH

06_37H,

5FH,

4AH,4CH

5FH,

4AH,4CH,

,5FH,

4AH,4C

7AH

,4DH,5A

7AH

4DH,5AH,

7AH

H,4DH,5

H,5DH

5DH

AH,5DH

PCMPGTB/D/W xmm, xmm

0.5

PCMPGTQ/PHMINPOSUW xmm, xmm

PCMPISTRI xmm, xmm, imm

14(C)/

17(C)/

21(F)1

24(F)

PCMPISTRM xmm, xmm, imm

10(X)/

13(X)/

20(F)1

20(F)

PEXTRB/WD r32, xmm, imm

PINSRB/WD xmm, r32, imm

PHADDD/PHSUBD xmm, xmm

PHADDW/PHADDSW xmm, xmm

PHSUBW/PHSUBSW xmm, xmm

PMADDUBSW/PMADDWD/PMULHRSW/PSADBW

xmm, xmm

PMAXSB/W/D xmm, xmm; PMAXUB/W/D xmm,

0.5

xmm

PMINSB/W/D xmm, xmm; PMINUB/W/D xmm, xmm

0.5

PMOVMSKB r32, xmm

PMOVSXBW/BD/BQ/WD/WQ/DQ xmm, xmm

0.5

PMOVZXBW/BD/BQ/WD/WQ/DQ xmm, xmm

0.5

PMULDQ/PMULUDQ xmm, xmm

PMULHUW/PMULHW/PMULLW xmm, xmm

PMULLD xmm, xmm

POPCNT r32, r32

POPCNT r64, r64

PSHUFB xmm, xmm

PSHUFD xmm, mem, imm

0.5

PSHUFHW; PSHUFLW; PSHUFW

0.5

PSIGNB/D/W xmm, xmm

0.5

PSLLDQ/PSRLDQ xmm, imm; SHUFPD/SHUFPS

0.5

PSLLD/Q/W xmm, xmm

PSRAD/W xmm, imm;

0.5

PSRAD/W xmm, xmm;

PSRLD/Q/W xmm, imm;

0.5

PSRLD/Q/W xmm, xmm

PTEST xmm, xmm

PUNPCKHBW/DQ/WD; PUNPCKLBW/DQ/WD

0.5

PUNPCKHQDQ; PUNPCKLQDQ

0.5

Ref#: 248966-048

6-46

EARLIER GENERATIONS OF INTEL ATOM® MICROARCHITECTURE AND SOFTWARE OPTIMIZATION

Table 6-19. Instructions Latency and Throughput Recent Microarchitectures for Intel Atom® Processors (Contd.)

Instruction

Throughput

Latency

MSROM

06_5CH,

06_37H,

06_5CH,

06_37H,

06_5CH

06_37H,

5FH,

4AH,4CH

5FH,

4AH,4CH,

,5FH,

4AH,4C

7AH

,4DH,5A

7AH

4DH,5AH,

7AH

H,4DH,5

H,5DH

5DH

AH,5DH

RCPPS/RSQRTPS

RCPSS/RSQRTSS

RDTSC

ROUNDPD/PS

ROUNDSD/SS

ROL; ROR; SAL; SAR; SHL; SHR ( count in CL)

1 (2 for

1 (2 for CL

source)

ROL; ROR; SAL; SAR; SHL; SHR ( count in imm8)

SAHF

SHLD r32, r32, imm

SHRD r32, r32, imm

SHLD/SHRD r64, r64, imm

SHLD/SHRD r64, r64, CL

SHLD/SHRD r32, r32, CL

SHUFPD/SHUFPS xmm, xmm, imm

0.5

SQRTPD

26 (GLP)

30 (GLP)

SQRTPS

14 (GLP)

18 (GLP)

SQRTSD

14 (GLP)

18 (GLP)

SQRTSS

8 (GLP)

12 (GLP)

TEST r32, r32

0.33

0.5

UNPCKHPD; UNPCKHPS; UNPCKLPD, UNPCKLPS

0.5

XADD r32, r32

XCHG r32, r32

XCHG r64, r64

SHA1MSG1/SHA1MSG2/SHA1NEXTE

SHA1RNDS4 xmm, xmm, imm

SHA256MSG1/SHA256MSG2

SHA256RNDS2

NOTES:

1. DIVPD/DIVPS/DIVSD/DIVSS list early-exit value first and common-case value second. Early-exit case applies to a special

input value such as QNAN. Common case applies to normal numeric values.

2. Throughput is 0.33 cycles if move elimination is effect, otherwise 0.5 cycle.

3. Latency values are for ECX/EFLAGS/XMM0 dependency: (C/F/X)

Ref#: 248966-048

6-47

CHAPTER 7

INSTRUCTION LATENCY AND THROUGHPUT

NOTE

All recent processors have latency and throughput information posted on the Intel® 64

and IA-32 Architectures Software Developer Manuals Page.

This appendix contains tables showing the latency and throughput are associated with commonly used

instructions¹. The instruction timing data varies across processors family/models. It contains the

following sections:

• Chapter 7.1, “Overview” — Provides an overview of issues related to instruction selection and

scheduling.

• Chapter 7.2, “Definitions” — Presents definitions.

• Chapter 7.3, “Latency and Throughput” — Lists instruction throughput, latency associated with

commonly-used instructions.

7.1

OVERVIEW

This appendix provides information to assembly language programmers and compiler writers. The infor-

mation aids in the selection of instruction sequences (to minimize chain latency) and in the arrangement

of instructions (assists in hardware processing). The performance impact of applying the information has

been shown to be on the order of several percent. This is for applications not dominated by other perfor-

mance factors, such as:

• Cache miss latencies.

• Bus bandwidth.

• I/O bandwidth.

Instruction selection and scheduling matters when the programmer has already addressed the perfor-

mance issues discussed in Chapter 2:

• Observe store forwarding restrictions.

• Avoid cache line and memory order buffer splits.

• Do not inhibit branch prediction.

• Minimize the use of xchg instructions on memory locations.

While several items on the above list involve selecting the right instruction, this appendix focuses on the

following issues. These are listed in priority order, though which item contributes most to performance

varies by application:

• Maximize the flow of ops into the execution core. Instructions which consist of more than four ops

require additional steps from microcode ROM. Instructions with longer micro-op flows incur a delay

in the front end and reduce the supply of micro-ops to the execution core.

In Pentium 4 and Intel Xeon processors, transfers to microcode ROM often reduce how efficiently

ops can be packed into the trace cache. Where possible, it is advisable to select instructions with

four or fewer ops. For example, a 32-bit integer multiply with a memory operand fits in the trace

cache without going to microcode, while a 16-bit integer multiply to memory does not.

1. Although instruction latency may be useful in some limited situations (e.g., a tight loop with a dependency chain that

exposes instruction latency), software optimization on super-scalar, out-of-order microarchitecture, in general, will ben-

efit much more on increasing the effective throughput of the larger-scale code path. Coding techniques that rely on

instruction latency alone to influence the scheduling of instruction is likely to be sub-optimal as such coding technique is

likely to interfere with the out-of-order machine or restrict the amount of instruction-level parallelism.

INSTRUCTION LATENCY AND THROUGHPUT

• Avoid resource conflicts. Interleaving instructions so that they don’t compete for the same port or

execution unit can increase throughput. For example, alternate PADDQ and PMULUDQ (each has a

throughput of one issue per two clock cycles). When interleaved, they can achieve an effective

throughput of one instruction per cycle because they use the same port but different execution units.

Selecting instructions with fast throughput also helps to preserve issue port bandwidth, hide latency

and allows for higher software performance.

• Minimize the latency of dependency chains that are on the critical path. For example, an operation to

shift left by two bits executes faster when encoded as two adds than when it is encoded as a shift. If

latency is not an issue, the shift results in a denser byte encoding.

In addition to the general and specific rules, coding guidelines and the instruction data provided in this

manual, you can take advantage of the software performance analysis and tuning toolset available at

http://developer.intel.com/software/products/index.htm. The tools include the Intel VTune Performance

Analyzer, with its performance-monitoring capabilities.

7.2

DEFINITIONS

The data is listed in several tables. The tables contain the following:

• Instruction Name — The assembly mnemonic of each instruction.

• Latency — The number of clock cycles that are required for the execution core to complete the

execution of all of the ops that form an instruction.

• Throughput — The number of clock cycles required to wait before the issue ports are free to accept

the same instruction again. For many instructions, the throughput of an instruction can be signifi-

cantly less than its latency.

• The case of RDRAND instruction latency and throughput is an exception to the definitions above,

because the hardware facility that executes the RDRAND instruction resides in the uncore and is

shared by all processor cores and logical processors in a physical package. The software observable

latency and throughput using the sequence of “rdrand followby jnc” in a single-thread scenario can

be as low as ~100 cycles. In third generation Intel Core processors based on Ivy Bridge microarchi-

tecture, the total bandwidth to deliver random numbers via RDRAND by the uncore is about 500

MBytes/sec. Within the same processor core microarchitecture and different uncore implementa-

tions, RDRAND latency/throughput can vary across Intel Core and Intel Xeon processors.

7.3

LATENCY AND THROUGHPUT

This section presents the latency and throughput information for commonly-used instructions including:

MMX technology, Streaming SIMD Extensions, subsequent generations of SIMD instruction extensions,

and most of the frequently used general-purpose integer and x87 floating-point instructions.

Due to the complexity of dynamic execution and out-of-order nature of the execution core, the instruc-

tion latency data may not be sufficient to accurately predict realistic performance of actual code

sequences based on adding instruction latency data.

• Instruction latency data is useful when tuning a dependency chain. However, dependency chains limit

the out-of-order core’s ability to execute micro-ops in parallel. Instruction throughput data are useful

when tuning parallel code unencumbered by dependency chains.

• Numeric data in the tables is:

— Approximate and subject to change in future implementations of the microarchitecture.

— Not meant to be used as reference for instruction-level performance benchmarks. Comparison of

instruction-level performance of microprocessors that are based on different microarchitectures

is a complex subject and requires information that is beyond the scope of this manual.

Comparisons of latency and throughput data between different microarchitectures can be misleading.

Chapter 7.3.1 provides latency and throughput data for the register-to-register instruction type.

7-2

INSTRUCTION LATENCY AND THROUGHPUT

Chapter 7.3.3 discusses how to adjust latency and throughput specifications for the register-to-memory

and memory-to-register instructions.

In some cases, the latency or throughput figures given are just one half of a clock. This occurs only for

the double-speed ALUs.

7.3.1

Latency and Throughput with Register Operands

Instruction latency and throughput data are presented in Table 7-4 through Table 7-18. Tables include

AESNI, SSE4.2, SSE4.1, Supplemental Streaming SIMD Extension 3, Streaming SIMD Extension 3,

Streaming SIMD Extension 2, Streaming SIMD Extension, MMX technology and most common Intel 64

and IA-32 instructions. Instruction latency and throughput for different processor microarchitectures are

in separate columns.

Processor instruction timing data is implementation specific; it can vary between model encodings within

the same family encoding (e.g. model = 3 vs model < 2). Separate sets of instruction latency and

throughput are shown in the columns for CPUID signature 0xF2n and 0xF3n. The column represented by

0xF3n also applies to Intel processors with CPUID signature 0xF4n and 0xF6n. The notation 0xF2n

represents the hex value of the lower 12 bits of the EAX register reported by CPUID instruction with input

value of EAX = 1; ‘F’ indicates the family encoding value is 15, ‘2’ indicates the model encoding is 2, ‘n’

indicates it applies to any value in the stepping encoding.

Intel Core Solo and Intel Core Duo processors are represented by 06_0EH. Processors bases on 65 nm

Intel Core microarchitecture are represented by 06_0FH. Processors based on Enhanced Intel Core

microarchitecture are represented by 06_17H and 06_1DH. CPUID family/Model signatures of proces-

sors based on Nehalem microarchitecture are represented by 06_1AH, 06_1EH, 06_1FH, and 06_2EH.

Processors based on Westmere microarchitecture are represented by 06_25H, 06_2CH and 06_2FH.

Processors based on Sandy Bridge microarchitecture are represented by 06_2AH, 06_2DH. Processors

based on Ivy Bridge microarchitecture are represented by 06_3AH, 06_3EH. Processors based on

Haswell microarchitecture are represented by 06_3CH, 06_45H and 06_46H.

Table 7-1. CPUID Signature Values of Of Recent Intel Microarchitectures

DisplayFamily_DisplayModel

Recent Intel Microarchitectures

06_4EH, 06_5EH

Skylake microarchitecture

06_3DH, 06_47H, 06_56H

Broadwell microarchitecture

06_3CH, 06_45H, 06_46H, 06_3FH

Haswell microarchitecture

06_3AH, 06_3EH

Ivy Bridge microarchitecture

06_2AH, 06_2DH

Sandy Bridge microarchitecture

06_25H, 06_2CH, 06_2FH

Intel microarchitecture Westmere

06_1AH, 06_1EH, 06_1FH, 06_2EH

Intel microarchitecture Nehalem

06_17H, 06_1DH

Enhanced Intel Core microarchitecture

06_0FH

Intel Core microarchitecture

Instruction latency varies by microarchitectures. Table 7-2 lists SIMD extensions introduction in recent

microarchitectures. Each microarchitecture may be associated with more than one signature value given

by the CPUID’s “display_family” and “display_model”. Not all instruction set extensions are enabled in all

processors associated with a particular family/model designation. To determine whether a given

instruction set extension is supported, software must use the appropriate CPUID feature flag as

described in Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.

7-3

INSTRUCTION LATENCY AND THROUGHPUT

Table 7-2. Instruction Extensions Introduction by Microarchitectures (CPUID Signature)

SIMD Instruction

DisplayFamily_DisplayModel

Extensions

06_3CH,

06_1AH,

06_3DH,

06_25H,

06_4EH,

06_45H,

06_3AH,

06_2AH,

06_1EH,

06_17H,

06_47H,

06_2CH,

06_5EH

06_46H,

06_3EH

06_2DH

06_1FH,

06_1DH

06_56H

06_2FH

06_3FH

06_2EH

CLFLUSHOPT

Yes

ADX, RDSEED

Yes

AVX2, FMA, BMI1,

Yes

BMI2

F16C, RDRAND,

Yes

RWFSGSBASE

AVX

Yes

AESNI, PCLMULQDQ

Yes

SSE4.2, POPCNT

Yes

SSE4.1

Yes

SSSE3

Yes

SSE3

Yes

SSE2

Yes

SSE

Yes

MMX

Yes

Table 7-3. BMI1, BMI2 and General Purpose Instructions

Instruction

Latency¹

Throughput

06_3D,

06_3D, 06_47,

DisplayFamily_DisplayModel

06_4E, 06_5E

06_47, 06_56

06_56

ADCX

ADOX

RESEED

Similar to

RDRAND

7-4

INSTRUCTION LATENCY AND THROUGHPUT

Table 7-4. 256-bit Intel® AVX2 Instructions

Instruction

Latency¹

Throughput

06_3C,

06_3D,

06_4E,

06_45,

06_4E,

06_45,

DisplayFamily_DisplayModel

06_47,

06_5E

06_46,

06_5E

06_46,

06_56

06_3F

VEXTRACTI128 xmm1, ymm2, imm

VMPSADBW

VPACKUSDW/SSWB

VPADDB/D/W/Q

0.33

0.5

VPADDSB

0.5

VPADDUSB

0.5

VPALIGNR

VPAVGB

0.5

VPBLENDD

0.33

VPBLENDW

VPBLENDVB

VPBROADCASTB/D/SS/SD

VPCMPEQB/W/D

0.5

VPCMPEQQ

0.5

VPCMPGTQ

VPHADDW/D/SW

VINSERTI128 ymm1, ymm2, xmm, imm

VPMADDWD

5^b

0.5

VPMADDUBSW

5^b

0.5

VPMAXSD

0.5

VPMAXUD

0.5

VPMOVSX

VPMOVZX

VPMULDQ/UDQ

5^b

0.5

VPMULHRSW

5^b

0.5

VPMULHW/LW

5^b

0.5

VPMULLD

10^b

VPOR/VPXOR

0.33

VPSADBW

VPSHUFB

VPSHUFD

VPSHUFLW/HW

VPSIGNB/D/W/Q

0.5

VPERMD/PS

VPSLLVD/Q

0.5

7-5

INSTRUCTION LATENCY AND THROUGHPUT

Table 7-4. 256-bit Intel® AVX2 Instructions (Contd.)

Instruction

Latency¹

Throughput

06_3C,

06_3D,

06_4E,

06_45,

06_4E,

06_45,

DisplayFamily_DisplayModel

06_47,

06_5E

06_46,

06_5E

06_46,

06_56

06_3F

VPSRAVD

0.5

VPSRAD/W ymm1, ymm2, imm8

VPSLLDQ ymm1, ymm2, imm8

VPSLLQ/D/W ymm1, ymm2, imm8

VPSLLQ/D/W ymm, ymm, ymm

VPUNPCKHBW/WD/DQ/QDQ

VPUNPCKLBW/WD/DQ/QDQ

ALL VFMA

0.5

VPMASKMOVD/Q mem, ymm^d, ymm

VPMASKMOVD/Q NUL, msk_0, ymm

>200^e

VPMASKMOVD/Q ymm, ymm^d, mem

VPMASKMOVD/Q ymm, msk_0, [base+index]^f

>200

~200

>200

~200

b: includes 1-cycle bubble due to bypass.

c: includes two 1-cycle bubbles due to bypass

d: MASKMOV instruction timing measured with L1 reference and mask register selecting at least 1 or more elements.

e: MASKMOV store instruction with a mask value selecting 0 elements and illegal address (NUL or non-NUL) incurs delay

due to assist.

f: MASKMOV Load instruction with a mask value selecting 0 elements and certain addressing forms incur delay due to

assist.

Table 7-5. Gather Timing Data from L1D*

Instruction

Latency¹

Throughput

06_3D,

06_4E,

06_3C/45/

06_4E,

06_3C/45/

DisplayFamily_DisplayModel

06_47,

06_5E

46/3F

06_5E

46/3F

06_56

VPGATHERDD/PS xmm, [vi128], xmm

~20

~17

~14

VPGATHERQQ/PD xmm, [vi128], xmm

~18

~15

~12

VPGATHERDD/PS ymm, [vi256], ymm

~22

~19

~20

~10

VPGATHERQQ/PD ymm, [vi256], ymm

~20

~16

~15

* Gather Instructions fetch data elements via memory references. The timing data shown applies to memory references

that reside within the L1 data cache and all mask elements selected

7-6

INSTRUCTION LATENCY AND THROUGHPUT

Table 7-6. BMI1, BMI2 and General Purpose Instructions

Instruction

Latency¹

Throughput

06_3D,

06_4E,

06_3C/45

06_4E,

06_3C/45

DisplayFamily_DisplayModel

06_47,

06_5E

/46/3F

06_5E

/46/3F

06_56

ANDN

0.5

BEXTR

0.5

BLSI/BLSMSK/BLSR

0.5

BZHI

0.5

MULX r64, r64, r64

PDEP/PEXT r64, r64, r64

RORX r64, r64, r64

0.5

SALX/SARX/SHLX r64, r64, r64

0.5

LZCNT/TZCNT

Table 7-7. F16C,RDRAND Instructions

Instruction

Latency¹

Throughput

06_3D,

06_3C/

06_3D,

06_3C/

06_4E,

06_3A/

06_4E,

06_3A/

DisplayFamily_DisplayModel

06_47,

45/46/

06_47,

45/46/

06_5E

06_56

RDRAND* r64

Varies

<200

<300

~250

<200

VCVTPH2PS ymm1, xmm2

VCVTPH2PS xmm1, xmm2

VCVTPS2PH ymm1, xmm2, imm

VCVTPS2PH xmm1, xmm2, imm

* See Section 7.2

Table 7-8. 256-bit Intel® AVX Instructions

Instruction

Latency¹

Throughput

DisplayFamily_DisplayModel

06_4E,

06_3D/

06_3C/4

06_3A

06_4E,

06_3D/

06_3C/4

06_3A

06_5E

47/56

5/46/3F

/3E

06_5E

47/56

5/46/3F

/3E

VADDPD/PS ymm1, ymm2, ymm3

0.5

VADDSUBPD/PS ymm1, ymm2, ymm3

0.5

VANDNPD/PS ymm1, ymm2, ymm3

0.33

VANDPD/PS ymm1, ymm2, ymm3

0.33

VBLENDPD/PS ymm1, ymm2, ymm3,

0.33

0.5

imm

VBLENDVPD/PS ymm1, ymm2, ymm3,

ymm

VCMPPD/PS ymm1, ymm2, ymm3

0.5

7-7

INSTRUCTION LATENCY AND THROUGHPUT

Table 7-8. 256-bit Intel® AVX Instructions (Contd.)

Instruction

Latency¹

Throughput

DisplayFamily_DisplayModel

06_4E,

06_3D/

06_3C/4

06_3A

06_4E,

06_3D/

06_3C/4

06_3A

06_5E

47/56

5/46/3F

/3E

06_5E

47/56

5/46/3F

/3E

VCVTDQ2PD ymm1, ymm2

VCVTDQ2PS ymm1, ymm2

0.5

VCVT(T)PD2DQ ymm1, ymm2

VCVTPD2PS ymm1, ymm2

VCVT(T)PS2DQ ymm1, ymm2

VCVTPS2PD ymm1, xmm2

VDIVPD ymm1, ymm2, ymm3

16-23

25-35

27-35

VDIVPS ymm1, ymm2, ymm3

13-17

17-21

18-21

VDPPS ymm1, ymm2, ymm3

1.5

VEXTRACTF128 xmm1, ymm2, imm

VINSERTF128 ymm1, xmm2, imm

VMAXPD/PS ymm1, ymm2, ymm3

0.5

VMINPD/PS ymm1, ymm2, ymm3

0.5

VMOVAPD/PS ymm1, ymm2

0.25

0.5

VMOVDDUP ymm1, ymm2

VMOVDQA/U ymm1, ymm2

0.25

0.5

VMOVMSKPD/PS ymm1, ymm2

VMOVQ xmm1, xmm2

0.33

VMOVD/Q xmm1, r32/r64

VMOVD/Q r32/r64, xmm

VMOVNTDQ/PS/PD

VMOVSHDUP ymm1, ymm2

VMOVSLDUP ymm1, ymm2

VMOVUPD/PS ymm1, ymm2

0.25

0.5

VMULPD/PS ymm1, ymm2, ymm3

0.5

VORPD/PS ymm1, ymm2, ymm3

0.33

VPERM2F128 ymm1, ymm2, ymm3,

imm

VPERMILPD/PS ymm1, ymm2, ymm3

VRCPPS ymm1, ymm2

VROUNDPD/PS ymm1, ymm2, imm

VRSQRTPS ymm1, ymm2

VSHUFPD/PS ymm1, ymm2, ymm3,

imm

VSQRTPD ymm1, ymm2

<18

19-35

<12

16-27

VSQRTPS ymm1, ymm2

18-21

VSUBPD/PS ymm1, ymm2, imm

0.5

7-8

INSTRUCTION LATENCY AND THROUGHPUT

Table 7-8. 256-bit Intel® AVX Instructions (Contd.)

Instruction

Latency¹

Throughput

DisplayFamily_DisplayModel

06_4E,

06_3D/

06_3C/4

06_3A

06_4E,

06_3D/

06_3C/4

06_3A

06_5E

47/56

5/46/3F

/3E

06_5E

47/56

5/46/3F

/3E

VTESTPS ymm1, ymm2

VUNPCKHPD/PS ymm1, ymm2, ymm3

VUNPCKLPD/PS ymm1, ymm2, ymm3

VXORPD/PS ymm1, ymm2, ymm3

0.33

VZEROUPPER

VZEROALL

VEXTRACTPS reg, xmm2, imm

VINSERTPS xmm1, xmm2, reg, imm

VMASKMOVPD/PS mem^a, ymm, ymm

VMASKMOVPD/PS NUL, msk_0, ymm

>200^b

VMASKMOVPD/PS ymm, ymm^a, mem

VMASKMOVPD/PS ymm, msk_0,

>200

~200

>200

~200

[base+index]^c

Latency and Throughput data for CPUID signature 06_3AH are generally the same as those of 06_2AH, only those that

differ from 06_2AH are shown in the 06_3AH column.

a: MASKMOV instruction timing measured with L1 reference and mask register selecting at least 1 or more elements.

b: MASKMOV store instruction with a mask value selecting 0 elements and illegal address (NUL or non-NUL) incurs delay due

to assist.

c: MASKMOV Load instruction with a mask value selecting 0 elements and certain addressing forms incur delay due to

assist.

Latency of VEX.128 encoded AVX instructions should refer to corresponding legacy 128-bit instructions.

Table 7-9. AESNI and PCLMULQDQ Instructions

Instruction

Latency¹

Throughput

DisplayFamily_DisplayModel

06_4E,

06_3D/

06_3C/4

06_3A

06_4E,

06_3D/

06_3C/4

06_3A

06_5E

47/56

5/46/3F

/3E

06_5E

47/56

5/46/3F

/3E

AESDEC/AESDECLAST xmm1, xmm2

AESENC/AESENCLAST xmm1, xmm2

AESIMC xmm1, xmm2

AESKEYGENASSIST xmm1, xmm2, imm

PCLMULQDQ xmm1, xmm2, imm

7^b

b: includes 1-cycle bubble due to bypass.

7-9

INSTRUCTION LATENCY AND THROUGHPUT

Table 7-10. Intel® SSE4.2 Instructions

Instruction

Latency¹

Throughput

DisplayFamily_DisplayModel

06_4E,

06_3D

06_3C

06_3A

06_4E,

06_3D

06_3C/

06_3A

06_5E

/47/56

/45/46

/3E/2A

06_5E

/47/56

45/46/

/3E/2A

/3F

/2D

CRC32 r32, r32

PCMPESTRI xmm1, xmm2, imm

PCMPESTRM xmm1, xmm2, imm

PCMPISTRI xmm1, xmm2, imm

PCMPISTRM xmm1, xmm2, imm

PCMPGTQ xmm1, xmm2

0.33

POPCNT r32, r32

POPCNT r64, r64

Table 7-11. Intel® SSE4.1 Instructions

Instruction

Latency¹

Throughput

DisplayFamily_DisplayModel

06_4E,

06_3D

06_3C/

06_3A

06_4E,

06_3D/

06_3C/

06_3A

06_5E

/47/56

45/46/

/3E/2A

06_5E

47/56

45/46/

/3E/2A

/2D

BLENDPD/S xmm1, xmm2, imm

0.33

0.5

BLENDVPD/S xmm1, xmm2

DPPD xmm1, xmm2

DPPS xmm1, xmm2

EXTRACTPS xmm1, xmm2, imm

INSERTPS xmm1, xmm2, imm

MPSADBW xmm1, xmm2, imm

PACKUSDW xmm1, xmm2

0.5

PBLENVB xmm1, xmm2

PBLENDW xmm1, xmm2, imm

0.5

PCMPEQQ xmm1, xmm2

0.5

PEXTRB/W/D reg, xmm1, imm

PHMINPOSUW xmm1,xmm2

PINSRB/W/D xmm1,reg, imm

PMAXSB/SD xmm1, xmm2

0.5

PMAXUW/UD xmm1, xmm2

0.5

PMINSB/SD xmm1, xmm2

0.5

PMINUW/UD xmm1, xmm2

0.5

PMOVSXBD/BW/BQ xmm1, xmm2

0.5

PMOVSXWD/WQ/DQ xmm1, xmm2

0.5

7-10

INSTRUCTION LATENCY AND THROUGHPUT

Table 7-11. Intel® SSE4.1 Instructions (Contd.)

Instruction

Latency¹

Throughput

DisplayFamily_DisplayModel

06_4E,

06_3D

06_3C/

06_3A

06_4E,

06_3D/

06_3C/

06_3A

06_5E

/47/56

45/46/

/3E/2A

06_5E

47/56

45/46/

/3E/2A

/2D

PMOVZXBD/BW/BQ xmm1, xmm2

0.5

PMOVZXWD/WQ/DQ xmm1, xmm2

0.5

PMULDQ xmm1, xmm2

5^b

0.5

PMULLD xmm1, xmm2

10^c

PTEST xmm1, xmm2

ROUNDPD/PS xmm1, xmm2, imm

ROUNDSD/SS xmm1, xmm2, imm

b: includes 1-cycle bubble due to bypass

c: includes two 1-cycle bubbles due to bypass

Table 7-12. Intel® SSE3 Instructions

Instruction

Latency¹

Throughput

DisplayFamily_DisplayModel

06_4E,

06_3D/

06_3C/

06_3A/

06_4E,

06_3D/

06_3C/

06_3A/

06_5E

47/56

45/46/

3E/2A/

06_5E

47/56

45/46/

3E/2A/

PALIGNR xmm1, xmm2, imm

0.5

PHADDD xmm1, xmm2

1.5

PHADDW xmm1, xmm2

1.5

PHADDSW xmm1, xmm2

1.5

PHSUBD xmm1, xmm2

1.5

PHSUBW xmm1, xmm2

1.5

PHSUBSW xmm1, xmm2

1.5

PMADDUBSW xmm1, xmm2

5^b

0.5

PMULHRSW xmm1, xmm2

5^b

0.5

PSHUFB xmm1, xmm2

0.5

PSIGNB/D/W xmm1, xmm2

0.5

PABSB/D/W xmm1, xmm2

0.5

b: includes 1-cycle bubble due to bypass

7-11

INSTRUCTION LATENCY AND THROUGHPUT

Table 7-13. Intel® SSE3 SIMD Floating-point Instructions

Instruction

Latency¹

Throughput

DisplayFamily_DisplayMo

06_4E,06

06_3D/4

06_3C/4

06_3A/3

06_4E,06

06_3D/4

06_3C/4

06_3A/3

del

_5E

7/56

5/46/3F

E/2A/2D

_5E

7/56

5/46/3F

E/2A/2D

ADDSUBPD/ADDSUBPS

0.5

HADDPD xmm1, xmm2

HADDPS xmm1, xmm2

HSUBPD xmm1, xmm2

HSUBPS xmm1, xmm2

MOVDDUP xmm1, xmm2

MOVSHDUP xmm1, xmm2

MOVSLDUP xmm1, xmm2

Table 1-14. Intel® SIM SSE2 128-bit Integer Instructions

Instruction

Latency¹

Throughput

06_4E,

06_3D/4

06_3C/4

06_3A/3

06_4E,

06_3D/4

06_3C/4

06_3A/3

CPUID

06_5E

7/56

5/46/3F

E/2A/2D

06_5E

7/56

5/46/3F

E/2A/2D

CVTPS2DQ xmm, xmm

CVTTPS2DQ xmm, xmm

MASKMOVDQU xmm, xmm

MOVD xmm, r64/r32

MOVD r64/r32, xmm

MOVDQA xmm, xmm

0.25

0.33

0.5

MOVDQU xmm, xmm

0.25

0.33

0.5

MOVQ xmm, xmm

0.33

PACKSSWB/PACKSSDW/

0.5

PACKUSWB xmm, xmm

PADDB/PADDW/PADDD

0.33

0.5

xmm, xmm

PADDSB/PADDSW/

0.5

PADDUSB/PADDUSW

xmm, xmm

PADDQ/ PSUBQ³ xmm, xmm

0.33

0.5

PAND xmm, xmm

0.33

PANDN xmm, xmm

0.33

PAVGB/PAVGW xmm, xmm

0.5

PCMPEQB/PCMPEQD/

0.5

PCMPEQW xmm, xmm

PCMPGTB/PCMPGTD/PCMP

0.5

GTW xmm, xmm

PEXTRW r32, xmm, imm8

PINSRW xmm, r32, imm8

7-12

INSTRUCTION LATENCY AND THROUGHPUT

Table 1-14. Intel® SIM SSE2 128-bit Integer Instructions (Contd.)

Instruction

Latency¹

Throughput

06_4E,

06_3D/4

06_3C/4

06_3A/3

06_4E,

06_3D/4

06_3C/4

06_3A/3

CPUID

06_5E

7/56

5/46/3F

E/2A/2D

06_5E

7/56

5/46/3F

E/2A/2D

PMADDWD xmm, xmm

5^b

0.5

PMAX xmm, xmm

0.5

PMIN xmm, xmm

0.5

PMOVMSKB³ r32, xmm

PMULHUW/PMULHW/

5^b

0.5

PMULLW xmm, xmm

PMULUDQ xmm, xmm

5^b

0.5

POR xmm, xmm

0.33

PSADBW xmm, xmm

PSHUFD xmm, xmm, imm8

0.5

PSHUFHW xmm, xmm, imm8

0.5

PSHUFLW xmm, xmm, imm8

0.5

PSLLDQ xmm, imm8

0.5

PSLLW/PSLLD/PSLLQ xmm,

imm8

PSLL/PSRL xmm, xmm

PSRAW/PSRAD xmm, imm8

PSRAW/PSRAD xmm, xmm

PSRLDQ xmm, imm8

0.5

PSRLW/PSRLD/PSRLQ xmm,

imm8

PSUBB/PSUBW/PSUBD

0.33

0.5

xmm, xmm

PSUBSB/PSUBSW/PSUBUSB

0.5

/PSUBUSW xmm, xmm

PUNPCKHBW/PUNPCKHWD/

0.5

PUNPCKHDQ xmm, xmm

PUNPCKHQDQ xmm, xmm

0.5

PUNPCKLBW/PUNPCKLWD/

0.5

PUNPCKLDQ xmm, xmm

PUNPCKLQDQ xmm, xmm

0.5

PXOR xmm, xmm

0.33

b: includes 1-cycle bubble due to bypass

7-13

INSTRUCTION LATENCY AND THROUGHPUT

Table 7-15. Intel® SSE2 Double-Precision Floating-Point Instructions

Instruction

Latency¹

Throughput

CPUID

06_4E,

06_3D/4

06_3C/4

06_2A/2

06_4E,

06_3D/4

06_3C/4

06_2A/2

06_5E

7/56

5/46/3F

D(06_3A/

06_5E

7/56

5/46/3F

D(06_3A/

3E)

ADDPD xmm, xmm

0.5

ADDSD xmm, xmm

0.5

ANDNPD xmm, xmm

0.33

ANDPD xmm, xmm

0.33

CMPPD xmm, xmm, imm8

0.5

CMPSD xmm, xmm, imm8

0.5

COMISD xmm, xmm

CVTDQ2PD xmm, xmm

CVTDQ2PS xmm, xmm

CVTPD2DQ xmm, xmm

CVTPD2PS xmm, xmm

CVT[T]PS2DQ xmm, xmm

CVTPS2PD xmm, xmm

CVT[T]SD2SI r64/r32, xmm

CVTSD2SS xmm, xmm

CVTSI2SD xmm, r64/r32

CVTSS2SD xmm, xmm

CVTTPD2DQ xmm, xmm

CVTTSD2SI r32, xmm

DIVPD xmm, xmm¹

<14

14-20

16-22

22(14)

(15-20)

DIVSD xmm, xmm

<14

14-20

16-22

22(14)

(15-20)

MAXPD xmm, xmm

0.5

MAXSD xmm, xmm

0.5

MINPD xmm, xmm

0.5

MINSD xmm, xmm

0.5

MOVAPD xmm, xmm

0.33

0.5

MOVMSKPD r64/r32, xmm

MOVSD xmm, xmm

MOVUPD xmm, xmm

0.33

0.5

MULPD xmm, xmm

0.5

MULSD xmm, xmm

0.5

ORPD xmm, xmm

0.33

SHUFPD xmm, xmm, imm8

SQRTPD xmm, xmm²

22(21)

22(14)

SQRTSD xmm, xmm

22(21)

22(14)

SUBPD xmm, xmm

0.5

7-14

INSTRUCTION LATENCY AND THROUGHPUT

Table 7-15. Intel® SSE2 Double-Precision Floating-Point Instructions (Contd.)

Instruction

Latency¹

Throughput

CPUID

06_4E,

06_3D/4

06_3C/4

06_2A/2

06_4E,

06_3D/4

06_3C/4

06_2A/2

06_5E

7/56

5/46/3F

D(06_3A/

06_5E

7/56

5/46/3F

D(06_3A/

3E)

SUBSD xmm, xmm

0.5

UCOMISD xmm, xmm

UNPCKHPD xmm, xmm

UNPCKLPD xmm, xmm

XORPD³ xmm, xmm

0.33

NOTES:

1. The latency and throughput of DIVPD/DIVSD can vary with input values. For certain values, hardware can complete

quickly, throughput may be as low as ~ 6 cycles. Similarly, latency for certain input values may be as low as less than 10

cycles.

2. The latency throughput of SQRTPD/SQRTSD can vary with input value. For certain values, hardware can complete quickly,

throughput may be as low as ~ 6 cycles. Similarly, latency for certain input values may be as low as less than10 cycles.

Table 7-16. Intel® SSE Single-Precision Floating-Point Instructions

Instruction

Latency¹

Throughput

06_4E,

06_3D/4

06_3C/4

06_2A/2

06_4E,

06_3D/4

06_3C/4

06_2A/2

06_5E

7/56

5/46/3F

D(06_3A/

06_5E

7/56

5/46/3F

D(06_3A/

CPUID

3E)

ADDPS xmm, xmm

0.5

ADDSS xmm, xmm

0.5

ANDNPS xmm, xmm

0.33

ANDPS xmm, xmm

0.33

CMPPS xmm, xmm

0.5

CMPSS xmm, xmm

0.5

COMISS xmm, xmm

CVTSI2SS xmm, r32

CVTSS2SI r32, xmm

CVT[T]SS2SI r64, xmm

CVTTSS2SI r32, xmm

DIVPS xmm, xmm¹

<11

<13

10-14

14(6)

DIVSS xmm, xmm

<11

<13

10-14

2.5

14(6)

MAXPS xmm, xmm

0.5

MAXSS xmm, xmm

0.5

MINPS xmm, xmm

0.5

MINSS xmm, xmm

0.5

MOVAPS xmm, xmm

0.25

0.5

MOVHLPS xmm, xmm

MOVLHPS xmm, xmm

MOVMSKPS r64/r32, xmm

7-15

INSTRUCTION LATENCY AND THROUGHPUT

Table 7-16. Intel® SSE Single-Precision Floating-Point Instructions (Contd.)

Instruction

Latency¹

Throughput

06_4E,

06_3D/4

06_3C/4

06_2A/2

06_4E,

06_3D/4

06_3C/4

06_2A/2

06_5E

7/56

5/46/3F

D(06_3A/

06_5E

7/56

5/46/3F

D(06_3A/

CPUID

3E)

MOVSS xmm, xmm

MOVUPS xmm, xmm

0.25

0.5

MULPS xmm, xmm

0.5

MULSS xmm, xmm

0.5

ORPS xmm, xmm

0.33

RCPPS xmm, xmm

RCPSS xmm, xmm

RSQRTPS xmm, xmm

RSQRTSS xmm, xmm

SHUFPS xmm, xmm, imm8

SQRTPS xmm, xmm²

14(7)

SQRTSS xmm, xmm

14(7)

SUBPS xmm, xmm

0.5

SUBSS xmm, xmm

0.5

UCOMISS xmm, xmm

UNPCKHPS xmm, xmm

UNPCKLPS xmm, xmm

XORPS xmm, xmm

LFENCE³

MFENCE³

~40

~35

SFENCE³

STMXCSR³

FXSAVE³

~90

~71

~75

~78

NOTES:

1. The latency and throughput of DIVPS/DIVSS can vary with input values. For certain values, hardware can complete

quickly, throughput may be as low as ~ 6 cycles. Similarly, latency for certain input values may be as low as less than 10

cycles.

2. The latency and throughput of SQRTPS/SQRTSS can vary with input values. For certain values, hardware can complete

quickly, throughput may be as low as ~ 6 cycles. Similarly, latency for certain input values may be as low as less than 10

cycles

3. The throughputs of FXSAVE/LFENCE/MFENCE/SFENCE/STMXCSR are measured with the destination in L1 Data Cache.

7-16

INSTRUCTION LATENCY AND THROUGHPUT

Table 1-17. General Purpose Instructions

Instruction

Latency¹

Throughput

CPUID

06_4E,06

06_3D/4

06_3C/4

06_3A,

06_4E,06

06_3D/4

06_3C/4

06_3A,

_5E

7/56

5/46/3F

06_3E

_5E

7/56

5/46/3F

06_3E

ADC/SBB reg, reg

0.5

ADC/SBB reg, imm

0.5

ADD/SUB

0.25

0.33

AND/OR/XOR

0.25

0.33

BSF/BSR

BSWAP

0.5

BTC/BTR/BTS

0.5

CBW/CWDE/CDQE

CDQ

CQO

0.5

CLC

0.25

0.33

CMC

0.25

0.33

STC

0.25

0.33

CLFLUSH¹²

~2 to 50

~3 to 50

~5 to 50

CLFLUSHOPT¹³

~2to 10

CMOVE/CMOVcc

0.5

CMOVBE/NBE/A/NA

CMP/TEST

0.25

0.33

CPUID (EAX = 0)

~100

~95

CPUID (EAX != 0)

>200

CMPXCHG r64, r64

CMPXCHG8B m64

CMPXCHG16B m128

Lock CMPXCHG8B m64

Lock CMPXCHG16B m128

DEC/INC

0.25

0.33

IMUL r64, r64

IMUL r64¹⁰

4, 5

3, 4

IMUL r32

IDIV r64 (RDX!= 0)⁸

~85-100

IDIV r32⁹

~20-26

~19-25

LEA

0.5

LEA [base+index]disp

MOVSB/MOVSW

0..25

0.33

MOVZB/MOVZW

0.25

0.33

DIV r64 (RDX!= 0)⁸

~80-95

DIV r32⁹

~20-26

~19-25

7-17

INSTRUCTION LATENCY AND THROUGHPUT

Table 1-17. General Purpose Instructions (Contd.)

Instruction

Latency¹

Throughput

CPUID

06_4E,06

06_3D/4

06_3C/4

06_3A,

06_4E,06

06_3D/4

06_3C/4

06_3A,

_5E

7/56

5/46/3F

06_3E

_5E

7/56

5/46/3F

06_3E

MUL r64¹⁰

4, 5

3, 4

NEG/NOT

0.25

0.33

PAUSE

~140

~10

RCL/RCR reg, 1

1.5

RCL/RCR

RDTSC

~13

~10

~20

RDTSCP

~20

~30

ROL/ROR reg 1

1 (2 flg)

ROL/ROR reg imm

0.5

ROL/ROR reg, cl

1.5

LAHF/SAHF

SAL/SAR/SHL/SHR reg, imm

0.5

SAL/SAR/SHL/SHR reg, cl

1.5

SETBE

SETE

0.5

SHLD/RD reg, reg, cl

2 (4 flg)

1.5

SHLD/RD reg, reg, imm

0.5

XSAVE¹¹

~98

~100

XSAVEOPT¹¹

~86

~90

XADD

XCHG reg, reg

XCHG reg, mem

7.3.2

Table Footnotes

The following footnotes refer to all tables in this appendix.

1. Latency information for many instructions that are complex (> 4 ops) are estimates based on

conservative (worst-case) estimates. Actual performance of these instructions by the out-of-order

core execution unit can range from somewhat faster to significantly faster than the latency data

shown in these tables.

2. Latency and Throughput of transcendental instructions can vary substantially in a dynamic execution

environment. Only an approximate value or a range of values are given for these instructions.

3. It may be possible to construct repetitive calls to some Intel 64 and IA-32 instructions in code

sequences to achieve latency that is one or two clock cycles faster than the more realistic number

listed in this table.

4. The FXCH instruction has 0 latency in code sequences. However, it is limited to an issue rate of one

instruction per clock cycle.

5. The load constant instructions, FINCSTP, and FDECSTP have 0 latency in code sequences.

6. Selection of conditional jump instructions should be based on the recommendation of Section 3.4.1,

“Branch Prediction Optimization,” to improve the predictability of branches. When branches are

predicted successfully, the latency of jcc is effectively zero.

7-18

INSTRUCTION LATENCY AND THROUGHPUT

RCL/RCR with shift count of 1 are optimized. Using RCL/RCR with shift count other than 1 will be

executed more slowly. This applies to the Pentium 4 and Intel Xeon processors.

The throughput of “DIV/IDIV r64” varies with the number of significant digits in the input RDX:RAX.

The throughput is significantly higher if RDX input is 0, similar to those of “DIV/IDIV r32”. If RDX is

not zero, the throughput is significantly lower, as shown in the range. The throughput decreases

(increasing numerical value in cycles) with increasing number of significant bits in the input RDX:RAX

(relative to the number of significant bits of the divisor) or the output quotient. The latency of

“DIV/IDIV r64” also varies with the significant bits of input values. For a given set of input values, the

latency is about the same as the throughput in cycles.

The throughput of “DIV/IDIV r32” varies with the number of significant digits in the input EDX:EAX

and/or of the quotient of the division for a given size of significant bits in the divisor r32. The

throughput decreases (increasing numerical value in cycles) with increasing number of significant

bits in the input EDX:EAX or the output quotient. The latency of “DIV/IDIV r32” also varies with the

significant bits of the input values. For a given set of input values, the latency is about the same as

the throughput in cycles.

10. The latency of MUL r64 into 128-bit result has two sets of numbers, the read-to-use latency of the

low 64-bit result (RAX) is smaller. The latency of the high 64-bit of the 128 bit result (RDX) is larger.

11. The throughputs of XSAVE and XSAVEOPT are measured with the destination in L1 Data Cache and

includes the YMM states.

12. CLFLUSH throughput is representative from clean cache lines for a range of buffer sizes. CLFLUSH

throughput can decrease significantly by factors including: (a) the number of back-to-back CLFLUSH

being executed, (b) flushing modified cache lines incurs additional cost than cache lines in other

coherent state. See Section 9.4.6.

13. CLFLUSHOPT throughput is representative from clean cache lines for a range of buffer sizes.

CLFLUSHOPT throughput can decrease by factors including: (a) flushing modified cache lines incurs

additional cost than cache lines in other coherent state, (b) the number of cache lines back-to-back.

See Section 9.4.7.

7.3.3

Instructions with Memory Operands

The latency of an Instruction with memory operand can vary greatly due to a number of factors, including

data locality in the memory/cache hierarchy and characteristics that are unique to each

microarchitecture. Generally, software can approach tuning for locality and instruction selection

independently. Thus Table 7-4 through Table 7-18 can be used for the purpose of instruction selection.

Latency and throughput of data movement in the cache/memory hierarchy can be dealt with indepen-

dent of instruction latency and throughput. Load-to-use Latency of the cache hierarchy can be found in

Chapter 2.

7.3.3.1

Software Observable Latency of Memory References

When measuring latency of memory references of individual instructions, many factors can influence the

observed latency exposure. Aside from access patterns, cache locality, effect of the hardware

prefetchers, different microarchitectures may expose variability such register domains of the destination

or memory addressing form with respect to the instruction encoding.

Table 7-18 gives a few selected sampling of the variability of L1D cache hit latency that software may

observe using pointer-chasing constructs, due to memory reference encoding details, on recent Intel

microarchitectures.

7-19

Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 153