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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 134

 

 

MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register
Shared/
Address
Register Name
Unique
Bit Description
Hex
Dec
9:8
Reserved
10
Shared
FERR# Multiplexing Enable (R/W)
1 = FERR# asserted by the processor to indicate a pending
break event within the processor
0 = Indicates compatible FERR# signaling behavior
This bit must be set to 1 to support XAPIC interrupt model
usage.
11
Shared
Branch Trace Storage Unavailable (R/O)
See Table 2-2.
12
Reserved
13
Shared
TM2 Enable (R/W)
When this bit is set (1) and the thermal sensor indicates that
the die temperature is at the pre-determined threshold, the
Thermal Monitor 2 mechanism is engaged. TM2 will reduce the
bus to core ratio and voltage according to the value last
written to MSR_THERM2_CTL bits 15:0.
When this bit is clear (0, default), the processor does not
change the VID signals or the bus to core ratio when the
processor enters a thermal managed state.
If the TM2 feature flag (ECX[8]) is not set to 1 after executing
CPUID with EAX = 1, then this feature is not supported and
BIOS must not alter the contents of this bit location. The
processor is operating out of spec if both this bit and the TM1
bit are set to disabled states.
15:14
Reserved
16
Shared
Enhanced Intel SpeedStep Technology Enable (R/W)
1 = Enhanced Intel SpeedStep Technology enabled
18
Shared
ENABLE MONITOR FSM (R/W)
See Table 2-2.
19
Reserved
22
Shared
Limit CPUID Maxval (R/W)
See Table 2-2.
Setting this bit may cause behavior in software that depends
on the availability of CPUID leaves greater than 2.
33:23
Reserved
34
Shared
XD Bit Disable (R/W)
See Table 2-3.
63:35
Reserved
1C9H
457
MSR_LASTBRANCH_TOS
Unique
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-3) that points to the MSR containing
the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP (at 40H).
Vol. 4
2-405
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register
Shared/
Address
Register Name
Unique
Bit Description
Hex
Dec
1D9H
473
IA32_DEBUGCTL
Unique
Debug Control (R/W)
Controls how several debug features are used. Bit definitions
are discussed in Table 2-2.
1DDH
477
MSR_LER_FROM_LIP
Unique
Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction that the
processor executed prior to the last exception that was
generated or the last interrupt that was handled.
1DEH
478
MSR_LER_TO_LIP
Unique
Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the last branch
instruction that the processor executed prior to the last
exception that was generated or the last interrupt that was
handled.
200H
512
MTRRphysBase0
Unique
Memory Type Range Registers
201H
513
MTRRphysMask0
Unique
Memory Type Range Registers
202H
514
MTRRphysBase1
Unique
Memory Type Range Registers
203H
515
MTRRphysMask1
Unique
Memory Type Range Registers
204H
516
MTRRphysBase2
Unique
Memory Type Range Registers
205H
517
MTRRphysMask2
Unique
Memory Type Range Registers
206H
518
MTRRphysBase3
Unique
Memory Type Range Registers
207H
519
MTRRphysMask3
Unique
Memory Type Range Registers
208H
520
MTRRphysBase4
Unique
Memory Type Range Registers
209H
521
MTRRphysMask4
Unique
Memory Type Range Registers
20AH
522
MTRRphysBase5
Unique
Memory Type Range Registers
20BH
523
MTRRphysMask5
Unique
Memory Type Range Registers
20CH
524
MTRRphysBase6
Unique
Memory Type Range Registers
20DH
525
MTRRphysMask6
Unique
Memory Type Range Registers
20EH
526
MTRRphysBase7
Unique
Memory Type Range Registers
20FH
527
MTRRphysMask7
Unique
Memory Type Range Registers
250H
592
MTRRfix64K_00000
Unique
Memory Type Range Registers
258H
600
MTRRfix16K_80000
Unique
Memory Type Range Registers
259H
601
MTRRfix16K_A0000
Unique
Memory Type Range Registers
268H
616
MTRRfix4K_C0000
Unique
Memory Type Range Registers
269H
617
MTRRfix4K_C8000
Unique
Memory Type Range Registers
26AH
618
MTRRfix4K_D0000
Unique
Memory Type Range Registers
26BH
619
MTRRfix4K_D8000
Unique
Memory Type Range Registers
26CH
620
MTRRfix4K_E0000
Unique
Memory Type Range Registers
26DH
621
MTRRfix4K_E8000
Unique
Memory Type Range Registers
26EH
622
MTRRfix4K_F0000
Unique
Memory Type Range Registers
26FH
623
MTRRfix4K_F8000
Unique
Memory Type Range Registers
2-406 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register
Shared/
Address
Register Name
Unique
Bit Description
Hex
Dec
2FFH
767
IA32_MTRR_DEF_TYPE
Unique
Default Memory Types (R/W)
See Table 2-2.
See Section 12.11.2.1, “IA32_MTRR_DEF_TYPE MSR.”
400H
1024
IA32_MC0_CTL
Unique
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
401H
1025
IA32_MC0_STATUS
Unique
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
402H
1026
IA32_MC0_ADDR
Unique
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or
contains no address if the ADDRV flag in the
IA32_MC0_STATUS register is clear. When not implemented in
the processor, all reads and writes to this MSR will cause a
general-protection exception.
404H
1028
IA32_MC1_CTL
Unique
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
405H
1029
IA32_MC1_STATUS
Unique
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
406H
1030
IA32_MC1_ADDR
Unique
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC1_ADDR register is either not implemented or
contains no address if the ADDRV flag in the
IA32_MC1_STATUS register is clear. When not implemented in
the processor, all reads and writes to this MSR will cause a
general-protection exception.
408H
1032
IA32_MC2_CTL
Unique
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
409H
1033
IA32_MC2_STATUS
Unique
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
40AH
1034
IA32_MC2_ADDR
Unique
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or
contains no address if the ADDRV flag in the
IA32_MC2_STATUS register is clear. When not implemented in
the processor, all reads and writes to this MSR will cause a
general-protection exception.
40CH
1036
MSR_MC4_CTL
Unique
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
40DH
1037
MSR_MC4_STATUS
Unique
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
40EH
1038
MSR_MC4_ADDR
Unique
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or
contains no address if the ADDRV flag in the
MSR_MC4_STATUS register is clear. When not implemented in
the processor, all reads and writes to this MSR will cause a
general-protection exception.
410H
1040
IA32_MC3_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
411H
1041
IA32_MC3_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
412H
1042
MSR_MC3_ADDR
Unique
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or
contains no address if the ADDRV flag in the
MSR_MC3_STATUS register is clear. When not implemented in
the processor, all reads and writes to this MSR will cause a
general-protection exception.
Vol. 4
2-407
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register
Shared/
Address
Register Name
Unique
Bit Description
Hex
Dec
413H
1043
MSR_MC3_MISC
Unique
Machine Check Error Reporting Register - contains additional
information describing the machine-check error if the MISCV
flag in the IA32_MCi_STATUS register is set.
414H
1044
MSR_MC5_CTL
Unique
Machine Check Error Reporting Register - controls signaling of
#MC for errors produced by a particular hardware unit (or
group of hardware units).
415H
1045
MSR_MC5_STATUS
Unique
Machine Check Error Reporting Register - contains information
related to a machine-check error if its VAL (valid) flag is set.
Software is responsible for clearing IA32_MCi_STATUS MSRs
by explicitly writing 0s to them; writing 1s to them causes a
general-protection exception.
416H
1046
MSR_MC5_ADDR
Unique
Machine Check Error Reporting Register - contains the address
of the code or data memory location that produced the
machine-check error if the ADDRV flag in the
IA32_MCi_STATUS register is set.
417H
1047
MSR_MC5_MISC
Unique
Machine Check Error Reporting Register - contains additional
information describing the machine-check error if the MISCV
flag in the IA32_MCi_STATUS register is set.
480H
1152
IA32_VMX_BASIC
Unique
Reporting Register of Basic VMX Capabilities (R/O)
See Table 2-2.
See Appendix A.1, “Basic VMX Information.”
(If CPUID.01H:ECX.[bit 5])
481H
1153
IA32_VMX_PINBASED_CTLS
Unique
Capability Reporting Register of Pin-Based VM-Execution
Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
(If CPUID.01H:ECX.[bit 5])
482H
1154
IA32_VMX_PROCBASED_CTLS
Unique
Capability Reporting Register of Primary Processor-Based
VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
(If CPUID.01H:ECX.[bit 5])
483H
1155
IA32_VMX_EXIT_CTLS
Unique
Capability Reporting Register of VM-Exit Controls (R/O)
See Appendix A.4, “VM-Exit Controls.”
(If CPUID.01H:ECX.[bit 5])
484H
1156
IA32_VMX_ENTRY_CTLS
Unique
Capability Reporting Register of VM-Entry Controls (R/O)
See Appendix A.5, “VM-Entry Controls.”
(If CPUID.01H:ECX.[bit 5])
485H
1157
IA32_VMX_MISC
Unique
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Appendix A.6, “Miscellaneous Data.”
(If CPUID.01H:ECX.[bit 5])
486H
1158
IA32_VMX_CR0_FIXED0
Unique
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0.”
(If CPUID.01H:ECX.[bit 5])
2-408 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-58. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register
Shared/
Address
Register Name
Unique
Bit Description
Hex
Dec
487H
1159
IA32_VMX_CR0_FIXED1
Unique
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0.”
(If CPUID.01H:ECX.[bit 5])
488H
1160
IA32_VMX_CR4_FIXED0
Unique
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4.”
(If CPUID.01H:ECX.[bit 5])
489H
1161
IA32_VMX_CR4_FIXED1
Unique
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4.”
(If CPUID.01H:ECX.[bit 5])
48AH
1162
IA32_VMX_VMCS_ENUM
Unique
Capability Reporting Register of VMCS Field Enumeration (R/O)
See Appendix A.9, “VMCS Enumeration.”
(If CPUID.01H:ECX.[bit 5])
48BH
1163
IA32_VMX_PROCBASED_CTLS2
Unique
Capability Reporting Register of Secondary Processor-Based
VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
(If CPUID.01H:ECX.[bit 5] and
IA32_VMX_PROCBASED_CTLS[bit 63])
600H
1536
IA32_DS_AREA
Unique
DS Save Area (R/W)
See Table 2-2.
See Section 20.6.3.4, “Debug Store (DS) Mechanism.”
31:0
DS Buffer Management Area
Linear address of the first byte of the DS buffer management
area.
63:32
Reserved
C000_
IA32_EFER
Unique
See Table 2-2.
0080H
10:0
Reserved
11
Execute Disable Bit Enable
63:12
Reserved
2.21
MSRS IN THE PENTIUM M PROCESSOR
Model-specific registers (MSRs) for the Pentium M processor are similar to those described in Section 2.22 for P6
family processors. The following table describes new MSRs and MSRs whose behavior has changed on the Pentium
M processor.
Table 2-59. MSRs in Pentium M Processors
Register
Bit Description
Address
Register Name / Bit Fields
Hex
Dec
0H
0
P5_MC_ADDR
See Section 2.23, “MSRs in Pentium Processors.”
Vol. 4
2-409
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-59. MSRs in Pentium M Processors (Contd.)
Register
Bit Description
Address
Register Name / Bit Fields
Hex
Dec
1H
1
P5_MC_TYPE
See Section 2.23, “MSRs in Pentium Processors.”
10H
16
IA32_TIME_STAMP_COUNTER
See Section 18.17, “Time-Stamp Counter,” and see Table 2-2.
17H
23
IA32_PLATFORM_ID
Platform ID (R)
See Table 2-2.
The operating system can use this MSR to determine “slot” information
for the processor and the proper microcode update to load.
2AH
42
MSR_EBL_CR_POWERON
Processor Hard Power-On Configuration
(R/W) Enables and disables processor features.
(R) Indicates current processor configuration.
0
Reserved
1
Data Error Checking Enable (R)
0 = Disabled
Always 0 on the Pentium M processor.
2
Response Error Checking Enable (R)
0 = Disabled
Always 0 on the Pentium M processor.
3
MCERR# Drive Enable (R)
0 = Disabled
Always 0 on the Pentium M processor.
4
Address Parity Enable (R)
0 = Disabled
Always 0 on the Pentium M processor.
6:5
Reserved
7
BINIT# Driver Enable (R)
1 = Enabled; 0 = Disabled
Always 0 on the Pentium M processor.
8
Output Tri-state Enabled (R/O)
1 = Enabled; 0 = Disabled
9
Execute BIST (R/O)
1 = Enabled; 0 = Disabled
10
MCERR# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled
Always 0 on the Pentium M processor.
11
Reserved
12
BINIT# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled
Always 0 on the Pentium M processor.
13
Reserved
2-410 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-59. MSRs in Pentium M Processors (Contd.)
Register
Bit Description
Address
Register Name / Bit Fields
Hex
Dec
14
1 MByte Power on Reset Vector (R/O)
1 = 1 MByte; 0 = 4 GBytes
Always 0 on the Pentium M processor.
15
Reserved
17:16
APIC Cluster ID (R/O)
Always 00B on the Pentium M processor.
18
System Bus Frequency (R/O)
0 = 100 MHz
1 = Reserved
Always 0 on the Pentium M processor.
19
Reserved
21: 20
Symmetric Arbitration ID (R/O)
Always 00B on the Pentium M processor.
26:22
Clock Frequency Ratio (R/O)
40H
64
MSR_LASTBRANCH_0
Last Branch Record 0 (R/W)
One of 8 last branch record registers on the last branch record stack: bits
31-0 hold the ‘from’ address and bits 63-32 hold the to address.
See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.15, “Last Branch, Interrupt, and Exception Recording
(Pentium M Processors).”
41H
65
MSR_LASTBRANCH_1
Last Branch Record 1 (R/W)
See description of MSR_LASTBRANCH_0.
42H
66
MSR_LASTBRANCH_2
Last Branch Record 2 (R/W)
See description of MSR_LASTBRANCH_0.
43H
67
MSR_LASTBRANCH_3
Last Branch Record 3 (R/W)
See description of MSR_LASTBRANCH_0.
44H
68
MSR_LASTBRANCH_4
Last Branch Record 4 (R/W)
See description of MSR_LASTBRANCH_0.
45H
69
MSR_LASTBRANCH_5
Last Branch Record 5 (R/W)
See description of MSR_LASTBRANCH_0.
46H
70
MSR_LASTBRANCH_6
Last Branch Record 6 (R/W)
See description of MSR_LASTBRANCH_0.
47H
71
MSR_LASTBRANCH_7
Last Branch Record 7 (R/W)
See description of MSR_LASTBRANCH_0.
119H
281
MSR_BBL_CR_CTL
Control Register
Used to program L2 commands to be issued via cache configuration
accesses mechanism. Also receives L2 lookup response.
63:0
Reserved
11EH
281
MSR_BBL_CR_CTL3
Control register 3
Used to configure the L2 Cache.
Vol. 4
2-411
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-59. MSRs in Pentium M Processors (Contd.)
Register
Bit Description
Address
Register Name / Bit Fields
Hex
Dec
0
L2 Hardware Enabled (R/O)
1 = If the L2 is hardware-enabled.
0 = Indicates if the L2 is hardware-disabled.
4:1
Reserved
5
ECC Check Enable (R/O)
This bit enables ECC checking on the cache data bus. ECC is always
generated on write cycles.
0 = Disabled (default)
1 = Enabled
For the Pentium M processor, ECC checking on the cache data bus is
always enabled.
7:6
Reserved
8
L2 Enabled (R/W)
1 = L2 cache has been initialized
0 = Disabled (default)
Until this bit is set the processor will not respond to the WBINVD
instruction or the assertion of the FLUSH# input.
22:9
Reserved
23
L2 Not Present (R/O)
0 = L2 Present
1 = L2 Not Present
63:24
Reserved
179H
377
IA32_MCG_CAP
Read-only register that provides information about the machine-check
architecture of the processor.
7:0
Count (R/O)
Indicates the number of hardware unit error reporting banks available in
the processor.
8
IA32_MCG_CTL Present (R/O)
1 = Indicates that the processor implements the MSR_MCG_CTL
register found at MSR 17BH.
0 = Not supported.
63:9
Reserved
17AH
378
IA32_MCG_STATUS
Global Machine Check Status
0
RIPV
When set, this bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check was
generated) can be used to restart the program. If this bit is cleared, the
program cannot be reliably restarted.
1
EIPV
When set, this bit indicates that the instruction addressed by the
instruction pointer pushed on the stack (when the machine check was
generated) is directly associated with the error.
2-412 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-59. MSRs in Pentium M Processors (Contd.)
Register
Bit Description
Address
Register Name / Bit Fields
Hex
Dec
2
MCIP
When set, this bit indicates that a machine check has been generated. If a
second machine check is detected while this bit is still set, the processor
enters a shutdown state. Software should write this bit to 0 after
processing a machine check exception.
63:3
Reserved
198H
408
IA32_PERF_STATUS
See Table 2-2.
199H
409
IA32_PERF_CTL
See Table 2-2.
19AH
410
IA32_CLOCK_MODULATION
Clock Modulation (R/W).
See Table 2-2.
See Section 15.8.3, “Software Controlled Clock Modulation.”
19BH
411
IA32_THERM_INTERRUPT
Thermal Interrupt Control (R/W)
See Table 2-2.
See Section 15.8.2, “Thermal Monitor.”
19CH
412
IA32_THERM_STATUS
Thermal Monitor Status (R/W)
See Table 2-2.
See Section 15.8.2, “Thermal Monitor.”
19DH
413
MSR_THERM2_CTL
Thermal Monitor 2 Control
15:0
Reserved
16
TM_SELECT (R/W)
Mode of automatic thermal monitor:
0 = Thermal Monitor 1 (thermally-initiated on-die modulation of the
stop-clock duty cycle)
1 = Thermal Monitor 2 (thermally-initiated frequency transitions)
If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no
effect. Neither TM1 nor TM2 will be enabled.
63:16
Reserved
1A0H
416
IA32_MISC_ENABLE
Enable Miscellaneous Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
2:0
Reserved
Vol. 4
2-413
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-59. MSRs in Pentium M Processors (Contd.)
Register
Bit Description
Address
Register Name / Bit Fields
Hex
Dec
3
Automatic Thermal Control Circuit Enable (R/W)
1 = Setting this bit enables the thermal control circuit (TCC) portion of
the Intel Thermal Monitor feature. This allows processor clocks to
be automatically modulated based on the processor's thermal
sensor operation.
0 = Disabled (default).
The automatic thermal control circuit enable bit determines if the
thermal control circuit (TCC) will be activated when the processor's
internal thermal sensor determines the processor is about to exceed its
maximum operating temperature.
When the TCC is activated and TM1 is enabled, the processors clocks will
be forced to a 50% duty cycle. BIOS must enable this feature.
The bit should not be confused with the on-demand thermal control
circuit enable bit.
6:4
Reserved
7
Performance Monitoring Available (R)
1 = Performance monitoring enabled.
0 = Performance monitoring disabled.
9:8
Reserved
10
FERR# Multiplexing Enable (R/W)
1 = FERR# asserted by the processor to indicate a pending break
event within the processor.
0 = Indicates compatible FERR# signaling behavior.
This bit must be set to 1 to support XAPIC interrupt model usage.
Branch Trace Storage Unavailable (R/O)
1 = Processor doesn’t support branch trace storage (BTS)
0 = BTS is supported
12
Processor Event Based Sampling Unavailable (R/O)
1 = Processor does not support processor event based sampling
(PEBS);
0 = PEBS is supported.
The Pentium M processor does not support PEBS.
15:13
Reserved
16
Enhanced Intel SpeedStep Technology Enable (R/W)
1 = Enhanced Intel SpeedStep Technology enabled.
On the Pentium M processor, this bit may be configured to be read-only.
22:17
Reserved
23
xTPR Message Disable (R/W)
When set to 1, xTPR messages are disabled. xTPR messages are optional
messages that allow the processor to inform the chipset of its priority.
The default is processor specific.
63:24
Reserved
2-414 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-59. MSRs in Pentium M Processors (Contd.)
Register
Bit Description
Address
Register Name / Bit Fields
Hex
Dec
1C9H
457
MSR_LASTBRANCH_TOS
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-3) that points to the MSR containing the most
recent branch record. See also:
• MSR_LASTBRANCH_0_FROM_IP (at 40H).
• Section 18.15, “Last Branch, Interrupt, and Exception Recording
(Pentium M Processors).”
1D9H
473
MSR_DEBUGCTLB
Debug Control (R/W)
Controls how several debug features are used. Bit definitions are
discussed in the referenced section.
See Section 18.15, “Last Branch, Interrupt, and Exception Recording
(Pentium M Processors).”
1DDH
477
MSR_LER_TO_LIP
Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the last branch instruction
that the processor executed prior to the last exception that was
generated or the last interrupt that was handled.
See Section 18.15, “Last Branch, Interrupt, and Exception Recording
(Pentium M Processors),” and Section 18.16.2, “Last Branch and Last
Exception MSRs.”
1DEH
478
MSR_LER_FROM_LIP
Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction that the processor
executed prior to the last exception that was generated or the last
interrupt that was handled.
See Section 18.15, “Last Branch, Interrupt, and Exception Recording
(Pentium M Processors),” and Section 18.16.2, “Last Branch and Last
Exception MSRs.”
2FFH
767
IA32_MTRR_DEF_TYPE
Default Memory Types (R/W)
Sets the memory type for the regions of physical memory that are not
mapped by the MTRRs.
See Section 12.11.2.1, “IA32_MTRR_DEF_TYPE MSR.”
400H
1024
IA32_MC0_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
401H
1025
IA32_MC0_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
402H
1026
IA32_MC0_ADDR
See Section 14.3.2.3., “IA32_MCi_ADDR MSRs”.
The IA32_MC0_ADDR register is either not implemented or contains no
address if the ADDRV flag in the IA32_MC0_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR
will cause a general-protection exception.
404H
1028
IA32_MC1_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
405H
1029
IA32_MC1_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
406H
1030
IA32_MC1_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC1_ADDR register is either not implemented or contains no
address if the ADDRV flag in the IA32_MC1_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR
will cause a general-protection exception.
408H
1032
IA32_MC2_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
409H
1033
IA32_MC2_STATUS
See Chapter 16.3.2.2, “IA32_MCi_STATUS MSRS.”
Vol. 4
2-415
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-59. MSRs in Pentium M Processors (Contd.)
Register
Bit Description
Address
Register Name / Bit Fields
Hex
Dec
40AH
1034
IA32_MC2_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or contains no
address if the ADDRV flag in the IA32_MC2_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR
will cause a general-protection exception.
40CH
1036
MSR_MC4_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
40DH
1037
MSR_MC4_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
40EH
1038
MSR_MC4_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or contains no
address if the ADDRV flag in the MSR_MC4_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR
will cause a general-protection exception.
410H
1040
MSR_MC3_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
411H
1041
MSR_MC3_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
412H
1042
MSR_MC3_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or contains no
address if the ADDRV flag in the MSR_MC3_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR
will cause a general-protection exception.
600H
1536
IA32_DS_AREA
DS Save Area (R/W)
See Table 2-2.
Points to the DS buffer management area, which is used to manage the
BTS and PEBS buffers. See Section 20.6.3.4, “Debug Store (DS)
Mechanism.”
31:0
DS Buffer Management Area
Linear address of the first byte of the DS buffer management area.
63:32
Reserved
2.22
MSRS IN THE P6 FAMILY PROCESSORS
The following MSRs are defined for the P6 family processors. The MSRs in this table that are shaded are available
only in the Pentium II and Pentium III processors. Beginning with the Pentium 4 processor, some of the MSRs in this
list have been designated as “architectural” and have had their names changed. See Table 2-2 for a list of the archi-
tectural MSRs.
Table 2-60. MSRs in the P6 Family Processors
Register
Address
Register Name / Bit Fields
Bit Description
Hex
Dec
0H
0
P5_MC_ADDR
See Section 2.23, “MSRs in Pentium Processors.”
1H
1
P5_MC_TYPE
See Section 2.23, “MSRs in Pentium Processors.”
10H
16
TSC
See Section 18.17, “Time-Stamp Counter.”
2-416 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-60. MSRs in the P6 Family Processors (Contd.)
Register
Address
Register Name / Bit Fields
Bit Description
Hex
Dec
17H
23
IA32_PLATFORM_ID
Platform ID (R)
The operating system can use this MSR to determine “slot” information for
the processor and the proper microcode update to load.
49:0
Reserved
52:50
Platform Id (R)
Contains information concerning the intended platform for the processor.
52 51
50
0
0
0 Processor Flag 0
0
0
1 Processor Flag 1
0
1
0 Processor Flag 2
0
1
1 Processor Flag 3
1
0
0 Processor Flag 4
1
0
1 Processor Flag 5
1
1
0 Processor Flag 6
1
1
1 Processor Flag 7
56:53
L2 Cache Latency Read.
59:57
Reserved
60
Clock Frequency Ratio Read.
63:61
Reserved
1BH
27
APIC_BASE
Section 11.4.4, “Local APIC Status and Location.”
7:0
Reserved
8
Boot Strap Processor Indicator Bit
1 = BSP
10:9
Reserved
11
APIC Global Enable Bit - Permanent till reset
1 = Enabled
0 = Disabled
31:12
APIC Base Address.
63:32
Reserved
2AH
42
EBL_CR_POWERON
Processor Hard Power-On Configuration
(R/W) Enables and disables processor features;
(R) indicates current processor configuration.
0
Reserved1
1
Data Error Checking Enable (R/W)
1 = Enabled
0 = Disabled
2
Response Error Checking Enable FRCERR Observation Enable (R/W)
1 = Enabled
0 = Disabled
3
AERR# Drive Enable (R/W)
1 = Enabled
0 = Disabled
Vol. 4
2-417
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-60. MSRs in the P6 Family Processors (Contd.)
Register
Address
Register Name / Bit Fields
Bit Description
Hex
Dec
4
BERR# Enable for Initiator Bus Requests (R/W)
1 = Enabled
0 = Disabled
5
Reserved
6
BERR# Driver Enable for Initiator Internal Errors (R/W)
1 = Enabled
0 = Disabled
7
BINIT# Driver Enable (R/W)
1 = Enabled
0 = Disabled
8
Output Tri-state Enabled (R)
1 = Enabled
0 = Disabled
9
Execute BIST (R)
1 = Enabled
0 = Disabled
10
AERR# Observation Enabled (R)
1 = Enabled
0 = Disabled
11
Reserved
12
BINIT# Observation Enabled (R)
1 = Enabled
0 = Disabled
13
In Order Queue Depth (R)
1 = 1
0 = 8
14
1-MByte Power on Reset Vector (R)
1 = 1MByte
0 = 4GBytes
15
FRC Mode Enable (R)
1 = Enabled
0 = Disabled
17:16
APIC Cluster ID (R)
19:18
System Bus Frequency (R)
00 = 66MHz
10 = 100Mhz
01 = 133MHz
11 = Reserved
21: 20
Symmetric Arbitration ID (R)
25:22
Clock Frequency Ratio (R)
26
Low Power Mode Enable (R/W)
2-418 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-60. MSRs in the P6 Family Processors (Contd.)
Register
Address
Register Name / Bit Fields
Bit Description
Hex
Dec
27
Clock Frequency Ratio
63:28
Reserved1
33H
51
MSR_TEST_CTRL
Test Control Register
29:0
Reserved
30
Streaming Buffer Disable
31
Disable LOCK#
Assertion for split locked access.
79H
121
BIOS_UPDT_TRIG
BIOS Update Trigger Register.
88H
136
BBL_CR_D0[63:0]
Chunk 0 data register D[63:0]: used to write to and read from the L2
89H
137
BBL_CR_D1[63:0]
Chunk 1 data register D[63:0]: used to write to and read from the L2
8AH
138
BBL_CR_D2[63:0]
Chunk 2 data register D[63:0]: used to write to and read from the L2
8BH
139
BIOS_SIGN/BBL_CR_D3[63:0]
BIOS Update Signature Register or Chunk 3 data register D[63:0]
Used to write to and read from the L2 depending on the usage model.
C1H
193
PerfCtr0 (PERFCTR0)
Performance Counter Register
See Table 2-2.
C2H
194
PerfCtr1 (PERFCTR1)
Performance Counter Register
See Table 2-2.
FEH
254
MTRRcap
Memory Type Range Registers
116H
278
BBL_CR_ADDR [63:0]
Address register: used to send specified address (A31-A3) to L2 during
cache initialization accesses.
BBL_CR_ADDR [63:32]
Reserved,
BBL_CR_ADDR [31:3]
Address bits [35:3]
BBL_CR_ADDR [2:0]
Reserved Set to 0.
118H
280
BBL_CR_DECC[63:0]
Data ECC register D[7:0]: used to write ECC and read ECC to/from L2
119H
281
BBL_CR_CTL
Control register: used to program L2 commands to be issued via cache
configuration accesses mechanism. Also receives L2 lookup response
Reserved
BL_CR_CTL[63:22]
Processor number2
BBL_CR_CTL[21]
Disable = 1
Enable = 0
Reserved
Vol. 4
2-419
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-60. MSRs in the P6 Family Processors (Contd.)
Register
Address
Register Name / Bit Fields
Bit Description
Hex
Dec
BBL_CR_CTL[20:19]
User supplied ECC
BBL_CR_CTL[18]
Reserved
BBL_CR_CTL[17]
L2 Hit
BBL_CR_CTL[16]
Reserved
BBL_CR_CTL[15:14]
State from L2
BBL_CR_CTL[13:12]
Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00
Way from L2
BBL_CR_CTL[11:10]
Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11
Way to L2
BBL_CR_CTL[9:8]
Reserved
BBL_CR_CTL[7]
State to L2
BBL_CR_CTL[6:5]
BBL_CR_CTL[4:0]
L2 Command
01100
Data Read w/ LRU update (RLU)
01110
Tag Read w/ Data Read (TRR)
01111
Tag Inquire (TI)
00010
L2 Control Register Read (CR)
00011
L2 Control Register Write (CW)
010 + MESI encode
Tag Write w/ Data Read (TWR)
111 + MESI encode
Tag Write w/ Data Write (TWW)
100 + MESI encode
Tag Write (TW)
11AH
282
BBL_CR_TRIG
Trigger register: used to initiate a cache configuration accesses access,
Write only with Data = 0.
11BH
283
BBL_CR_BUSY
Busy register: indicates when a cache configuration accesses L2 command
is in progress. D[0] = 1 = BUSY
11EH
286
BBL_CR_CTL3
Control register 3: used to configure the L2 Cache
BBL_CR_CTL3[63:26]
Reserved
BBL_CR_CTL3[25]
Cache bus fraction (read only)
BBL_CR_CTL3[24]
Reserved
BBL_CR_CTL3[23]
L2 Hardware Disable (read only)
BBL_CR_CTL3[22:20]
L2 Physical Address Range support
111
64GBytes
110
32GBytes
101
16GBytes
100
8GBytes
011
4GBytes
010
2GBytes
001
1GBytes
000
512MBytes
BBL_CR_CTL3[19]
Reserved
BBL_CR_CTL3[18]
Cache State error checking enable (read/write)
2-420 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-60. MSRs in the P6 Family Processors (Contd.)
Register
Address
Register Name / Bit Fields
Bit Description
Hex
Dec
BBL_CR_CTL3[17:13
Cache size per bank (read/write)
00001
256KBytes
00010
512KBytes
00100
1MByte
01000
2MByte
10000
4MBytes
BBL_CR_CTL3[12:11]
Number of L2 banks (read only)
BBL_CR_CTL3[10:9]
L2 Associativity (read only)
00
Direct Mapped
01
2 Way
10
4 Way
11
Reserved
BBL_CR_CTL3[8]
L2 Enabled (read/write)
BBL_CR_CTL3[7]
CRTN Parity Check Enable (read/write)
BBL_CR_CTL3[6]
Address Parity Check Enable (read/write)
BBL_CR_CTL3[5]
ECC Check Enable (read/write)
BBL_CR_CTL3[4:1]
L2 Cache Latency (read/write)
BBL_CR_CTL3[0]
L2 Configured (read/write
)
174H
372
SYSENTER_CS_MSR
CS register target for CPL 0 code
175H
373
SYSENTER_ESP_MSR
Stack pointer for CPL 0 stack
176H
374
SYSENTER_EIP_MSR
CPL 0 code entry point
179H
377
MCG_CAP
Machine Check Global Control Register
17AH
378
MCG_STATUS
Machine Check Error Reporting Register - contains information related to a
machine-check error if its VAL (valid) flag is set. Software is responsible
for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them;
writing 1s to them causes a general-protection exception.
17BH
379
MCG_CTL
Machine Check Error Reporting Register - controls signaling of #MC for
errors produced by a particular hardware unit (or group of hardware
units).
186H
390
PerfEvtSel0 (EVNTSEL0)
Performance Event Select Register 0 (R/W)
7:0
Event Select
Refer to Performance Counter section for a list of event encodings.
15:8
UMASK (Unit Mask)
Unit mask register set to 0 to enable all count options.
16
USER
Controls the counting of events at Privilege levels of 1, 2, and 3.
17
OS
Controls the counting of events at Privilege level of 0.
Vol. 4
2-421
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-60. MSRs in the P6 Family Processors (Contd.)
Register
Address
Register Name / Bit Fields
Bit Description
Hex
Dec
18
E
Occurrence/Duration Mode Select
1 = Occurrence
0 = Duration
19
PC
Enabled the signaling of performance counter overflow via BP0 pin
20
INT
Enables the signaling of counter overflow via input to APIC
1 = Enable
0 = Disable
22
ENABLE
Enables the counting of performance events in both counters
1 = Enable
0 = Disable
23
INV
Inverts the result of the CMASK condition
1 = Inverted
0 = Non-Inverted
31:24
CMASK (Counter Mask)
187H
391
PerfEvtSel1 (EVNTSEL1)
Performance Event Select for Counter 1 (R/W)
7:0
Event Select
Refer to Performance Counter section for a list of event encodings.
15:8
UMASK (Unit Mask)
Unit mask register set to 0 to enable all count options.
16
USER
Controls the counting of events at Privilege levels of 1, 2, and 3.
17
OS
Controls the counting of events at Privilege level of 0.
18
E
Occurrence/Duration Mode Select.
1 = Occurrence
0 = Duration
19
PC
Enabled the signaling of performance counter overflow via BP0 pin.
2-422 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-60. MSRs in the P6 Family Processors (Contd.)
Register
Address
Register Name / Bit Fields
Bit Description
Hex
Dec
20
INT
Enables the signaling of counter overflow via input to APIC.
1 = Enable
0 = Disable
23
INV
Inverts the result of the CMASK condition.
1 = Inverted
0 = Non-Inverted
31:24
CMASK (Counter Mask)
1D9H
473
DEBUGCTLMSR
Enables last branch, interrupt, and exception recording; taken branch
breakpoints; the breakpoint reporting pins; and trace messages. This
register can be written to using the WRMSR instruction, when operating
at privilege level 0 or when in real-address mode.
0
Enable/Disable Last Branch Records
1
Branch Trap Flag
2
Performance Monitoring/Break Point Pins
3
Performance Monitoring/Break Point Pins
4
Performance Monitoring/Break Point Pins
5
Performance Monitoring/Break Point Pins
6
Enable/Disable Execution Trace Messages
31:7
Reserved
1DBH
475
LASTBRANCHFROMIP
32-bit register for recording the instruction pointers for the last branch,
interrupt, or exception that the processor took prior to a debug exception
being generated.
1DCH
476
LASTBRANCHTOIP
32-bit register for recording the instruction pointers for the last branch,
interrupt, or exception that the processor took prior to a debug exception
being generated.
1DDH
477
LASTINTFROMIP
Last INT from IP
1DEH
478
LASTINTTOIP
Last INT to IP
200H
512
MTRRphysBase0
Memory Type Range Registers
201H
513
MTRRphysMask0
Memory Type Range Registers
202H
514
MTRRphysBase1
Memory Type Range Registers
203H
515
MTRRphysMask1
Memory Type Range Registers
204H
516
MTRRphysBase2
Memory Type Range Registers
205H
517
MTRRphysMask2
Memory Type Range Registers
206H
518
MTRRphysBase3
Memory Type Range Registers
207H
519
MTRRphysMask3
Memory Type Range Registers
208H
520
MTRRphysBase4
Memory Type Range Registers
209H
521
MTRRphysMask4
Memory Type Range Registers
20AH
522
MTRRphysBase5
Memory Type Range Registers
Vol. 4
2-423
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-60. MSRs in the P6 Family Processors (Contd.)
Register
Address
Register Name / Bit Fields
Bit Description
Hex
Dec
20BH
523
MTRRphysMask5
Memory Type Range Registers
20CH
524
MTRRphysBase6
Memory Type Range Registers
20DH
525
MTRRphysMask6
Memory Type Range Registers
20EH
526
MTRRphysBase7
Memory Type Range Registers
20FH
527
MTRRphysMask7
Memory Type Range Registers
250H
592
MTRRfix64K_00000
Memory Type Range Registers
258H
600
MTRRfix16K_80000
Memory Type Range Registers
259H
601
MTRRfix16K_A0000
Memory Type Range Registers
268H
616
MTRRfix4K_C0000
Memory Type Range Registers
269H
617
MTRRfix4K_C8000
Memory Type Range Registers
26AH
618
MTRRfix4K_D0000
Memory Type Range Registers
26BH
619
MTRRfix4K_D8000
Memory Type Range Registers
26CH
620
MTRRfix4K_E0000
Memory Type Range Registers
26DH
621
MTRRfix4K_E8000
Memory Type Range Registers
26EH
622
MTRRfix4K_F0000
Memory Type Range Registers
26FH
623
MTRRfix4K_F8000
Memory Type Range Registers
2FFH
767
MTRRdefType
Memory Type Range Registers
2:0
Default memory type
10
Fixed MTRR enable
11
MTRR Enable
400H
1024
MC0_CTL
Machine Check Error Reporting Register - controls signaling of #MC for
errors produced by a particular hardware unit (or group of hardware
units).
401H
1025
MC0_STATUS
Machine Check Error Reporting Register - contains information related to a
machine-check error if its VAL (valid) flag is set. Software is responsible
for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them;
writing 1s to them causes a general-protection exception.
15:0
MC_STATUS_MCACOD
31:16
MC_STATUS_MSCOD
57
MC_STATUS_DAM
58
MC_STATUS_ADDRV
59
MC_STATUS_MISCV
60
MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is hardcoded to 1.)
61
MC_STATUS_UC
62
MC_STATUS_O
63
MC_STATUS_V
402H
1026
MC0_ADDR
403H
1027
MC0_MISC
Defined in MCA architecture but not implemented in the P6 family
processors.
2-424 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-60. MSRs in the P6 Family Processors (Contd.)
Register
Address
Register Name / Bit Fields
Bit Description
Hex
Dec
404H
1028
MC1_CTL
405H
1029
MC1_STATUS
Bit definitions same as MC0_STATUS.
406H
1030
MC1_ADDR
407H
1031
MC1_MISC
Defined in MCA architecture but not implemented in the P6 family
processors.
408H
1032
MC2_CTL
409H
1033
MC2_STATUS
Bit definitions same as MC0_STATUS.
40AH
1034
MC2_ADDR
40BH
1035
MC2_MISC
Defined in MCA architecture but not implemented in the P6 family
processors.
40CH
1036
MC4_CTL
40DH
1037
MC4_STATUS
Bit definitions same as MC0_STATUS, except bits 0, 4, 57, and 61 are
hardcoded to 1.
40EH
1038
MC4_ADDR
Defined in MCA architecture but not implemented in P6 Family processors.
40FH
1039
MC4_MISC
Defined in MCA architecture but not implemented in the P6 family
processors.
410H
1040
MC3_CTL
411H
1041
MC3_STATUS
Bit definitions same as MC0_STATUS.
412H
1042
MC3_ADDR
413H
1043
MC3_MISC
Defined in MCA architecture but not implemented in the P6 family
processors.
NOTES
1.Bit 0 of this register has been redefined several times, and is no longer used in P6 family processors.
2.The processor number feature may be disabled by setting bit 21 of the BBL_CR_CTL MSR (model-specific register address 119h)
to “1”. Once set, bit 21 of the BBL_CR_CTL may not be cleared. This bit is write-once. The processor number feature will be disabled
until the processor is reset.
3.The Pentium III processor will prevent FSB frequency overclocking with a new shutdown mechanism. If the FSB frequency
selected is greater than the internal FSB frequency the processor will shutdown. If the FSB selected is less than the internal FSB
frequency the BIOS may choose to use bit 11 to implement its own shutdown policy.
2.23
MSRS IN PENTIUM PROCESSORS
The following MSRs are defined for the Pentium processors. The P5_MC_ADDR, P5_MC_TYPE, and TSC MSRs
(named IA32_P5_MC_ADDR, IA32_P5_MC_TYPE, and IA32_TIME_STAMP_COUNTER in the Pentium 4 processor)
are architectural; that is, code that accesses these registers will run on Pentium 4 and P6 family processors without
generating exceptions (see Section 2.1, “Architectural MSRs”). The CESR, CTR0, and CTR1 MSRs are unique to
Pentium processors; code that accesses these registers will generate exceptions on Pentium 4 and P6 family
processors.
Vol. 4
2-425
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-61. MSRs in the Pentium Processor
Register
Address
Hex
Dec
Register Name
Bit Description
0H
0
P5_MC_ADDR
See Section 16.10.2, “Pentium Processor Machine-Check Exception Handling.”
1H
1
P5_MC_TYPE
See Section 16.10.2, “Pentium Processor Machine-Check Exception Handling.”
10H
16
TSC
See Section 18.17, “Time-Stamp Counter.”
11H
17
CESR
See Section 20.6.9.1, “Control and Event Select Register (CESR).”
12H
18
CTR0
Section 20.6.9.3, “Events Counted.”
13H
19
CTR1
Section 20.6.9.3, “Events Counted.”
2.24
MSR INDEX
MSRs of recent processors are indexed here for convenience. IA32 MSRs are excluded from this index.
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_ALF_ESCR0
0FH
See Table 2-55
MSR_ALF_ESCR1
0FH
See Table 2-55
MSR_ANY_CORE_C0
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_ANY_GFXE_C0
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_B0_PMON_BOX_CTRL
06_2EH
See Table 2-17
MSR_B0_PMON_BOX_OVF_CTRL
06_2EH
See Table 2-17
MSR_B0_PMON_BOX_STATUS
06_2EH
See Table 2-17
MSR_B0_PMON_CTR0
06_2EH
See Table 2-17
MSR_B0_PMON_CTR1
06_2EH
See Table 2-17
MSR_B0_PMON_CTR2
06_2EH
See Table 2-17
MSR_B0_PMON_CTR3
06_2EH
See Table 2-17
MSR_B0_PMON_EVNT_SEL0
06_2EH
See Table 2-17
2-426 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_B0_PMON_EVNT_SEL1
06_2EH
See Table 2-17
MSR_B0_PMON_EVNT_SEL2
06_2EH
See Table 2-17
MSR_B0_PMON_EVNT_SEL3
06_2EH
See Table 2-17
MSR_B0_PMON_MASK
06_2EH
See Table 2-17
MSR_B0_PMON_MATCH
06_2EH
See Table 2-17
MSR_B1_PMON_BOX_CTRL
06_2EH
See Table 2-17
MSR_B1_PMON_BOX_OVF_CTRL
06_2EH
See Table 2-17
MSR_B1_PMON_BOX_STATUS
06_2EH
See Table 2-17
MSR_B1_PMON_CTR0
06_2EH
See Table 2-17
MSR_B1_PMON_CTR1
06_2EH
See Table 2-17
MSR_B1_PMON_CTR2
06_2EH
See Table 2-17
MSR_B1_PMON_CTR3
06_2EH
See Table 2-17
MSR_B1_PMON_EVNT_SEL0
06_2EH
See Table 2-17
MSR_B1_PMON_EVNT_SEL1
06_2EH
See Table 2-17
MSR_B1_PMON_EVNT_SEL2
06_2EH
See Table 2-17
MSR_B1_PMON_EVNT_SEL3
06_2EH
See Table 2-17
MSR_B1_PMON_MASK
06_2EH
See Table 2-17
MSR_B1_PMON_MATCH
06_2EH
See Table 2-17
MSR_BBL_CR_CTL
06_09H
See Table 2-59
MSR_BBL_CR_CTL3
06_0FH, 06_17H
See Table 2-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
Vol. 4
2-427
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_0EH
See Table 2-58
06_09H
See Table 2-59
MSR_BIOS_DEBUG
06_8CH, 06_8DH
See Table 2-45
MSR_BIOS_DONE
06_7DH, 06_7EH
See Table 2-44
MSR_BIOS_MCU_ERRORCODE
06_7DH, 06_7EH
See Table 2-44
06_8CH, 06_8DH
See Table 2-45
MSR_BPU_CCCR0
0FH
See Table 2-55
MSR_BPU_CCCR1
0FH
See Table 2-55
MSR_BPU_CCCR2
0FH
See Table 2-55
MSR_BPU_CCCR3
0FH
See Table 2-55
MSR_BPU_COUNTER0
0FH
See Table 2-55
MSR_BPU_COUNTER1
0FH
See Table 2-55
MSR_BPU_COUNTER2
0FH
See Table 2-55
MSR_BPU_COUNTER3
0FH
See Table 2-55
MSR_BPU_ESCR0
0FH
See Table 2-55
MSR_BPU_ESCR1
0FH
See Table 2-55
MSR_BR_DETECT_COUNTER_CONFIG_i
06_66H
See Table 2-42
MSR_BR_DETECT_CTRL
06_66H
See Table 2-42
MSR_BR_DETECT_STATUS
06_66H
See Table 2-42
MSR_BSU_ESCR0
0FH
See Table 2-55
MSR_BSU_ESCR1
0FH
See Table 2-55
MSR_C0_PMON_BOX_CTRL
06_2EH
See Table 2-17
06_2DH
See Table 2-24
2-428 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3FH
See Table 2-33
MSR_C0_PMON_BOX_FILTER
06_2DH
See Table 2-24
MSR_C0_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C0_PMON_BOX_FILTER1
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C0_PMON_BOX_OVF_CTRL
06_2EH
See Table 2-17
MSR_C0_PMON_BOX_STATUS
06_2EH
See Table 2-17
06_3FH
See Table 2-33
MSR_C0_PMON_CTR0
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C0_PMON_CTR1
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C0_PMON_CTR2
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C0_PMON_CTR3
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C0_PMON_CTR4
06_2EH
See Table 2-17
MSR_C0_PMON_CTR5
06_2EH
See Table 2-17
MSR_C0_PMON_EVNT_SEL0
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C0_PMON_EVNT_SEL1
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C0_PMON_CTR1
Vol. 4
2-429
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C0_PMON_EVNT_SEL2
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C0_PMON_CTR2
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C0_PMON_EVNT_SEL3
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C0_PMON_EVNT_SEL4
06_2EH
See Table 2-17
MSR_C0_PMON_EVNT_SEL5
06_2EH
See Table 2-17
MSR_C1_PMON_BOX_CTRL
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C1_PMON_BOX_FILTER
06_2DH
See Table 2-24
MSR_C1_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C1_PMON_BOX_FILTER1
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C1_PMON_BOX_OVF_CTRL
06_2EH
See Table 2-17
MSR_C1_PMON_BOX_STATUS
06_2EH
See Table 2-17
06_3FH
See Table 2-33
MSR_C1_PMON_CTR0
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C1_PMON_CTR1
06_2EH
See Table 2-17
06_2DH
See Table 2-24
2-430 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_3FH
See Table 2-33
MSR_C1_PMON_CTR2
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C1_PMON_CTR3
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C1_PMON_CTR4
06_2EH
See Table 2-17
MSR_C1_PMON_CTR5
06_2EH
See Table 2-17
MSR_C1_PMON_EVNT_SEL0
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C1_PMON_EVNT_SEL1
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C1_PMON_EVNT_SEL2
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C1_PMON_EVNT_SEL3
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C1_PMON_EVNT_SEL4
06_2EH
See Table 2-17
MSR_C1_PMON_EVNT_SEL5
06_2EH
See Table 2-17
MSR_C10_PMON_BOX_FILTER
06_3EH
See Table 2-28
MSR_C10_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C10_PMON_BOX_FILTER1
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C11_PMON_BOX_FILTER
06_3EH
See Table 2-28
Vol. 4
2-431
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_C11_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C11_PMON_BOX_FILTER1
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C12_PMON_BOX_FILTER
06_3EH
See Table 2-28
MSR_C12_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C12_PMON_BOX_FILTER1
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C13_PMON_BOX_FILTER
06_3EH
See Table 2-28
MSR_C13_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C13_PMON_BOX_FILTER1
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C14_PMON_BOX_FILTER
06_3EH
See Table 2-28
MSR_C14_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C14_PMON_BOX_FILTER1
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C15_PMON_BOX_CTL
06_3FH
See Table 2-33
MSR_C15_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C15_PMON_BOX_FILTER1
06_3FH
See Table 2-33
MSR_C15_PMON_BOX_STATUS
06_3FH
See Table 2-33
MSR_C15_PMON_CTR0
06_3FH
See Table 2-33
MSR_C15_PMON_CTR1
06_3FH
See Table 2-33
MSR_C15_PMON_CTR2
06_3FH
See Table 2-33
MSR_C15_PMON_CTR3
06_3FH
See Table 2-33
2-432 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_C15_PMON_EVNTSEL0
06_3FH
See Table 2-33
MSR_C15_PMON_EVNTSEL1
06_3FH
See Table 2-33
MSR_C15_PMON_EVNTSEL2
06_3FH
See Table 2-33
MSR_C15_PMON_EVNTSEL3
06_3FH
See Table 2-33
MSR_C16_PMON_BOX_CTL
06_3FH
See Table 2-33
MSR_C16_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C16_PMON_BOX_FILTER1
06_3FH
See Table 2-33
MSR_C16_PMON_BOX_STATUS
06_3FH
See Table 2-33
MSR_C16_PMON_CTR0
06_3FH
See Table 2-33
MSR_C16_PMON_CTR3
06_3FH
See Table 2-33
MSR_C16_PMON_CTR2
06_3FH
See Table 2-33
MSR_C16_PMON_CTR3
06_3FH
See Table 2-33
MSR_C16_PMON_EVNTSEL0
06_3FH
See Table 2-33
MSR_C16_PMON_EVNTSEL1
06_3FH
See Table 2-33
MSR_C16_PMON_EVNTSEL2
06_3FH
See Table 2-33
MSR_C16_PMON_EVNTSEL3
06_3FH
See Table 2-33
MSR_C17_PMON_BOX_CTL
06_3FH
See Table 2-33
MSR_C17_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C17_PMON_BOX_FILTER1
06_3FH
See Table 2-33
MSR_C17_PMON_BOX_STATUS
06_3FH
See Table 2-33
MSR_C17_PMON_CTR0
06_3FH
See Table 2-33
Vol. 4
2-433
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_C17_PMON_CTR1
06_3FH
See Table 2-33
MSR_C17_PMON_CTR2
06_3FH
See Table 2-33
MSR_C17_PMON_CTR3
06_3FH
See Table 2-33
MSR_C17_PMON_EVNTSEL0
06_3FH
See Table 2-33
MSR_C17_PMON_EVNTSEL1
06_3FH
See Table 2-33
MSR_C17_PMON_EVNTSEL2
06_3FH
See Table 2-33
MSR_C17_PMON_EVNTSEL3
06_3FH
See Table 2-33
MSR_C2_PMON_BOX_CTRL
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C2_PMON_BOX_FILTER
06_2DH
See Table 2-24
MSR_C2_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C2_PMON_BOX_FILTER1
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C2_PMON_BOX_OVF_CTRL
06_2EH
See Table 2-17
MSR_C2_PMON_BOX_STATUS
06_2EH
See Table 2-17
06_3FH
See Table 2-33
MSR_C2_PMON_CTR0
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C2_PMON_CTR1
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C2_PMON_CTR2
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
2-434 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_C2_PMON_CTR3
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C2_PMON_CTR4
06_2EH
See Table 2-17
MSR_C2_PMON_CTR5
06_2EH
See Table 2-17
MSR_C2_PMON_EVNT_SEL0
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C2_PMON_EVNT_SEL1
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C2_PMON_EVNT_SEL2
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C2_PMON_EVNT_SEL3
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C2_PMON_EVNT_SEL4
06_2EH
See Table 2-17
MSR_C2_PMON_EVNT_SEL5
06_2EH
See Table 2-17
MSR_C3_PMON_BOX_CTRL
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C3_PMON_BOX_FILTER
06_2DH
See Table 2-24
MSR_C3_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C3_PMON_BOX_FILTER1
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C3_PMON_BOX_OVF_CTRL
06_2EH
See Table 2-17
MSR_C3_PMON_BOX_STATUS
Vol. 4
2-435
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2EH
See Table 2-17
06_3FH
See Table 2-33
MSR_C3_PMON_CTR0
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C3_PMON_CTR1
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C3_PMON_CTR2
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C3_PMON_CTR3
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C3_PMON_CTR4
06_2EH
See Table 2-17
MSR_C3_PMON_CTR5
06_2EH
See Table 2-17
MSR_C3_PMON_EVNT_SEL0
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C3_PMON_EVNT_SEL1
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C3_PMON_EVNT_SEL2
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C3_PMON_EVNT_SEL3
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C3_PMON_EVNT_SEL4
06_2EH
See Table 2-17
MSR_C3_PMON_EVNT_SEL5
06_2EH
See Table 2-17
2-436 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_C4_PMON_BOX_CTRL
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C4_PMON_BOX_FILTER
06_2DH
See Table 2-24
MSR_C4_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C4_PMON_BOX_FILTER1
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C4_PMON_BOX_OVF_CTRL
06_2EH
See Table 2-17
MSR_C4_PMON_BOX_STATUS
06_2EH
See Table 2-17
06_3FH
See Table 2-33
MSR_C4_PMON_CTR0
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C4_PMON_CTR1
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C4_PMON_CTR2
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C4_PMON_CTR3
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C4_PMON_CTR4
06_2EH
See Table 2-17
MSR_C4_PMON_CTR5
06_2EH
See Table 2-17
MSR_C4_PMON_EVNT_SEL0
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C4_PMON_EVNT_SEL1
06_2EH
See Table 2-17
Vol. 4
2-437
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C4_PMON_EVNT_SEL2
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C4_PMON_EVNT_SEL3
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C4_PMON_EVNT_SEL4
06_2EH
See Table 2-17
MSR_C4_PMON_EVNT_SEL5
06_2EH
See Table 2-17
MSR_C5_PMON_BOX_CTRL
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C5_PMON_BOX_FILTER
06_2DH
See Table 2-24
MSR_C5_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C5_PMON_BOX_FILTER1
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C5_PMON_BOX_OVF_CTRL
06_2EH
See Table 2-17
MSR_C5_PMON_BOX_STATUS
06_2EH
See Table 2-17
06_3FH
See Table 2-33
MSR_C5_PMON_CTR0
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C5_PMON_CTR1
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C5_PMON_CTR2
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
2-438 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_C5_PMON_CTR3
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C5_PMON_CTR4
06_2EH
See Table 2-17
MSR_C5_PMON_CTR5
06_2EH
See Table 2-17
MSR_C5_PMON_EVNT_SEL0
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C5_PMON_EVNT_SEL1
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C5_PMON_EVNT_SEL2
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C5_PMON_EVNT_SEL3
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C5_PMON_EVNT_SEL4
06_2EH
See Table 2-17
MSR_C5_PMON_EVNT_SEL5
06_2EH
See Table 2-17
MSR_C6_PMON_BOX_CTRL
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C6_PMON_BOX_FILTER
06_2DH
See Table 2-24
MSR_C6_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C6_PMON_BOX_FILTER1
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C6_PMON_BOX_OVF_CTRL
06_2EH
See Table 2-17
MSR_C6_PMON_BOX_STATUS
Vol. 4
2-439
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2EH
See Table 2-17
06_3FH
See Table 2-33
MSR_C6_PMON_CTR0
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C6_PMON_CTR1
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C6_PMON_CTR2
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C6_PMON_CTR3
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C6_PMON_CTR4
06_2EH
See Table 2-17
MSR_C6_PMON_CTR5
06_2EH
See Table 2-17
MSR_C6_PMON_EVNT_SEL0
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C6_PMON_EVNT_SEL1
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C6_PMON_EVNT_SEL2
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C6_PMON_EVNT_SEL3
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C6_PMON_EVNT_SEL4
06_2EH
See Table 2-17
MSR_C6_PMON_EVNT_SEL5
06_2EH
See Table 2-17
2-440 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_C7_PMON_BOX_CTRL
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C7_PMON_BOX_FILTER
06_2DH
See Table 2-24
MSR_C7_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C7_PMON_BOX_FILTER1
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C7_PMON_BOX_OVF_CTRL
06_2EH
See Table 2-17
MSR_C7_PMON_BOX_STATUS
06_2EH
See Table 2-17
06_3FH
See Table 2-33
MSR_C7_PMON_CTR0
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C7_PMON_CTR1
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C7_PMON_CTR2
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C7_PMON_CTR3
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C7_PMON_CTR4
06_2EH
See Table 2-17
MSR_C7_PMON_CTR5
06_2EH
See Table 2-17
MSR_C7_PMON_EVNT_SEL0
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C7_PMON_EVNT_SEL1
06_2EH
See Table 2-17
Vol. 4
2-441
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C7_PMON_EVNT_SEL2
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C7_PMON_EVNT_SEL3
06_2EH
See Table 2-17
06_2DH
See Table 2-24
06_3FH
See Table 2-33
MSR_C7_PMON_EVNT_SEL4
06_2EH
See Table 2-17
MSR_C7_PMON_EVNT_SEL5
06_2EH
See Table 2-17
MSR_C8_PMON_BOX_CTRL
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C8_PMON_BOX_FILTER
06_3EH
See Table 2-28
MSR_C8_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C8_PMON_BOX_FILTER1
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C8_PMON_BOX_OVF_CTRL
06_2FH
See Table 2-19
MSR_C8_PMON_BOX_STATUS
06_2FH
See Table 2-19
06_3FH
See Table 2-33
MSR_C8_PMON_CTR0
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C8_PMON_CTR1
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C8_PMON_CTR2
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
2-442 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_C8_PMON_CTR3
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C8_PMON_CTR4
06_2FH
See Table 2-19
MSR_C8_PMON_CTR5
06_2FH
See Table 2-19
MSR_C8_PMON_EVNT_SEL0
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C8_PMON_EVNT_SEL1
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C8_PMON_EVNT_SEL2
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C8_PMON_EVNT_SEL3
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C8_PMON_EVNT_SEL4
06_2FH
See Table 2-19
MSR_C8_PMON_EVNT_SEL5
06_2FH
See Table 2-19
MSR_C9_PMON_BOX_CTRL
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C9_PMON_BOX_FILTER
06_3EH
See Table 2-28
MSR_C9_PMON_BOX_FILTER0
06_3FH
See Table 2-33
MSR_C9_PMON_BOX_FILTER1
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C9_PMON_BOX_OVF_CTRL
06_2FH
See Table 2-19
MSR_C9_PMON_BOX_STATUS
Vol. 4
2-443
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2FH
See Table 2-19
06_3FH
See Table 2-33
MSR_C9_PMON_CTR0
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C9_PMON_CTR1
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C9_PMON_CTR2
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C9_PMON_CTR3
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C9_PMON_CTR4
06_2FH
See Table 2-19
MSR_C9_PMON_CTR5
06_2FH
See Table 2-19
MSR_C9_PMON_EVNT_SEL0
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C9_PMON_EVNT_SEL1
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C9_PMON_EVNT_SEL2
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C9_PMON_EVNT_SEL3
06_2FH
See Table 2-19
06_3EH
See Table 2-28
06_3FH
See Table 2-33
MSR_C9_PMON_EVNT_SEL4
06_2FH
See Table 2-19
MSR_C9_PMON_EVNT_SEL5
06_2FH
See Table 2-19
2-444 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_CC6_DEMOTION_POLICY_CONFIG
06_37H
See Table 2-9
MSR_CONFIG_TDP_CONTROL
06_3AH
See Table 2-25
06_3CH, 06_45H, 06_46H
See Table 2-29
06_57H, 06_85H
See Table 2-53
MSR_CONFIG_TDP_LEVEL1
06_3AH
See Table 2-25
06_3CH, 06_45H, 06_46H
See Table 2-29
06_57H, 06_85H
See Table 2-53
MSR_CONFIG_TDP_LEVEL2
06_3AH
See Table 2-25
06_3CH, 06_45H, 06_46H
See Table 2-29
06_57H, 06_85H
See Table 2-53
MSR_CONFIG_TDP_NOMINAL
06_3AH
See Table 2-25
06_3CH, 06_45H, 06_46H
See Table 2-29
06_57H, 06_85H
See Table 2-53
MSR_CORE_C1_RESIDENCY
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH
See Table 2-6
06_66H
See Table 2-42
MSR_CORE_C3_RESIDENCY
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH, 06_25H, 06_2CH, 06_2FH
See Table 2-15
06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H
See Table 2-20
MSR_CORE_C6_RESIDENCY
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH
See Table 2-6
06_1AH, 06_1EH, 06_1FH, 06_2EH, 06_25H, 06_2CH, 06_2FH
See Table 2-15
06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H
See Table 2-20
06_57H, 06_85H
See Table 2-53
MSR_CORE_C7_RESIDENCY
06_2AH, 06_2DH, 06_3AH, 06_3CH, 06_3EH, 06_3FH, 06_45H, 06_46H
See Table 2-20
MSR_CORE_GFXE_OVERLAP_C0
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_CORE_HDC_RESIDENCY
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_CORE_PERF_LIMIT_REASONS
06_5CH, 06_7AH
See Table 2-12
06_3CH, 06_45H, 06_46H
See Table 2-30
06_3F
See Table 2-32
Vol. 4
2-445
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_56H, 06_4FH
See Table 2-36
06_57H, 06_85H
See Table 2-53
MSR_CORE_THREAD_COUNT
06_3FH
See Table 2-32
MSR_CRASHLOG_CONTROL
06_7DH, 06_7EH
See Table 2-44
MSR_CRU_ESCR0
0FH
See Table 2-55
MSR_CRU_ESCR1
0FH
See Table 2-55
MSR_CRU_ESCR2
0FH
See Table 2-55
MSR_CRU_ESCR3
0FH
See Table 2-55
MSR_CRU_ESCR4
0FH
See Table 2-55
MSR_CRU_ESCR5
0FH
See Table 2-55
MSR_DAC_ESCR0
0FH
See Table 2-55
MSR_DAC_ESCR1
0FH
See Table 2-55
MSR_DRAM_ENERGY_ STATUS
06_5CH, 06_7AH
See Table 2-12
06_2DH
See Table 2-23
06_3EH, 06_3FH
See Table 2-26
06_3CH, 06_45H, 06_46H
See Table 2-29
06_3F
See Table 2-32
06_56H, 06_4FH
See Table 2-36
06_6AH, 06_6CH
See Table 2-51
06_57H, 06_85H
See Table 2-53
MSR_DRAM_PERF_STATUS
06_5CH, 06_7AH
See Table 2-12
06_2DH
See Table 2-23
06_3EH, 06_3FH
See Table 2-26
06_3CH, 06_45H, 06_46H
See Table 2-29
06_3F
See Table 2-32
06_56H, 06_4FH
See Table 2-36
06_6AH, 06_6CH
See Table 2-51
06_57H, 06_85H
See Table 2-53
MSR_DRAM_POWER_INFO
06_5CH, 06_7AH
See Table 2-12
2-446 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2DH
See Table 2-23
06_3EH, 06_3FH
See Table 2-26
06_3F
See Table 2-32
06_56H, 06_4FH
See Table 2-36
06_6AH, 06_6CH
See Table 2-51
06_57H, 06_85H
See Table 2-53
MSR_DRAM_POWER_LIMIT
06_5CH, 06_7AH
See Table 2-12
06_2DH
See Table 2-23
06_3EH, 06_3FH
See Table 2-26
06_3F
See Table 2-32
06_56H, 06_4FH
See Table 2-36
06_6AH, 06_6CH
See Table 2-51
06_57H, 06_85H
See Table 2-53
MSR_EBC_FREQUENCY_ID
0FH
See Table 2-55
MSR_EBC_HARD_POWERON
0FH
See Table 2-55
MSR_EBC_SOFT_POWERON
0FH
See Table 2-55
MSR_EBL_CR_POWERON
06_0FH, 06_17H
See Table 2-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH
See Table 2-6
06_0EH
See Table 2-58
06_09H
See Table 2-59
MSR_EFSB_DRDY0
0F_03H, 0F_04H
See Table 2-56
MSR_EFSB_DRDY1
0F_03H, 0F_04H
See Table 2-56
MSR_EMON_L3_CTR_CTL0
06_0FH, 06_17H
See Table 2-3
0F_06H
See Table 2-57
MSR_EMON_L3_CTR_CTL1
06_0FH, 06_17H
See Table 2-3
0F_06H
See Table 2-57
MSR_EMON_L3_CTR_CTL2
06_0FH, 06_17H
See Table 2-3
0F_06H
See Table 2-57
MSR_EMON_L3_CTR_CTL3
06_0FH, 06_17H
See Table 2-3
0F_06H
See Table 2-57
Vol. 4
2-447
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_EMON_L3_CTR_CTL4
06_0FH, 06_17H
See Table 2-3
0F_06H
See Table 2-57
MSR_EMON_L3_CTR_CTL5
06_0FH, 06_17H
See Table 2-3
0F_06H
See Table 2-57
MSR_EMON_L3_CTR_CTL6
06_0FH, 06_17H
See Table 2-3
0F_06H
See Table 2-57
MSR_EMON_L3_CTR_CTL7
06_0FH, 06_17H
See Table 2-3
0F_06H
See Table 2-57
MSR_EMON_L3_GL_CTL
06_0FH, 06_17H
See Table 2-3
MSR_ERROR_CONTROL
06_2DH
See Table 2-23
06_3EH
See Table 2-26
06_3F
See Table 2-32
MSR_FAST_UNCORE_MSRS_CAPABILITY
06_7DH, 06_7EH
See Table 2-44
MSR_FAST_UNCORE_MSRS_CTL
06_7DH, 06_7EH
See Table 2-44
MSR_FAST_UNCORE_MSRS_STATUS
06_7DH, 06_7EH
See Table 2-44
MSR_FEATURE_CONFIG
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH
See Table 2-6
06_25H, 06_2CH
See Table 2-18
06_2FH
See Table 2-19
06_2AH, 06_2DH
See Table 2-20
06_57H, 06_85H
See Table 2-53
MSR_FIRM_ESCR0
0FH
See Table 2-55
MSR_FIRM_ESCR1
0FH
See Table 2-55
MSR_FLAME_CCCR0
0FH
See Table 2-55
MSR_FLAME_CCCR1
0FH
See Table 2-55
MSR_FLAME_CCCR2
0FH
See Table 2-55
MSR_FLAME_CCCR3
0FH
See Table 2-55
2-448 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_FLAME_COUNTER0
0FH
See Table 2-55
MSR_FLAME_COUNTER1
0FH
See Table 2-55
MSR_FLAME_COUNTER2
0FH
See Table 2-55
MSR_FLAME_COUNTER3
0FH
See Table 2-55
MSR_FLAME_ESCR0
0FH
See Table 2-55
MSR_FLAME_ESCR1
0FH
See Table 2-55
MSR_FSB_ESCR0
0FH
See Table 2-55
MSR_FSB_ESCR1
0FH
See Table 2-55
MSR_FSB_FREQ
06_0FH, 06_17H
See Table 2-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_4CH
See Table 2-11
06_0EH
See Table 2-58
MSR_GQ_SNOOP_MESF
06_1AH, 06_1EH, 06_1FH, 06_25H, 06_2CH
See Table 2-16
MSR_GRAPHICS_PERF_LIMIT_REASONS
06_3CH, 06_45H, 06_46H
See Table 2-30
MSR_IFSB_BUSQ0
0F_03H, 0F_04H
See Table 2-56
MSR_IFSB_BUSQ1
0F_03H, 0F_04H
See Table 2-56
MSR_IFSB_CNTR7
0F_03H, 0F_04H
See Table 2-56
MSR_IFSB_CTL6
0F_03H, 0F_04H
See Table 2-56
MSR_IFSB_SNPQ0
0F_03H, 0F_04H
See Table 2-56
MSR_IFSB_SNPQ1
0F_03H, 0F_04H
See Table 2-56
MSR_IQ_CCCR0
0FH
See Table 2-55
MSR_IQ_CCCR1
0FH
See Table 2-55
Vol. 4
2-449
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_IQ_CCCR2
0FH
See Table 2-55
MSR_IQ_CCCR3
0FH
See Table 2-55
MSR_IQ_CCCR4
0FH
See Table 2-55
MSR_IQ_CCCR5
0FH
See Table 2-55
MSR_IQ_COUNTER0
0FH
See Table 2-55
MSR_IQ_COUNTER1
0FH
See Table 2-55
MSR_IQ_COUNTER2
0FH
See Table 2-55
MSR_IQ_COUNTER3
0FH
See Table 2-55
MSR_IQ_COUNTER4
0FH
See Table 2-55
MSR_IQ_COUNTER5
0FH
See Table 2-55
MSR_IQ_ESCR0
0FH
See Table 2-55
MSR_IQ_ESCR1
0FH
See Table 2-55
MSR_IS_ESCR0
0FH
See Table 2-55
MSR_IS_ESCR1
0FH
See Table 2-55
MSR_ITLB_ESCR0
0FH
See Table 2-55
MSR_ITLB_ESCR1
0FH
See Table 2-55
MSR_IX_ESCR0
0FH
See Table 2-55
MSR_IX_ESCR1
0FH
See Table 2-55
MSR_LASTBRANCH_0
0FH
See Table 2-55
06_0EH
See Table 2-58
06_09H
See Table 2-59
MSR_LASTBRANCH_0_FROM_IP
06_0FH, 06_17H
See Table 2-3
2-450 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH
See Table 2-12
06_7AH
See Table 2-13
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_0_TO_IP
06_0FH, 06_17H
See Table 2-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH
See Table 2-12
06_7AH
See Table 2-13
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_1_FROM_IP
06_0FH, 06_17H
See Table 2-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_1_TO_IP
06_0FH, 06_17H
See Table 2-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_10_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_10_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
Vol. 4
2-451
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_LASTBRANCH_11_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_11_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_12_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_12_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_13_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_13_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_14_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_14_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_15_FROM_IP
06_5CH, 06_7AH
See Table 2-12
2-452 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_15_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_16_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_16_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_17_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_17_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_18_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_18_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_19_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_19_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_2
0FH
See Table 2-55
06_0EH
See Table 2-58
06_09H
See Table 2-59
Vol. 4
2-453
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_LASTBRANCH_2_FROM_IP
06_0FH, 06_17H
See Table 2-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_2_TO_IP
06_0FH, 06_17H
See Table 2-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_20_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_20_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_21_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_21_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_22_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_22_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_23_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
2-454 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_LASTBRANCH_23_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_24_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_24_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_25_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_25_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_26_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_26_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_27_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_27_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_28_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_28_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_29_FROM_IP
Vol. 4
2-455
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_29_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_3
0FH
See Table 2-55
06_0EH
See Table 2-58
06_09H
See Table 2-59
MSR_LASTBRANCH_3_FROM_IP
06_0FH, 06_17H
See Table 2-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_3_TO_IP
06_0FH, 06_17H
See Table 2-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_30_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_30_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_31_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
MSR_LASTBRANCH_31_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
2-456 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
MSR_LASTBRANCH_4
06_0EH
See Table 2-58
06_09H
See Table 2-59
MSR_LASTBRANCH_4_FROM_IP
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_4_TO_IP
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_5
06_0EH
See Table 2-58
06_09H
See Table 2-59
MSR_LASTBRANCH_5_FROM_IP
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_5_TO_IP
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_6
06_0EH
See Table 2-58
06_09H
See Table 2-59
MSR_LASTBRANCH_6_FROM_IP
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
Vol. 4
2-457
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_6_TO_IP
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_7
06_0EH
See Table 2-58
06_09H
See Table 2-59
MSR_LASTBRANCH_7_FROM_IP
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_7_TO_IP
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_8_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_8_TO_IP
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_9_FROM_IP
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_9_TO_IP
2-458 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
0FH
See Table 2-55
MSR_LASTBRANCH_TOS
06_0FH, 06_17H
See Table 2-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_57H, 06_85H
See Table 2-53
06_0EH
See Table 2-58
06_09H
See Table 2-59
MSR_LASTBRANCH_INFO_0
06_7AH
See Table 2-13
MSR_LBR_INFO_1
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_10
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_11
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_12
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_13
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_14
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_15
Vol. 4
2-459
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_16
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_17
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_18
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_19
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_2
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_20
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_21
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_22
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_23
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_24
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_25
2-460 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_26
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_27
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_28
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_29
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_3
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_30
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_31
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_4
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_5
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_6
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_7
Vol. 4
2-461
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_8
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_INFO_9
06_4EH, 06_5EH, 06_55H, 06_8EH, 06_9EH, 06_66H, 06_7DH, 06_7EH, 06_8CH, 06_8DH,
See Table 2-39
06_6AH, 06_6CH
06_7AH
See Table 2-13
MSR_LBR_SELECT
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH
See Table 2-7
06_5CH, 06_7AH
See Table 2-12
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
06_3CH, 06_45H, 06_46H
See Table 2-29
06_57H, 06_85H
See Table 2-53
MSR_LER_FROM_LIP
06_0FH, 06_17H
See Table 2-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH
See Table 2-6
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
06_57H, 06_85H
See Table 2-53
0FH
See Table 2-55
06_0EH
See Table 2-58
06_09H
See Table 2-59
MSR_LER_TO_LIP
06_0FH, 06_17H
See Table 2-3
06_1CH, 06_26H, 06_27H, 06_35H, 06_36H
See Table 2-4
06_37H, 06_4AH, 06_4DH, 06_5AH, 06_5DH, 06_5CH, 06_7AH
See Table 2-6
06_1AH, 06_1EH, 06_1FH, 06_2EH
See Table 2-15
06_2AH, 06_2DH
See Table 2-20
06_57H, 06_85H
See Table 2-53
0FH
See Table 2-55
06_0EH
See Table 2-58
06_09H
See Table 2-59
MSR_M0_PMON_ADDR_MASK
06_2EH
See Table 2-17
MSR_M0_PMON_ADDR_MATCH
06_2EH
See Table 2-17
MSR_M0_PMON_BOX_CTRL
2-462 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2EH
See Table 2-17
MSR_M0_PMON_BOX_OVF_CTRL
06_2EH
See Table 2-17
MSR_M0_PMON_BOX_STATUS
06_2EH
See Table 2-17
MSR_M0_PMON_CTR0
06_2EH
See Table 2-17
MSR_M0_PMON_CTR1
06_2EH
See Table 2-17
MSR_M0_PMON_CTR2
06_2EH
See Table 2-17
MSR_M0_PMON_CTR3
06_2EH
See Table 2-17
MSR_M0_PMON_CTR4
06_2EH
See Table 2-17
MSR_M0_PMON_CTR5
06_2EH
See Table 2-17
MSR_M0_PMON_DSP
06_2EH
See Table 2-17
MSR_M0_PMON_EVNT_SEL0
06_2EH
See Table 2-17
MSR_M0_PMON_EVNT_SEL1
06_2EH
See Table 2-17
MSR_M0_PMON_EVNT_SEL2
06_2EH
See Table 2-17
MSR_M0_PMON_EVNT_SEL3
06_2EH
See Table 2-17
MSR_M0_PMON_EVNT_SEL4
06_2EH
See Table 2-17
MSR_M0_PMON_EVNT_SEL5
06_2EH
See Table 2-17
MSR_M0_PMON_ISS
06_2EH
See Table 2-17
MSR_M0_PMON_MAP
06_2EH
See Table 2-17
MSR_M0_PMON_MM_CONFIG
06_2EH
See Table 2-17
MSR_M0_PMON_MSC_THR
06_2EH
See Table 2-17
MSR_M0_PMON_PGT
06_2EH
See Table 2-17
MSR_M0_PMON_PLD
Vol. 4
2-463
MODEL-SPECIFIC REGISTERS (MSRS)
MSR Name and CPUID DisplayFamily_DisplayModel
Location
06_2EH
See Table 2-17
MSR_M0_PMON_TIMESTAMP
06_2EH
See Table 2-17
MSR_M0_PMON_ZDP
06_2EH
See Table 2-17
MSR_M1_PMON_ADDR_MASK
06_2EH
See Table 2-17
MSR_M1_PMON_ADDR_MATCH
06_2EH
See Table 2-17
MSR_M1_PMON_BOX_CTRL
06_2EH
See Table 2-17
MSR_M1_PMON_BOX_OVF_CTRL
06_2EH
See Table 2-17
MSR_M1_PMON_BOX_STATUS
06_2EH
See Table 2-17
MSR_M1_PMON_CTR0
06_2EH
See Table 2-17
MSR_M1_PMON_CTR1
06_2EH
See Table 2-17
MSR_M1_PMON_CTR2
06_2EH
See Table 2-17
MSR_M1_PMON_CTR3
06_2EH
See Table 2-17
MSR_M1_PMON_CTR4
06_2EH
See Table 2-17
MSR_M1_PMON_CTR5
06_2EH
See Table 2-17
MSR_M1_PMON_DSP
06_2EH
See Table 2-17
MSR_M1_PMON_EVNT_SEL0
06_2EH
See Table 2-17
MSR_M1_PMON_EVNT_SEL1
06_2EH
See Table 2-17
MSR_M1_PMON_EVNT_SEL2
06_2EH
See Table 2-17
MSR_M1_PMON_EVNT_SEL3
06_2EH
See Table 2-17
MSR_M1_PMON_EVNT_SEL4
06_2EH
See Table 2-17
MSR_M1_PMON_EVNT_SEL5
06_2EH
See Table 2-17
MSR_M1_PMON_ISS
2-464 Vol. 4

 

 

 

 

 

 

 

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