Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 112

 

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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 112

 

 

INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
mem to ymmreg1
C4: rxb0_1: w_F 111:12:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_ F 111:12:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 111:12:mod ymmreg1 r/m
VMOVHLPS — Move Packed Single Precision Floating-Point Values High to Low
xmmreg2 and xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:12:11 xmmreg1 xmmreg3
xmmreglo2 and xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:12:11 xmmreg1 xmmreglo3
VMOVSHDUP — Move Packed Single-FP High and Duplicate
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 010:16:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 010:16:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 010:16:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 010:16:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 110:16:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 110:16:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 110:16:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 110:16:mod ymmreg1 r/m
VMOVSLDUP — Move Packed Single-FP Low and Duplicate
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 010:12:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 010:12:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 010:12:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 010:12:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 110:12:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 110:12:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 110:12:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 110:12:mod ymmreg1 r/m
VADDPD — Add Packed Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:58:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:58:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:58:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:58:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:58:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:58:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:58:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:58:mod ymmreg1 r/m
VADDSD — Add Scalar Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:58:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:58:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:58:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5 r_xmmreglo2 011:58:mod xmmreg1 r/m
VANDPD — Bitwise Logical AND of Packed Double Precision Floating-Point Values
Vol. 2D B-79
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:54:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:54:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:54:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:54:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:54:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:54:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:54:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:54:mod ymmreg1 r/m
VANDNPD — Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:55:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:55:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:55:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:55:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:55:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:55:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:55:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:55:mod ymmreg1 r/m
VCMPPD — Compare Packed Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:C2:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:C2:mod xmmreg1 r/m: imm
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:C2:11 xmmreg1 xmmreglo3: imm
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:C2:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:C2:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:C2:mod ymmreg1 r/m: imm
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:C2:11 ymmreg1 ymmreglo3: imm
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:C2:mod ymmreg1 r/m: imm
VCMPSD — Compare Scalar Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:C2:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:C2:mod xmmreg1 r/m: imm
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:C2:11 xmmreg1 xmmreglo3: imm
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:C2:mod xmmreg1 r/m: imm
VCOMISD — Compare Scalar Ordered Double Precision Floating-Point Values and Set EFLAGS
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 001:2F:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 001:2F:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 001:2F:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 001:2F:mod xmmreg1 r/m
VCVTDQ2PD— Convert Packed Dword Integers to Packed Double Precision FP Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 010:E6:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 010:E6:mod xmmreg1 r/m
B-80
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo to xmmreg1
C5: r_F 010:E6:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 010:E6:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 110:E6:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 110:E6:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 110:E6:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 110:E6:mod ymmreg1 r/m
VCVTDQ2PS— Convert Packed Dword Integers to Packed Single Precision FP Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:5B:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:5B:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:5B:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:5B:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:5B:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:5B:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:5B:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:5B:mod ymmreg1 r/m
VCVTPD2DQ— Convert Packed Double Precision FP Values to Packed Dword Integers
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 011:E6:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 011:E6:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 011:E6:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 011:E6:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 111:E6:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 111:E6:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 111:E6:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 111:E6:mod ymmreg1 r/m
VCVTPD2PS— Convert Packed Double Precision FP Values to Packed Single Precision FP Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 001:5A:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 001:5A:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 001:5A:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 001:5A:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 101:5A:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 101:5A:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 101:5A:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 101:5A:mod ymmreg1 r/m
VCVTPS2DQ— Convert Packed Single Precision FP Values to Packed Dword Integers
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 001:5B:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 001:5B:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 001:5B:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 001:5B:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 101:5B:11 ymmreg1 ymmreg2
Vol. 2D B-81
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
mem to ymmreg1
C4: rxb0_1: w_F 101:5B:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 101:5B:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 101:5B:mod ymmreg1 r/m
VCVTPS2PD— Convert Packed Single Precision FP Values to Packed Double Precision FP Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:5A:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:5A:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:5A:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:5A:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:5A:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:5A:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:5A:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:5A:mod ymmreg1 r/m
VCVTSD2SI— Convert Scalar Double Precision FP Value to Integer
xmmreg1 to reg32
C4: rxb0_1: 0_F 011:2D:11 reg xmmreg1
mem to reg32
C4: rxb0_1: 0_F 011:2D:mod reg r/m
xmmreglo to reg32
C5: r_F 011:2D:11 reg xmmreglo
mem to reg32
C5: r_F 011:2D:mod reg r/m
ymmreg1 to reg64
C4: rxb0_1: 1_F 111:2D:11 reg ymmreg1
mem to reg64
C4: rxb0_1: 1_F 111:2D:mod reg r/m
VCVTSD2SS — Convert Scalar Double Precision FP Value to Scalar Single Precision FP Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:5A:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:5A:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:5A:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:5A:mod xmmreg1 r/m
VCVTSI2SD— Convert Dword Integer to Scalar Double Precision FP Value
xmmreg2 with reg to xmmreg1
C4: rxb0_1: 0 xmmreg2 011:2A:11 xmmreg1 reg
xmmreg2 with mem to xmmreg1
C4: rxb0_1: 0 xmmreg2 011:2A:mod xmmreg1 r/m
xmmreglo2 with reglo to xmmreg1
C5: r_xmmreglo2 011:2A:11 xmmreg1 reglo
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:2A:mod xmmreg1 r/m
ymmreg2 with reg to ymmreg1
C4: rxb0_1: 1 ymmreg2 111:2A:11 ymmreg1 reg
ymmreg2 with mem to ymmreg1
C4: rxb0_1: 1 ymmreg2 111:2A:mod ymmreg1 r/m
VCVTSS2SD — Convert Scalar Single Precision FP Value to Scalar Double Precision FP Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:5A:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:5A:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:5A:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:5A:mod xmmreg1 r/m
VCVTTPD2DQ— Convert with Truncation Packed Double Precision FP Values to Packed Dword Integers
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 001:E6:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 001:E6:mod xmmreg1 r/m
B-82
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo to xmmreg1
C5: r_F 001:E6:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 001:E6:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 101:E6:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 101:E6:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 101:E6:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 101:E6:mod ymmreg1 r/m
VCVTTPS2DQ— Convert with Truncation Packed Single Precision FP Values to Packed Dword Integers
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 010:5B:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 010:5B:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 010:5B:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 010:5B:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 110:5B:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 110:5B:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 110:5B:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 110:5B:mod ymmreg1 r/m
VCVTTSD2SI— Convert with Truncation Scalar Double Precision FP Value to Signed Integer
xmmreg1 to reg32
C4: rxb0_1: 0_F 011:2C:11 reg xmmreg1
mem to reg32
C4: rxb0_1: 0_F 011:2C:mod reg r/m
xmmreglo to reg32
C5: r_F 011:2C:11 reg xmmreglo
mem to reg32
C5: r_F 011:2C:mod reg r/m
xmmreg1 to reg64
C4: rxb0_1: 1_F 011:2C:11 reg xmmreg1
mem to reg64
C4: rxb0_1: 1_F 011:2C:mod reg r/m
VDIVPD — Divide Packed Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:5E:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:5E:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:5E:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:5E:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:5E:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:5E:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:5E:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:5E:mod ymmreg1 r/m
VDIVSD — Divide Scalar Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:5E:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:5E:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:5E:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:5E:mod xmmreg1 r/m
VMASKMOVDQU— Store Selected Bytes of Double Quadword
xmmreg1 to mem; xmmreg2 as mask
C4: rxb0_1: w_F 001:F7:11 r/m xmmreg1: xmmreg2
xmmreg1 to mem; xmmreg2 as mask
C5: r_F 001:F7:11 r/m xmmreg1: xmmreg2
Vol. 2D B-83
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
VMAXPD — Return Maximum Packed Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:5F:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:5F:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:5F:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:5F:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:5F:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:5F:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:5F:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:5F:mod ymmreg1 r/m
VMAXSD — Return Maximum Scalar Double Precision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:5F:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:5F:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:5F:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:5F:mod xmmreg1 r/m
VMINPD — Return Minimum Packed Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:5D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:5D:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:5D:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:5D:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:5D:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:5D:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:5D:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:5D:mod ymmreg1 r/m
VMINSD — Return Minimum Scalar Double Precision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:5D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:5D:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:5D:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:5D:mod xmmreg1 r/m
VMOVAPD — Move Aligned Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 001:28:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 001:28:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 001:28:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 001:28:mod xmmreg1 r/m
xmmreg1 to xmmreg2
C4: rxb0_1: w_F 001:29:11 xmmreg2 xmmreg1
xmmreg1 to mem
C4: rxb0_1: w_F 001:29:mod r/m xmmreg1
xmmreg1 to xmmreglo
C5: r_F 001:29:11 xmmreglo xmmreg1
xmmreg1 to mem
C5: r_F 001:29:mod r/m xmmreg1
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 101:28:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 101:28:mod ymmreg1 r/m
B-84
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
ymmreglo to ymmreg1
C5: r_F 101:28:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 101:28:mod ymmreg1 r/m
ymmreg1 to ymmreg2
C4: rxb0_1: w_F 101:29:11 ymmreg2 ymmreg1
ymmreg1 to mem
C4: rxb0_1: w_F 101:29:mod r/m ymmreg1
ymmreg1 to ymmreglo
C5: r_F 101:29:11 ymmreglo ymmreg1
ymmreg1 to mem
C5: r_F 101:29:mod r/m ymmreg1
VMOVD — Move Doubleword
reg32 to xmmreg1
C4: rxb0_1: 0_F 001:6E:11 xmmreg1 reg32
mem32 to xmmreg1
C4: rxb0_1: 0_F 001:6E:mod xmmreg1 r/m
reg32 to xmmreg1
C5: r_F 001:6E:11 xmmreg1 reg32
mem32 to xmmreg1
C5: r_F 001:6E:mod xmmreg1 r/m
xmmreg1 to reg32
C4: rxb0_1: 0_F 001:7E:11 reg32 xmmreg1
xmmreg1 to mem32
C4: rxb0_1: 0_F 001:7E:mod mem32 xmmreg1
xmmreglo to reg32
C5: r_F 001:7E:11 reg32 xmmreglo
xmmreglo to mem32
C5: r_F 001:7E:mod mem32 xmmreglo
VMOVQ — Move Quadword
reg64 to xmmreg1
C4: rxb0_1: 1_F 001:6E:11 xmmreg1 reg64
mem64 to xmmreg1
C4: rxb0_1: 1_F 001:6E:mod xmmreg1 r/m
xmmreg1 to reg64
C4: rxb0_1: 1_F 001:7E:11 reg64 xmmreg1
xmmreg1 to mem64
C4: rxb0_1: 1_F 001:7E:mod r/m xmmreg1
VMOVDQA — Move Aligned Double Quadword
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 001:6F:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 001:6F:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 001:6F:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 001:6F:mod xmmreg1 r/m
xmmreg1 to xmmreg2
C4: rxb0_1: w_F 001:7F:11 xmmreg2 xmmreg1
xmmreg1 to mem
C4: rxb0_1: w_F 001:7F:mod r/m xmmreg1
xmmreg1 to xmmreglo
C5: r_F 001:7F:11 xmmreglo xmmreg1
xmmreg1 to mem
C5: r_F 001:7F:mod r/m xmmreg1
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 101:6F:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 101:6F:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 101:6F:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 101:6F:mod ymmreg1 r/m
ymmreg1 to ymmreg2
C4: rxb0_1: w_F 101:7F:11 ymmreg2 ymmreg1
ymmreg1 to mem
C4: rxb0_1: w_F 101:7F:mod r/m ymmreg1
ymmreg1 to ymmreglo
C5: r_F 101:7F:11 ymmreglo ymmreg1
ymmreg1 to mem
C5: r_F 101:7F:mod r/m ymmreg1
VMOVDQU — Move Unaligned Double Quadword
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 010:6F:11 xmmreg1 xmmreg2
Vol. 2D B-85
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
mem to xmmreg1
C4: rxb0_1: w_F 010:6F:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 010:6F:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 010:6F:mod xmmreg1 r/m
xmmreg1 to xmmreg2
C4: rxb0_1: w_F 010:7F:11 xmmreg2 xmmreg1
xmmreg1 to mem
C4: rxb0_1: w_F 010:7F:mod r/m xmmreg1
xmmreg1 to xmmreglo
C5: r_F 010:7F:11 xmmreglo xmmreg1
xmmreg1 to mem
C5: r_F 010:7F:mod r/m xmmreg1
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 110:6F:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 110:6F:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 110:6F:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 110:6F:mod ymmreg1 r/m
ymmreg1 to ymmreg2
C4: rxb0_1: w_F 110:7F:11 ymmreg2 ymmreg1
ymmreg1 to mem
C4: rxb0_1: w_F 110:7F:mod r/m ymmreg1
ymmreg1 to ymmreglo
C5: r_F 110:7F:11 ymmreglo ymmreg1
ymmreg1 to mem
C5: r_F 110:7F:mod r/m ymmreg1
VMOVHPD — Move High Packed Double Precision Floating-Point Value
xmmreg1 and mem to xmmreg2
C4: rxb0_1: w xmmreg1 001:16:11 xmmreg2 r/m
xmmreg1 and mem to xmmreglo2
C5: r_xmmreg1 001:16:11 xmmreglo2 r/m
xmmreg1 to mem
C4: rxb0_1: w_F 001:17:mod r/m xmmreg1
xmmreglo to mem
C5: r_F 001:17:mod r/m xmmreglo
VMOVLPD — Move Low Packed Double Precision Floating-Point Value
xmmreg1 and mem to xmmreg2
C4: rxb0_1: w xmmreg1 001:12:11 xmmreg2 r/m
xmmreg1 and mem to xmmreglo2
C5: r_xmmreg1 001:12:11 xmmreglo2 r/m
xmmreg1 to mem
C4: rxb0_1: w_F 001:13:mod r/m xmmreg1
xmmreglo to mem
C5: r_F 001:13:mod r/m xmmreglo
VMOVMSKPD — Extract Packed Double Precision Floating-Point Sign Mask
xmmreg2 to reg
C4: rxb0_1: w_F 001:50:11 reg xmmreg1
xmmreglo to reg
C5: r_F 001:50:11 reg xmmreglo
ymmreg2 to reg
C4: rxb0_1: w_F 101:50:11 reg ymmreg1
ymmreglo to reg
C5: r_F 101:50:11 reg ymmreglo
VMOVNTDQ — Store Double Quadword Using Non-Temporal Hint
xmmreg1 to mem
C4: rxb0_1: w_F 001:E7:11 r/m xmmreg1
xmmreglo to mem
C5: r_F 001:E7:11 r/m xmmreglo
ymmreg1 to mem
C4: rxb0_1: w_F 101:E7:11 r/m ymmreg1
ymmreglo to mem
C5: r_F 101:E7:11 r/m ymmreglo
VMOVNTPD — Store Packed Double Precision Floating-Point Values Using Non-Temporal Hint
xmmreg1 to mem
C4: rxb0_1: w_F 001:2B:11 r/m xmmreg1
xmmreglo to mem
C5: r_F 001:2B:11 r/m xmmreglo
ymmreg1 to mem
C4: rxb0_1: w_F 101:2B:11r/m ymmreg1
B-86
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
ymmreglo to mem
C5: r_F 101:2B:11r/m ymmreglo
VMOVSD — Move Scalar Double Precision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:10:11 xmmreg1 xmmreg3
mem to xmmreg1
C4: rxb0_1: w_F 011:10:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:10:11 xmmreg1 xmmreglo3
mem to xmmreg1
C5: r_F 011:10:mod xmmreg1 r/m
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:11:11 xmmreg1 xmmreg3
xmmreg1 to mem
C4: rxb0_1: w_F 011:11:mod r/m xmmreg1
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:11:11 xmmreg1 xmmreglo3
xmmreglo to mem
C5: r_F 011:11:mod r/m xmmreglo
VMOVUPD — Move Unaligned Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 001:10:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 001:10:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 001:10:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 001:10:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 101:10:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 101:10:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 101:10:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 101:10:mod ymmreg1 r/m
xmmreg1 to xmmreg2
C4: rxb0_1: w_F 001:11:11 xmmreg2 xmmreg1
xmmreg1 to mem
C4: rxb0_1: w_F 001:11:mod r/m xmmreg1
xmmreg1 to xmmreglo
C5: r_F 001:11:11 xmmreglo xmmreg1
xmmreg1 to mem
C5: r_F 001:11:mod r/m xmmreg1
ymmreg1 to ymmreg2
C4: rxb0_1: w_F 101:11:11 ymmreg2 ymmreg1
ymmreg1 to mem
C4: rxb0_1: w_F 101:11:mod r/m ymmreg1
ymmreg1 to ymmreglo
C5: r_F 101:11:11 ymmreglo ymmreg1
ymmreg1 to mem
C5: r_F 101:11:mod r/m ymmreg1
VMULPD — Multiply Packed Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:59:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:59:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:59:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:59:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:59:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:59:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:59:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:59:mod ymmreg1 r/m
VMULSD — Multiply Scalar Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:59:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:59:mod xmmreg1 r/m
Vol. 2D B-87
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:59:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:59:mod xmmreg1 r/m
VORPD — Bitwise Logical OR of Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:56:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:56:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:56:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:56:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:56:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:56:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:56:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:56:mod ymmreg1 r/m
VPACKSSWB— Pack with Signed Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:63:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:63:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:63:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:63:mod xmmreg1 r/m
VPACKSSDW— Pack with Signed Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:6B:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:6B:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:6B:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:6B:mod xmmreg1 r/m
VPACKUSWB— Pack with Unsigned Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:67:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:67:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:67:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:67:mod xmmreg1 r/m
VPADDB — Add Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:FC:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:FC:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:FC:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:FC:mod xmmreg1 r/m
VPADDW — Add Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:FD:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:FD:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:FD:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:FD:mod xmmreg1 r/m
VPADDD — Add Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:FE:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:FE:mod xmmreg1 r/m
B-88
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:FE:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:FE:mod xmmreg1 r/m
VPADDQ — Add Packed Quadword Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D4:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D4:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D4:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D4:mod xmmreg1 r/m
VPADDSB — Add Packed Signed Integers with Signed Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:EC:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:EC:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:EC:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:EC:mod xmmreg1 r/m
VPADDSW — Add Packed Signed Integers with Signed Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:ED:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:ED:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:ED:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:ED:mod xmmreg1 r/m
VPADDUSB — Add Packed Unsigned Integers with Unsigned Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:DC:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:DC:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:DC:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:DC:mod xmmreg1 r/m
VPADDUSW — Add Packed Unsigned Integers with Unsigned Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:DD:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:DD:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:DD:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:DD:mod xmmreg1 r/m
VPAND — Logical AND
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:DB:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:DB:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:DB:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:DB:mod xmmreg1 r/m
VPANDN — Logical AND NOT
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:DF:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:DF:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:DF:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:DF:mod xmmreg1 r/m
VPAVGB — Average Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E0:11 xmmreg1 xmmreg3
Vol. 2D B-89
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E0:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E0:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E0:mod xmmreg1 r/m
VPAVGW — Average Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E3:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E3:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E3:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E3:mod xmmreg1 r/m
VPCMPEQB — Compare Packed Data for Equal
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:74:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:74:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:74:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:74:mod xmmreg1 r/m
VPCMPEQW — Compare Packed Data for Equal
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:75:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:75:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:75:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:75:mod xmmreg1 r/m
VPCMPEQD — Compare Packed Data for Equal
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:76:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:76:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:76:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:76:mod xmmreg1 r/m
VPCMPGTB — Compare Packed Signed Integers for Greater Than
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:64:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:64:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:64:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:64:mod xmmreg1 r/m
VPCMPGTW — Compare Packed Signed Integers for Greater Than
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:65:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:65:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:65:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:65:mod xmmreg1 r/m
VPCMPGTD — Compare Packed Signed Integers for Greater Than
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:66:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:66:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:66:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:66:mod xmmreg1 r/m
VPEXTRW — Extract Word
B-90
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg1 to reg using imm
C4: rxb0_1: 0_F 001:C5:11 reg xmmreg1: imm
xmmreg1 to reg using imm
C5: r_F 001:C5:11 reg xmmreg1: imm
VPINSRW — Insert Word
xmmreg2 with reg to xmmreg1
C4: rxb0_1: 0 xmmreg2 001:C4:11 xmmreg1 reg: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_1: 0 xmmreg2 001:C4:mod xmmreg1 r/m: imm
xmmreglo2 with reglo to xmmreg1
C5: r_xmmreglo2 001:C4:11 xmmreg1 reglo: imm
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:C4:mod xmmreg1 r/m: imm
VPMADDWD — Multiply and Add Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F5:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F5:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F5:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F5:mod xmmreg1 r/m
VPMAXSW — Maximum of Packed Signed Word Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:EE:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:EE:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:EE:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:EE:mod xmmreg1 r/m
VPMAXUB — Maximum of Packed Unsigned Byte Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:DE:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:DE:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:DE:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:DE:mod xmmreg1 r/m
VPMINSW — Minimum of Packed Signed Word Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:EA:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:EA:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:EA:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:EA:mod xmmreg1 r/m
VPMINUB — Minimum of Packed Unsigned Byte Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:DA:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:DA:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:DA:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:DA:mod xmmreg1 r/m
VPMOVMSKB — Move Byte Mask
xmmreg1 to reg
C4: rxb0_1: w_F 001:D7:11 reg xmmreg1
xmmreg1 to reg
C5: r_F 001:D7:11 reg xmmreg1
VPMULHUW — Multiply Packed Unsigned Integers and Store High Result
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E4:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E4:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E4:11 xmmreg1 xmmreglo3
Vol. 2D B-91
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E4:mod xmmreg1 r/m
VPMULHW — Multiply Packed Signed Integers and Store High Result
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E5:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E5:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E5:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E5:mod xmmreg1 r/m
VPMULLW — Multiply Packed Signed Integers and Store Low Result
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D5:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D5:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D5:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D5:mod xmmreg1 r/m
VPMULUDQ — Multiply Packed Unsigned Doubleword Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F4:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F4:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F4:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F4:mod xmmreg1 r/m
VPOR — Bitwise Logical OR
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:EB:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:EB:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:EB:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:EB:mod xmmreg1 r/m
VPSADBW — Compute Sum of Absolute Differences
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F6:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F6:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F6:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F6:mod xmmreg1 r/m
VPSHUFD — Shuffle Packed Doublewords
xmmreg2 to xmmreg1 using imm
C4: rxb0_1: w_F 001:70:11 xmmreg1 xmmreg2: imm
mem to xmmreg1 using imm
C4: rxb0_1: w_F 001:70:mod xmmreg1 r/m: imm
xmmreglo to xmmreg1 using imm
C5: r_F 001:70:11 xmmreg1 xmmreglo: imm
mem to xmmreg1 using imm
C5: r_F 001:70:mod xmmreg1 r/m: imm
VPSHUFHW — Shuffle Packed High Words
xmmreg2 to xmmreg1 using imm
C4: rxb0_1: w_F 010:70:11 xmmreg1 xmmreg2: imm
mem to xmmreg1 using imm
C4: rxb0_1: w_F 010:70:mod xmmreg1 r/m: imm
xmmreglo to xmmreg1 using imm
C5: r_F 010:70:11 xmmreg1 xmmreglo: imm
mem to xmmreg1 using imm
C5: r_F 010:70:mod xmmreg1 r/m: imm
VPSHUFLW — Shuffle Packed Low Words
xmmreg2 to xmmreg1 using imm
C4: rxb0_1: w_F 011:70:11 xmmreg1 xmmreg2: imm
mem to xmmreg1 using imm
C4: rxb0_1: w_F 011:70:mod xmmreg1 r/m: imm
B-92
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo to xmmreg1 using imm
C5: r_F 011:70:11 xmmreg1 xmmreglo: imm
mem to xmmreg1 using imm
C5: r_F 011:70:mod xmmreg1 r/m: imm
VPSLLDQ — Shift Double Quadword Left Logical
xmmreg2 to xmmreg1 using imm
C4: rxb0_1: w_F 001:73:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm
C5: r_F 001:73:11 xmmreg1 xmmreglo: imm
VPSLLW — Shift Packed Data Left Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F1:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F1:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F1:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F1:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:71:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:71:11 xmmreg1 xmmreglo: imm
VPSLLD — Shift Packed Data Left Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F2:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F2:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F2:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F2:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:72:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:72:11 xmmreg1 xmmreglo: imm
VPSLLQ — Shift Packed Data Left Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F3:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F3:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F3:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F3:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:73:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:73:11 xmmreg1 xmmreglo: imm
VPSRAW — Shift Packed Data Right Arithmetic
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E1:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E1:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E1:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E1:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:71:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:71:11 xmmreg1 xmmreglo: imm
VPSRAD — Shift Packed Data Right Arithmetic
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E2:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E2:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E2:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E2:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:72:11 xmmreg1 xmmreg2: imm
Vol. 2D B-93
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo to xmmreg1 using imm8
C5: r_F 001:72:11 xmmreg1 xmmreglo: imm
VPSRLDQ — Shift Double Quadword Right Logical
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:73:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:73:11 xmmreg1 xmmreglo: imm
VPSRLW — Shift Packed Data Right Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D1:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D1:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D1:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D1:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:71:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:71:11 xmmreg1 xmmreglo: imm
VPSRLD — Shift Packed Data Right Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D2:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D2:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D2:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D2:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:72:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:72:11 xmmreg1 xmmreglo: imm
VPSRLQ — Shift Packed Data Right Logical
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D3:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D3:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D3:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D3:mod xmmreg1 r/m
xmmreg2 to xmmreg1 using imm8
C4: rxb0_1: w_F 001:73:11 xmmreg1 xmmreg2: imm
xmmreglo to xmmreg1 using imm8
C5: r_F 001:73:11 xmmreg1 xmmreglo: imm
VPSUBB — Subtract Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F8:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F8:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F8:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:F8:mod xmmreg1 r/m
VPSUBW — Subtract Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:F9:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:F9:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:F9:11 xmmreg1 xmmreglo3
xmmrelog2 with mem to xmmreg1
C5: r_xmmreglo2 001:F9:mod xmmreg1 r/m
VPSUBD — Subtract Packed Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:FA:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:FA:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:FA:11 xmmreg1 xmmreglo3
B-94
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:FA:mod xmmreg1 r/m
VPSUBQ — Subtract Packed Quadword Integers
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:FB:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:FB:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:FB:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:FB:mod xmmreg1 r/m
VPSUBSB — Subtract Packed Signed Integers with Signed Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E8:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E8:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E8:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E8:mod xmmreg1 r/m
VPSUBSW — Subtract Packed Signed Integers with Signed Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:E9:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:E9:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:E9:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:E9:mod xmmreg1 r/m
VPSUBUSB — Subtract Packed Unsigned Integers with Unsigned Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D8:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D8:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D8:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D8:mod xmmreg1 r/m
VPSUBUSW — Subtract Packed Unsigned Integers with Unsigned Saturation
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:D9:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:D9:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:D9:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:D9:mod xmmreg1 r/m
VPUNPCKHBW — Unpack High Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:68:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:68:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:68:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:68:mod xmmreg1 r/m
VPUNPCKHWD — Unpack High Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:69:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:69:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:69:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:69:mod xmmreg1 r/m
VPUNPCKHDQ — Unpack High Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:6A:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:6A:mod xmmreg1 r/m
Vol. 2D B-95
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:6A:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:6A:mod xmmreg1 r/m
VPUNPCKHQDQ — Unpack High Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:6D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:6D:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:6D:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:6D:mod xmmreg1 r/m
VPUNPCKLBW — Unpack Low Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:60:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:60:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:60:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:60:mod xmmreg1 r/m
VPUNPCKLWD — Unpack Low Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:61:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:61:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:61:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:61:mod xmmreg1 r/m
VPUNPCKLDQ — Unpack Low Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:62:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:62:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:62:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:62:mod xmmreg1 r/m
VPUNPCKLQDQ — Unpack Low Data
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:6C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:6C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:6C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:6C:mod xmmreg1 r/m
VPXOR — Logical Exclusive OR
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:EF:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:EF:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:EF:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:EF:mod xmmreg1 r/m
VSHUFPD — Shuffle Packed Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1 using imm8
C4: rxb0_1: w xmmreg2 001:C6:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1 using imm8
C4: rxb0_1: w xmmreg2 001:C6:mod xmmreg1 r/m: imm
xmmreglo2 with xmmreglo3 to xmmreg1 using imm8
C5: r_xmmreglo2 001:C6:11 xmmreg1 xmmreglo3: imm
xmmreglo2 with mem to xmmreg1 using imm8
C5: r_xmmreglo2 001:C6:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 to ymmreg1 using imm8
C4: rxb0_1: w ymmreg2 101:C6:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1 using imm8
C4: rxb0_1: w ymmreg2 101:C6:mod ymmreg1 r/m: imm
B-96
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
ymmreglo2 with ymmreglo3 to ymmreg1 using imm8
C5: r_ymmreglo2 101:C6:11 ymmreg1 ymmreglo3: imm
ymmreglo2 with mem to ymmreg1 using imm8
C5: r_ymmreglo2 101:C6:mod ymmreg1 r/m: imm
VSQRTPD — Compute Square Roots of Packed Double Precision Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 001:51:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 001:51:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 001:51:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 001:51:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 101:51:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 101:51:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 101:51:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 101:51:mod ymmreg1 r/m
VSQRTSD — Compute Square Root of Scalar Double Precision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:51:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:51:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:51:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:51:mod xmmreg1 r/m
VSUBPD — Subtract Packed Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:5C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:5C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:5C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:5C:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:5C:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:5C:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:5C:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:5C:mod ymmreg1 r/m
VSUBSD — Subtract Scalar Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 011:5C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 011:5C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 011:5C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 011:5C:mod xmmreg1 r/m
VUCOMISD — Unordered Compare Scalar Double Precision Floating-Point Values and Set EFLAGS
xmmreg2 with xmmreg1, set EFLAGS
C4: rxb0_1: w_F xmmreg1 001:2E:11 xmmreg2
mem with xmmreg1, set EFLAGS
C4: rxb0_1: w_F xmmreg1 001:2E:mod r/m
xmmreglo with xmmreg1, set EFLAGS
C5: r_F xmmreg1 001:2E:11 xmmreglo
mem with xmmreg1, set EFLAGS
C5: r_F xmmreg1 001:2E:mod r/m
VUNPCKHPD — Unpack and Interleave High Packed Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:15:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:15:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:15:11 xmmreg1 xmmreglo3
Vol. 2D B-97
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:15:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:15:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:15:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:15:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:15:mod ymmreg1 r/m
VUNPCKHPS — Unpack and Interleave High Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:15:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:15:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:15:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:15:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:15:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:15:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:15:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:15:mod ymmreg1 r/m
VUNPCKLPD — Unpack and Interleave Low Packed Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:14:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:14:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:14:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:14:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:14:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:14:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:14:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:14:mod ymmreg1 r/m
VUNPCKLPS — Unpack and Interleave Low Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:14:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:14:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:14:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:14:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:14:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:14:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:14:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:14:mod ymmreg1 r/m
VXORPD — Bitwise Logical XOR for Double Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 001:57:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 001:57:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 001:57:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 001:57:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 101:57:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 101:57:mod ymmreg1 r/m
B-98
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 101:57:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 101:57:mod ymmreg1 r/m
VADDPS — Add Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:58:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:58:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:58:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:58:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:58:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:58:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:58:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:58:mod ymmreg1 r/m
VADDSS — Add Scalar Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:58:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:58:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:58:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:58:mod xmmreg1 r/m
VANDPS — Bitwise Logical AND of Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:54:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:54:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:54:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:54:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:54:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:54:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:54:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:54:mod ymmreg1 r/m
VANDNPS — Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:55:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:55:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:55:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:55:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:55:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:55:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:55:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:55:mod ymmreg1 r/m
VCMPPS — Compare Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:C2:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:C2:mod xmmreg1 r/m: imm
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:C2:11 xmmreg1 xmmreglo3: imm
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:C2:mod xmmreg1 r/m: imm
Vol. 2D B-99
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:C2:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:C2:mod ymmreg1 r/m: imm
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:C2:11 ymmreg1 ymmreglo3: imm
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:C2:mod ymmreg1 r/m: imm
VCMPSS — Compare Scalar Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:C2:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:C2:mod xmmreg1 r/m: imm
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:C2:11 xmmreg1 xmmreglo3: imm
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:C2:mod xmmreg1 r/m: imm
VCOMISS — Compare Scalar Ordered Single Precision Floating-Point Values and Set EFLAGS
xmmreg2 with xmmreg1
C4: rxb0_1: w_F 000:2F:11 xmmreg1 xmmreg2
mem with xmmreg1
C4: rxb0_1: w_F 000:2F:mod xmmreg1 r/m
xmmreglo with xmmreg1
C5: r_F 000:2F:11 xmmreg1 xmmreglo
mem with xmmreg1
C5: r_F 000:2F:mod xmmreg1 r/m
VCVTSI2SS — Convert Dword Integer to Scalar Single Precision FP Value
xmmreg2 with reg to xmmreg1
C4: rxb0_1: 0 xmmreg2 010:2A:11 xmmreg1 reg
xmmreg2 with mem to xmmreg1
C4: rxb0_1: 0 xmmreg2 010:2A:mod xmmreg1 r/m
xmmreglo2 with reglo to xmmreg1
C5: r_xmmreglo2 010:2A:11 xmmreg1 reglo
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:2A:mod xmmreg1 r/m
xmmreg2 with reg to xmmreg1
C4: rxb0_1: 1 xmmreg2 010:2A:11 xmmreg1 reg
xmmreg2 with mem to xmmreg1
C4: rxb0_1: 1 xmmreg2 010:2A:mod xmmreg1 r/m
VCVTSS2SI — Convert Scalar Single Precision FP Value to Dword Integer
xmmreg1 to reg
C4: rxb0_1: 0_F 010:2D:11 reg xmmreg1
mem to reg
C4: rxb0_1: 0_F 010:2D:mod reg r/m
xmmreglo to reg
C5: r_F 010:2D:11 reg xmmreglo
mem to reg
C5: r_F 010:2D:mod reg r/m
xmmreg1 to reg
C4: rxb0_1: 1_F 010:2D:11 reg xmmreg1
mem to reg
C4: rxb0_1: 1_F 010:2D:mod reg r/m
VCVTTSS2SI — Convert with Truncation Scalar Single Precision FP Value to Dword Integer
xmmreg1 to reg
C4: rxb0_1: 0_F 010:2C:11 reg xmmreg1
mem to reg
C4: rxb0_1: 0_F 010:2C:mod reg r/m
xmmreglo to reg
C5: r_F 010:2C:11 reg xmmreglo
mem to reg
C5: r_F 010:2C:mod reg r/m
xmmreg1 to reg
C4: rxb0_1: 1_F 010:2C:11 reg xmmreg1
mem to reg
C4: rxb0_1: 1_F 010:2C:mod reg r/m
VDIVPS — Divide Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:5E:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:5E:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:5E:11 xmmreg1 xmmreglo3
B-100
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:5E:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:5E:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:5E:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:5E:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:5E:mod ymmreg1 r/m
VDIVSS — Divide Scalar Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:5E:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:5E:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:5E:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:5E:mod xmmreg1 r/m
VLDMXCSR — Load MXCSR Register
mem to MXCSR reg
C4: rxb0_1: w_F 000:AEmod 011 r/m
mem to MXCSR reg
C5: r_F 000:AEmod 011 r/m
VMAXPS — Return Maximum Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:5F:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:5F:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:5F:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:5F:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:5F:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:5F:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:5F:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:5F:mod ymmreg1 r/m
VMAXSS — Return Maximum Scalar Single Precision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:5F:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:5F:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:5F:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:5F:mod xmmreg1 r/m
VMINPS — Return Minimum Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:5D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:5D:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:5D:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:5D:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:5D:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:5D:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:5D:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:5D:mod ymmreg1 r/m
VMINSS — Return Minimum Scalar Single Precision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:5D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:5D:mod xmmreg1 r/m
Vol. 2D B-101
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:5D:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:5D:mod xmmreg1 r/m
VMOVAPS— Move Aligned Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:28:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:28:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:28:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:28:mod xmmreg1 r/m
xmmreg1 to xmmreg2
C4: rxb0_1: w_F 000:29:11 xmmreg2 xmmreg1
xmmreg1 to mem
C4: rxb0_1: w_F 000:29:mod r/m xmmreg1
xmmreg1 to xmmreglo
C5: r_F 000:29:11 xmmreglo xmmreg1
xmmreg1 to mem
C5: r_F 000:29:mod r/m xmmreg1
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:28:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:28:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:28:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:28:mod ymmreg1 r/m
ymmreg1 to ymmreg2
C4: rxb0_1: w_F 100:29:11 ymmreg2 ymmreg1
ymmreg1 to mem
C4: rxb0_1: w_F 100:29:mod r/m ymmreg1
ymmreg1 to ymmreglo
C5: r_F 100:29:11 ymmreglo ymmreg1
ymmreg1 to mem
C5: r_F 100:29:mod r/m ymmreg1
VMOVHPS — Move High Packed Single Precision Floating-Point Values
xmmreg1 with mem to xmmreg2
C4: rxb0_1: w xmmreg1 000:16:mod xmmreg2 r/m
xmmreg1 with mem to xmmreglo2
C5: r_xmmreg1 000:16:mod xmmreglo2 r/m
xmmreg1 to mem
C4: rxb0_1: w_F 000:17:mod r/m xmmreg1
xmmreglo to mem
C5: r_F 000:17:mod r/m xmmreglo
VMOVLHPS — Move Packed Single Precision Floating-Point Values Low to High
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:16:11 xmmreg1 xmmreg3
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:16:11 xmmreg1 xmmreglo3
VMOVLPS — Move Low Packed Single Precision Floating-Point Values
xmmreg1 with mem to xmmreg2
C4: rxb0_1: w xmmreg1 000:12:mod xmmreg2 r/m
xmmreg1 with mem to xmmreglo2
C5: r_xmmreg1 000:12:mod xmmreglo2 r/m
xmmreg1 to mem
C4: rxb0_1: w_F 000:13:mod r/m xmmreg1
xmmreglo to mem
C5: r_F 000:13:mod r/m xmmreglo
VMOVMSKPS — Extract Packed Single Precision Floating-Point Sign Mask
xmmreg2 to reg
C4: rxb0_1: w_F 000:50:11 reg xmmreg2
xmmreglo to reg
C5: r_F 000:50:11 reg xmmreglo
ymmreg2 to reg
C4: rxb0_1: w_F 100:50:11 reg ymmreg2
ymmreglo to reg
C5: r_F 100:50:11 reg ymmreglo
VMOVNTPS — Store Packed Single Precision Floating-Point Values Using Non-Temporal Hint
xmmreg1 to mem
C4: rxb0_1: w_F 000:2B:mod r/m xmmreg1
B-102
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo to mem
C5: r_F 000:2B:mod r/m xmmreglo
ymmreg1 to mem
C4: rxb0_1: w_F 100:2B:mod r/m ymmreg1
ymmreglo to mem
C5: r_F 100:2B:mod r/m ymmreglo
VMOVSS — Move Scalar Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:10:11 xmmreg1 xmmreg3
mem to xmmreg1
C4: rxb0_1: w_F 010:10:mod xmmreg1 r/m
xmmreg2 with xmmreg3 to xmmreg1
C5: r_xmmreg2 010:10:11 xmmreg1 xmmreg3
mem to xmmreg1
C5: r_F 010:10:mod xmmreg1 r/m
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:11:11 xmmreg1 xmmreg3
xmmreg1 to mem
C4: rxb0_1: w_F 010:11:mod r/m xmmreg1
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:11:11 xmmreg1 xmmreglo3
xmmreglo to mem
C5: r_F 010:11:mod r/m xmmreglo
VMOVUPS— Move Unaligned Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:10:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:10:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:10:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:10:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:10:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:10:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:10:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:10:mod ymmreg1 r/m
xmmreg1 to xmmreg2
C4: rxb0_1: w_F 000:11:11 xmmreg2 xmmreg1
xmmreg1 to mem
C4: rxb0_1: w_F 000:11:mod r/m xmmreg1
xmmreg1 to xmmreglo
C5: r_F 000:11:11 xmmreglo xmmreg1
xmmreg1 to mem
C5: r_F 000:11:mod r/m xmmreg1
ymmreg1 to ymmreg2
C4: rxb0_1: w_F 100:11:11 ymmreg2 ymmreg1
ymmreg1 to mem
C4: rxb0_1: w_F 100:11:mod r/m ymmreg1
ymmreg1 to ymmreglo
C5: r_F 100:11:11 ymmreglo ymmreg1
ymmreg1 to mem
C5: r_F 100:11:mod r/m ymmreg1
VMULPS — Multiply Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:59:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:59:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:59:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:59:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:59:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:59:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:59:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:59:mod ymmreg1 r/m
VMULSS — Multiply Scalar Single Precision Floating-Point Values
Vol. 2D B-103
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:59:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:59:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:59:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:59:mod xmmreg1 r/m
VORPS — Bitwise Logical OR of Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:56:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:56:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:56:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:56:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:56:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:56:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:56:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:56:mod ymmreg1 r/m
VRCPPS — Compute Reciprocals of Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:53:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:53:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:53:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:53:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:53:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:53:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:53:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:53:mod ymmreg1 r/m
VRCPSS — Compute Reciprocal of Scalar Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:53:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:53:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:53:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:53:mod xmmreg1 r/m
VRSQRTPS — Compute Reciprocals of Square Roots of Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:52:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:52:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:52:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:52:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:52:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:52:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:52:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:52:mod ymmreg1 r/m
VRSQRTSS — Compute Reciprocal of Square Root of Scalar Single Precision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:52:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:52:mod xmmreg1 r/m
B-104
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:52:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:52:mod xmmreg1 r/m
VSHUFPS — Shuffle Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1, imm8
C4: rxb0_1: w xmmreg2 000:C6:11 xmmreg1 xmmreg3: imm
xmmreg2 with mem to xmmreg1, imm8
C4: rxb0_1: w xmmreg2 000:C6:mod xmmreg1 r/m: imm
xmmreglo2 with xmmreglo3 to xmmreg1, imm8
C5: r_xmmreglo2 000:C6:11 xmmreg1 xmmreglo3: imm
xmmreglo2 with mem to xmmreg1, imm8
C5: r_xmmreglo2 000:C6:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 to ymmreg1, imm8
C4: rxb0_1: w ymmreg2 100:C6:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1, imm8
C4: rxb0_1: w ymmreg2 100:C6:mod ymmreg1 r/m: imm
ymmreglo2 with ymmreglo3 to ymmreg1, imm8
C5: r_ymmreglo2 100:C6:11 ymmreg1 ymmreglo3: imm
ymmreglo2 with mem to ymmreg1, imm8
C5: r_ymmreglo2 100:C6:mod ymmreg1 r/m: imm
VSQRTPS — Compute Square Roots of Packed Single Precision Floating-Point Values
xmmreg2 to xmmreg1
C4: rxb0_1: w_F 000:51:11 xmmreg1 xmmreg2
mem to xmmreg1
C4: rxb0_1: w_F 000:51:mod xmmreg1 r/m
xmmreglo to xmmreg1
C5: r_F 000:51:11 xmmreg1 xmmreglo
mem to xmmreg1
C5: r_F 000:51:mod xmmreg1 r/m
ymmreg2 to ymmreg1
C4: rxb0_1: w_F 100:51:11 ymmreg1 ymmreg2
mem to ymmreg1
C4: rxb0_1: w_F 100:51:mod ymmreg1 r/m
ymmreglo to ymmreg1
C5: r_F 100:51:11 ymmreg1 ymmreglo
mem to ymmreg1
C5: r_F 100:51:mod ymmreg1 r/m
VSQRTSS — Compute Square Root of Scalar Single Precision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:51:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:51:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:51:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:51:mod xmmreg1 r/m
VSTMXCSR — Store MXCSR Register State
MXCSR to mem
C4: rxb0_1: w_F 000:AE:mod 011 r/m
MXCSR to mem
C5: r_F 000:AE:mod 011 r/m
VSUBPS — Subtract Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:5C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:5C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:5C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:5C:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:5C:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:5C:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:5C:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:5C:mod ymmreg1 r/m
VSUBSS — Subtract Scalar Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 010:5C:11 xmmreg1 xmmreg3
Vol. 2D B-105
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 010:5C:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 010:5C:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 010:5C:mod xmmreg1 r/m
VUCOMISS — Unordered Compare Scalar Single Precision Floating-Point Values and Set EFLAGS
xmmreg2 with xmmreg1
C4: rxb0_1: w_F 000:2E:11 xmmreg1 xmmreg2
mem with xmmreg1
C4: rxb0_1: w_F 000:2E:mod xmmreg1 r/m
xmmreglo with xmmreg1
C5: r_F 000:2E:11 xmmreg1 xmmreglo
mem with xmmreg1
C5: r_F 000:2E:mod xmmreg1 r/m
UNPCKHPS — Unpack and Interleave High Packed Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:15:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:15mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:15:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:15mod ymmreg1 r/m
UNPCKLPS — Unpack and Interleave Low Packed Single Precision Floating-Point Value
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:14:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:14mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:14:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:14mod ymmreg1 r/m
VXORPS — Bitwise Logical XOR for Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_1: w xmmreg2 000:57:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_1: w xmmreg2 000:57:mod xmmreg1 r/m
xmmreglo2 with xmmreglo3 to xmmreg1
C5: r_xmmreglo2 000:57:11 xmmreg1 xmmreglo3
xmmreglo2 with mem to xmmreg1
C5: r_xmmreglo2 000:57:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_1: w ymmreg2 100:57:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_1: w ymmreg2 100:57:mod ymmreg1 r/m
ymmreglo2 with ymmreglo3 to ymmreg1
C5: r_ymmreglo2 100:57:11 ymmreg1 ymmreglo3
ymmreglo2 with mem to ymmreg1
C5: r_ymmreglo2 100:57:mod ymmreg1 r/m
VBROADCAST —Load with Broadcast
mem to xmmreg1
C4: rxb0_2: 0_F 001:18:mod xmmreg1 r/m
mem to ymmreg1
C4: rxb0_2: 0_F 101:18:mod ymmreg1 r/m
mem to ymmreg1
C4: rxb0_2: 0_F 101:19:mod ymmreg1 r/m
mem to ymmreg1
C4: rxb0_2: 0_F 101:1A:mod ymmreg1 r/m
VEXTRACTF128 — Extract Packed Floating-Point Values
ymmreg2 to xmmreg1, imm8
C4: rxb0_3: 0_F 001:19:11 xmmreg1 ymmreg2: imm
ymmreg2 to mem, imm8
C4: rxb0_3: 0_F 001:19:mod r/m ymmreg2: imm
VINSERTF128 — Insert Packed Floating-Point Values
xmmreg3 and merge with ymmreg2 to ymmreg1, imm8
C4: rxb0_3: 0 ymmreg2101:18:11 ymmreg1 xmmreg3: imm
mem and merge with ymmreg2 to ymmreg1, imm8
C4: rxb0_3: 0 ymmreg2 101:18:mod ymmreg1 r/m: imm
VPERMILPD — Permute Double Precision Floating-Point Values
B-106
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Instruction and Format
Encoding
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: 0 xmmreg2 001:0D:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: 0 xmmreg2 001:0D:mod xmmreg1 r/m
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_2: 0 ymmreg2 101:0D:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_2: 0 ymmreg2 101:0D:mod ymmreg1 r/m
xmmreg2 to xmmreg1, imm
C4: rxb0_3: 0_F 001:05:11 xmmreg1 xmmreg2: imm
mem to xmmreg1, imm
C4: rxb0_3: 0_F 001:05:mod xmmreg1 r/m: imm
ymmreg2 to ymmreg1, imm
C4: rxb0_3: 0_F 101:05:11 ymmreg1 ymmreg2: imm
mem to ymmreg1, imm
C4: rxb0_3: 0_F 101:05:mod ymmreg1 r/m: imm
VPERMILPS — Permute Single Precision Floating-Point Values
xmmreg2 with xmmreg3 to xmmreg1
C4: rxb0_2: 0 xmmreg2 001:0C:11 xmmreg1 xmmreg3
xmmreg2 with mem to xmmreg1
C4: rxb0_2: 0 xmmreg2 001:0C:mod xmmreg1 r/m
xmmreg2 to xmmreg1, imm
C4: rxb0_3: 0_F 001:04:11 xmmreg1 xmmreg2: imm
mem to xmmreg1, imm
C4: rxb0_3: 0_F 001:04:mod xmmreg1 r/m: imm
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_2: 0 ymmreg2 101:0C:11 ymmreg1 ymmreg3
ymmreg2 with mem to ymmreg1
C4: rxb0_2: 0 ymmreg2 101:0C:mod ymmreg1 r/m
ymmreg2 to ymmreg1, imm
C4: rxb0_3: 0_F 101:04:11 ymmreg1 ymmreg2: imm
mem to ymmreg1, imm
C4: rxb0_3: 0_F 101:04:mod ymmreg1 r/m: imm
VPERM2F128 — Permute Floating-Point Values
ymmreg2 with ymmreg3 to ymmreg1
C4: rxb0_3: 0 ymmreg2 101:06:11 ymmreg1 ymmreg3: imm
ymmreg2 with mem to ymmreg1
C4: rxb0_3: 0 ymmreg2 101:06:mod ymmreg1 r/m: imm
VTESTPD/VTESTPS — Packed Bit Test
xmmreg2 to xmmreg1
C4: rxb0_2: 0_F 001:0E:11 xmmreg2 xmmreg1
mem to xmmreg1
C4: rxb0_2: 0_F 001:0E:mod xmmreg2 r/m
ymmreg2 to ymmreg1
C4: rxb0_2: 0_F 101:0E:11 ymmreg2 ymmreg1
mem to ymmreg1
C4: rxb0_2: 0_F 101:0E:mod ymmreg2 r/m
xmmreg2 to xmmreg1
C4: rxb0_2: 0_F 001:0F:11 xmmreg1 xmmreg2: imm
mem to xmmreg1
C4: rxb0_2: 0_F 001:0F:mod xmmreg1 r/m: imm
ymmreg2 to ymmreg1
C4: rxb0_2: 0_F 101:0F:11 ymmreg1 ymmreg2: imm
mem to ymmreg1
C4: rxb0_2: 0_F 101:0F:mod ymmreg1 r/m: imm
NOTES:
1. The term “lo” refers to the lower eight registers, 0-7
Vol. 2D B-107
INSTRUCTION FORMATS AND ENCODINGS
B.17 FLOATING-POINT INSTRUCTION FORMATS AND ENCODINGS
Table B-38 shows the five different formats used for floating-point instructions. In all cases, instructions are at
least two bytes long and begin with the bit pattern 11011.
Table B-38. General Floating-Point Instruction Formats
Instruction
First Byte
Second Byte
Optional Fields
1
11011
OPA
1
mod
1
OPB
r/m
s-i-b
disp
2
11011
MF
OPA
mod
OPB
r/m
s-i-b
disp
3
11011
d
P
OPA
1
1
OPB
R
ST(i)
4
11011
0
0
1
1
1
1
OP
5
11011
0
1
1
1
1
1
OP
15-11
10
9
8
7
6
5
4
3
2
1
0
MF = Memory Format
R XOR d = 0 — Destination OP Source
00 — 32-bit real
R XOR d = 1 — Source OP Destination
01 — 32-bit integer
10 — 64-bit real
ST(i) = Register stack element i
11 — 16-bit integer
000 = Stack Top
P = Pop
001 = Second stack element
0 — Do not pop stack
⋅
1 — Pop stack after operation
⋅
d = Destination
⋅
0 — Destination is ST(0)
111 = Eighth stack element
1 — Destination is ST(i)
The Mod and R/M fields of the ModR/M byte have the same interpretation as the corresponding fields of the integer
instructions. The SIB byte and disp (displacement) are optionally present in instructions that have Mod and R/M
fields. Their presence depends on the values of Mod and R/M, as for integer instructions.
Table B-39 shows the formats and encodings of the floating-point instructions.
Table B-39. Floating-Point Instruction Formats and Encodings
Instruction and Format
Encoding
F2XM1 - Compute 2ST(0) - 1
11011 001 : 1111 0000
FABS - Absolute Value
11011 001 : 1110 0001
FADD - Add
ST(0) := ST(0) + 32-bit memory
11011 000 : mod 000 r/m
ST(0) := ST(0) + 64-bit memory
11011 100 : mod 000 r/m
ST(d) := ST(0) + ST(i)
11011 d00 : 11 000 ST(i)
FADDP - Add and Pop
ST(0) := ST(0) + ST(i)
11011 110 : 11 000 ST(i)
FBLD - Load Binary Coded Decimal
11011 111 : mod 100 r/m
FBSTP - Store Binary Coded Decimal and Pop
11011 111 : mod 110 r/m
FCHS - Change Sign
11011 001 : 1110 0000
FCLEX - Clear Exceptions
11011 011 : 1110 0010
FCOM - Compare Real
B-108
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-39. Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format
Encoding
32-bit memory
11011 000 : mod 010 r/m
64-bit memory
11011 100 : mod 010 r/m
ST(i)
11011 000 : 11 010 ST(i)
FCOMP - Compare Real and Pop
32-bit memory
11011 000 : mod 011 r/m
64-bit memory
11011 100 : mod 011 r/m
ST(i)
11011 000 : 11 011 ST(i)
FCOMPP - Compare Real and Pop Twice
11011 110 : 11 011 001
FCOMIP - Compare Real, Set EFLAGS, and Pop
11011 111 : 11 110 ST(i)
FCOS - Cosine of ST(0)
11011 001 : 1111 1111
FDECSTP - Decrement Stack-Top Pointer
11011 001 : 1111 0110
FDIV - Divide
ST(0) := ST(0) ÷ 32-bit memory
11011 000 : mod 110 r/m
ST(0) := ST(0) ÷ 64-bit memory
11011 100 : mod 110 r/m
ST(d) := ST(0) ÷ ST(i)
11011 d00 : 1111 R ST(i)
FDIVP - Divide and Pop
ST(0) := ST(0) ÷ ST(i)
11011 110 : 1111 1 ST(i)
FDIVR - Reverse Divide
ST(0) := 32-bit memory ÷ ST(0)
11011 000 : mod 111 r/m
ST(0) := 64-bit memory ÷ ST(0)
11011 100 : mod 111 r/m
ST(d) := ST(i) ÷ ST(0)
11011 d00 : 1111 R ST(i)
FDIVRP - Reverse Divide and Pop
ST(0) := ST(i) ÷ ST(0)
11011 110 : 1111 0 ST(i)
FFREE - Free ST(i) Register
11011 101 : 1100 0 ST(i)
FIADD - Add Integer
ST(0) := ST(0) + 16-bit memory
11011 110 : mod 000 r/m
ST(0) := ST(0) + 32-bit memory
11011 010 : mod 000 r/m
FICOM - Compare Integer
16-bit memory
11011 110 : mod 010 r/m
32-bit memory
11011 010 : mod 010 r/m
FICOMP - Compare Integer and Pop
16-bit memory
11011 110 : mod 011 r/m
32-bit memory
11011 010 : mod 011 r/m
FIDIV - Divide
ST(0) := ST(0) ÷ 16-bit memory
11011 110 : mod 110 r/m
ST(0) := ST(0) ÷ 32-bit memory
11011 010 : mod 110 r/m
FIDIVR - Reverse Divide
ST(0) := 16-bit memory ÷ ST(0)
11011 110 : mod 111 r/m
Vol. 2D B-109
INSTRUCTION FORMATS AND ENCODINGS
Table B-39. Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format
Encoding
ST(0) := 32-bit memory ÷ ST(0)
11011 010 : mod 111 r/m
FILD - Load Integer
16-bit memory
11011 111 : mod 000 r/m
32-bit memory
11011 011 : mod 000 r/m
64-bit memory
11011 111 : mod 101 r/m
FIMUL- Multiply
ST(0) := ST(0) × 16-bit memory
11011 110 : mod 001 r/m
ST(0) := ST(0) × 32-bit memory
11011 010 : mod 001 r/m
FINCSTP - Increment Stack Pointer
11011 001 : 1111 0111
FINIT - Initialize Floating-Point Unit
FIST - Store Integer
16-bit memory
11011 111 : mod 010 r/m
32-bit memory
11011 011 : mod 010 r/m
FISTP - Store Integer and Pop
16-bit memory
11011 111 : mod 011 r/m
32-bit memory
11011 011 : mod 011 r/m
64-bit memory
11011 111 : mod 111 r/m
FISUB - Subtract
ST(0) := ST(0) - 16-bit memory
11011 110 : mod 100 r/m
ST(0) := ST(0) - 32-bit memory
11011 010 : mod 100 r/m
FISUBR - Reverse Subtract
ST(0) := 16-bit memory − ST(0)
11011 110 : mod 101 r/m
ST(0) := 32-bit memory − ST(0)
11011 010 : mod 101 r/m
FLD - Load Real
32-bit memory
11011 001 : mod 000 r/m
64-bit memory
11011 101 : mod 000 r/m
80-bit memory
11011 011 : mod 101 r/m
ST(i)
11011 001 : 11 000 ST(i)
FLD1 - Load +1.0 into ST(0)
11011 001 : 1110 1000
FLDCW - Load Control Word
11011 001 : mod 101 r/m
FLDENV - Load FPU Environment
11011 001 : mod 100 r/m
FLDL2E - Load log2(ε) into ST(0)
11011 001 : 1110 1010
FLDL2T - Load log2(10) into ST(0)
11011 001 : 1110 1001
FLDLG2 - Load log10(2) into ST(0)
11011 001 : 1110 1100
FLDLN2 - Load logε(2) into ST(0)
11011 001 : 1110 1101
FLDPI - Load π into ST(0)
11011 001 : 1110 1011
FLDZ - Load +0.0 into ST(0)
11011 001 : 1110 1110
FMUL - Multiply
B-110
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-39. Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format
Encoding
ST(0) := ST(0) × 32-bit memory
11011 000 : mod 001 r/m
ST(0) := ST(0) × 64-bit memory
11011 100 : mod 001 r/m
ST(d) := ST(0) × ST(i)
11011 d00 : 1100 1 ST(i)
FMULP - Multiply
ST(i) := ST(0) × ST(i)
11011 110 : 1100 1 ST(i)
FNOP - No Operation
11011 001 : 1101 0000
FPATAN - Partial Arctangent
11011 001 : 1111 0011
FPREM - Partial Remainder
11011 001 : 1111 1000
FPREM1 - Partial Remainder (IEEE)
11011 001 : 1111 0101
FPTAN - Partial Tangent
11011 001 : 1111 0010
FRNDINT - Round to Integer
11011 001 : 1111 1100
FRSTOR - Restore FPU State
11011 101 : mod 100 r/m
FSAVE - Store FPU State
11011 101 : mod 110 r/m
FSCALE - Scale
11011 001 : 1111 1101
FSIN - Sine
11011 001 : 1111 1110
FSINCOS - Sine and Cosine
11011 001 : 1111 1011
FSQRT - Square Root
11011 001 : 1111 1010
FST - Store Real
32-bit memory
11011 001 : mod 010 r/m
64-bit memory
11011 101 : mod 010 r/m
ST(i)
11011 101 : 11 010 ST(i)
FSTCW - Store Control Word
11011 001 : mod 111 r/m
FSTENV - Store FPU Environment
11011 001 : mod 110 r/m
FSTP - Store Real and Pop
32-bit memory
11011 001 : mod 011 r/m
64-bit memory
11011 101 : mod 011 r/m
80-bit memory
11011 011 : mod 111 r/m
ST(i)
11011 101 : 11 011 ST(i)
FSTSW - Store Status Word into AX
11011 111 : 1110 0000
FSTSW - Store Status Word into Memory
11011 101 : mod 111 r/m
FSUB - Subtract
ST(0) := ST(0) - 32-bit memory
11011 000 : mod 100 r/m
ST(0) := ST(0) - 64-bit memory
11011 100 : mod 100 r/m
ST(d) := ST(0) - ST(i)
11011 d00 : 1110 R ST(i)
FSUBP - Subtract and Pop
ST(0) := ST(0) - ST(i)
11011 110 : 1110 1 ST(i)
FSUBR - Reverse Subtract
ST(0) := 32-bit memory - ST(0)
11011 000 : mod 101 r/m
Vol. 2D B-111
INSTRUCTION FORMATS AND ENCODINGS
Table B-39. Floating-Point Instruction Formats and Encodings (Contd.)
Instruction and Format
Encoding
ST(0) := 64-bit memory - ST(0)
11011 100 : mod 101 r/m
ST(d) := ST(i) - ST(0)
11011 d00 : 1110 R ST(i)
FSUBRP - Reverse Subtract and Pop
ST(i) := ST(i) - ST(0)
11011 110 : 1110 0 ST(i)
FTST - Test
11011 001 : 1110 0100
FUCOM - Unordered Compare Real
11011 101 : 1110 0 ST(i)
FUCOMP - Unordered Compare Real and Pop
11011 101 : 1110 1 ST(i)
FUCOMPP - Unordered Compare Real and Pop Twice
11011 010 : 1110 1001
FUCOMI - Unorderd Compare Real and Set EFLAGS
11011 011 : 11 101 ST(i)
FUCOMIP - Unorderd Compare Real, Set EFLAGS, and Pop
11011 111 : 11 101 ST(i)
FXAM - Examine
11011 001 : 1110 0101
FXCH - Exchange ST(0) and ST(i)
11011 001 : 1100 1 ST(i)
FXTRACT - Extract Exponent and Significand
11011 001 : 1111 0100
FYL2X - ST(1) × log2(ST(0))
11011 001 : 1111 0001
FYL2XP1 - ST(1) × log2(ST(0) + 1.0)
11011 001 : 1111 1001
FWAIT - Wait until FPU Ready
1001 1011 (same instruction as WAIT)
B.18 VMX INSTRUCTIONS
Table B-40 describes virtual-machine extensions (VMX).
Table B-40. Encodings for VMX Instructions
Instruction and Format
Encoding
INVEPT—Invalidate Cached EPT Mappings
Descriptor m128 according to reg
01100110 00001111 00111000 10000000: mod reg r/m
INVVPID—Invalidate Cached VPID Mappings
Descriptor m128 according to reg
01100110 00001111 00111000 10000001: mod reg r/m
VMCALL—Call to VM Monitor
Call VMM: causes VM exit.
00001111 00000001 11000001
VMCLEAR—Clear Virtual-Machine Control Structure
mem32:VMCS_data_ptr
01100110 00001111 11000111: mod 110 r/m
mem64:VMCS_data_ptr
01100110 00001111 11000111: mod 110 r/m
VMFUNC—Invoke VM Function
Invoke VM function specified in EAX
00001111 00000001 11010100
VMLAUNCH—Launch Virtual Machine
Launch VM managed by Current_VMCS
00001111 00000001 11000010
VMRESUME—Resume Virtual Machine
Resume VM managed by Current_VMCS
00001111 00000001 11000011
VMPTRLD—Load Pointer to Virtual-Machine Control Structure
mem32 to Current_VMCS_ptr
00001111 11000111: mod 110 r/m
B-112
Vol. 2D
INSTRUCTION FORMATS AND ENCODINGS
Table B-40. Encodings for VMX Instructions
Instruction and Format
Encoding
mem64 to Current_VMCS_ptr
00001111 11000111: mod 110 r/m
VMPTRST—Store Pointer to Virtual-Machine Control Structure
Current_VMCS_ptr to mem32
00001111 11000111: mod 111 r/m
Current_VMCS_ptr to mem64
00001111 11000111: mod 111 r/m
VMREAD—Read Field from Virtual-Machine Control Structure
r32 (VMCS_fieldn) to r32
00001111 01111000: 11 reg2 reg1
r32 (VMCS_fieldn) to mem32
00001111 01111000: mod r32 r/m
r64 (VMCS_fieldn) to r64
00001111 01111000: 11 reg2 reg1
r64 (VMCS_fieldn) to mem64
00001111 01111000: mod r64 r/m
VMWRITE—Write Field to Virtual-Machine Control Structure
r32 to r32 (VMCS_fieldn)
00001111 01111001: 11 reg1 reg2
mem32 to r32 (VMCS_fieldn)
00001111 01111001: mod r32 r/m
r64 to r64 (VMCS_fieldn)
00001111 01111001: 11 reg1 reg2
mem64 to r64 (VMCS_fieldn)
00001111 01111001: mod r64 r/m
VMXOFF—Leave VMX Operation
Leave VMX.
00001111 00000001 11000100
VMXON—Enter VMX Operation
Enter VMX.
11110011 000011111 11000111: mod 110 r/m
B.19 SMX INSTRUCTIONS
Table B-38 describes Safer Mode extensions (VMX). GETSEC leaf functions are selected by a valid value in EAX on input.
Table B-41. Encodings for SMX Instructions
Instruction and Format
Encoding
GETSEC—GETSEC leaf functions are selected by the value in EAX on input
GETSEC[CAPABILITIES]
00001111 00110111 (EAX= 0)
GETSEC[ENTERACCS]
00001111 00110111 (EAX= 2)
GETSEC[EXITAC]
00001111 00110111 (EAX= 3)
GETSEC[SENTER]
00001111 00110111 (EAX= 4)
GETSEC[SEXIT]
00001111 00110111 (EAX= 5)
GETSEC[PARAMETERS]
00001111 00110111 (EAX= 6)
GETSEC[SMCTRL]
00001111 00110111 (EAX= 7)
GETSEC[WAKEUP]
00001111 00110111 (EAX= 8)
Vol. 2D B-113
APPENDIX C
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
The two tables in this appendix itemize the Intel C/C++ compiler intrinsics and functional equivalents for the Intel
MMX technology, SSE, SSE2, SSE3, and SSSE3 instructions.
There may be additional intrinsics that do not have an instruction equivalent. It is strongly recommended that the
reader reference the compiler documentation for the complete list of supported intrinsics. Please refer to
http://www.intel.com/support/performancetools/.
Table C-1 presents simple intrinsics and Table C-2 presents composite intrinsics. Some intrinsics are “composites”
because they require more than one instruction to implement them.
Intel C/C++ Compiler intrinsic names reflect the following naming conventions:
_mm_<intrin_op>_<suffix>
where:
<intrin_op>
Indicates the intrinsics basic operation; for example, add for addition and sub for subtrac-
tion
<suffix>
Denotes the type of data operated on by the instruction. The first one or two letters of
each suffix denotes whether the data is packed (p), extended packed (ep), or scalar (s).
The remaining letters denote the type:
s
single-precision floating-point
d
double precision floating-point
i128
signed 128-bit integer
i64
signed 64-bit integer
u64
unsigned 64-bit integer
i32
signed 32-bit integer
u32
unsigned 32-bit integer
i16
signed 16-bit integer
u16
unsigned 16-bit integer
i8
signed 8-bit integer
u8
unsigned 8-bit integer
The variable r is generally used for the intrinsic's return value. A number appended to a variable name indicates the
element of a packed object. For example, r0 is the lowest word of r.
The packed values are represented in right-to-left order, with the lowest value being used for scalar operations.
Consider the following example operation:
double a[2] = {1.0, 2.0};
__m128d t = _mm_load_pd(a);
The result is the same as either of the following:
__m128d t = _mm_set_pd(2.0, 1.0);
__m128d t = _mm_setr_pd(1.0, 2.0);
In other words, the XMM register that holds the value t will look as follows:
2.0
1.0
127
6463
0
Vol. 2D C-1
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
The “scalar” element is 1.0. Due to the nature of the instruction, some intrinsics require their arguments to be
immediates (constant integer literals).
To use an intrinsic in your code, insert a line with the following syntax:
data_type intrinsic_name (parameters)
Where:
data_type
Is the return data type, which can be either void, int, __m64, __m128, __m128d, or
__m128i. Only the _mm_empty intrinsic returns void.
intrinsic_name
Is the name of the intrinsic, which behaves like a function that you can use in your C/C++
code instead of in-lining the actual instruction.
parameters
Represents the parameters required by each intrinsic.
C.1
SIMPLE INTRINSICS
NOTE
For detailed descriptions of the intrinsics in Table C-1, see the corresponding mnemonic in Chapter
3, “Instruction Set Reference, A-L” of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2A; Chapter 4, “Instruction Set Reference, M-U” of the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 2B; Chapter 5, “Instruction Set Reference, V,” of the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2C; or Chapter 6,
“Instruction Set Reference, W-Z,” of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2D.
Table C-1. Simple Intrinsics
Mnemonic
Intrinsic
ADDPD
__m128d _mm_add_pd(__m128d a, __m128d b)
ADDPS
__m128 _mm_add_ps(__m128 a, __m128 b)
ADDSD
__m128d _mm_add_sd(__m128d a, __m128d b)
ADDSS
__m128 _mm_add_ss(__m128 a, __m128 b)
ADDSUBPD
__m128d _mm_addsub_pd(__m128d a, __m128d b)
ADDSUBPS
__m128 _mm_addsub_ps(__m128 a, __m128 b)
AESDEC
__m128i _mm_aesdec (__m128i, __m128i)
AESDECLAST
__m128i _mm_aesdeclast (__m128i, __m128i)
AESENC
__m128i _mm_aesenc (__m128i, __m128i)
AESENCLAST
__m128i _mm_aesenclast (__m128i, __m128i)
AESIMC
__m128i _mm_aesimc (__m128i)
AESKEYGENASSIST
__m128i _mm_aesimc (__m128i, const int)
ANDNPD
__m128d _mm_andnot_pd(__m128d a, __m128d b)
ANDNPS
__m128 _mm_andnot_ps(__m128 a, __m128 b)
ANDPD
__m128d _mm_and_pd(__m128d a, __m128d b)
ANDPS
__m128 _mm_and_ps(__m128 a, __m128 b)
BLENDPD
__m128d _mm_blend_pd(__m128d v1, __m128d v2, const int mask)
BLENDPS
__m128 _mm_blend_ps(__m128 v1, __m128 v2, const int mask)
BLENDVPD
__m128d _mm_blendv_pd(__m128d v1, __m128d v2, __m128d v3)
BLENDVPS
__m128 _mm_blendv_ps(__m128 v1, __m128 v2, __m128 v3)
CLFLUSH
void _mm_clflush(void const *p)
C-2
Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
CMPPD
__m128d _mm_cmpeq_pd(__m128d a, __m128d b)
__m128d _mm_cmplt_pd(__m128d a, __m128d b)
__m128d _mm_cmple_pd(__m128d a, __m128d b)
__m128d _mm_cmpgt_pd(__m128d a, __m128d b)
__m128d _mm_cmpge_pd(__m128d a, __m128d b)
__m128d _mm_cmpneq_pd(__m128d a, __m128d b)
__m128d _mm_cmpnlt_pd(__m128d a, __m128d b)
__m128d _mm_cmpngt_pd(__m128d a, __m128d b)
__m128d _mm_cmpnge_pd(__m128d a, __m128d b)
__m128d _mm_cmpord_pd(__m128d a, __m128d b)
__m128d _mm_cmpunord_pd(__m128d a, __m128d b)
__m128d _mm_cmpnle_pd(__m128d a, __m128d b)
CMPPS
__m128 _mm_cmpeq_ps(__m128 a, __m128 b)
__m128 _mm_cmplt_ps(__m128 a, __m128 b)
__m128 _mm_cmple_ps(__m128 a, __m128 b)
__m128 _mm_cmpgt_ps(__m128 a, __m128 b)
__m128 _mm_cmpge_ps(__m128 a, __m128 b)
__m128 _mm_cmpneq_ps(__m128 a, __m128 b)
__m128 _mm_cmpnlt_ps(__m128 a, __m128 b)
__m128 _mm_cmpngt_ps(__m128 a, __m128 b)
__m128 _mm_cmpnge_ps(__m128 a, __m128 b)
__m128 _mm_cmpord_ps(__m128 a, __m128 b)
__m128 _mm_cmpunord_ps(__m128 a, __m128 b)
__m128 _mm_cmpnle_ps(__m128 a, __m128 b)
CMPSD
__m128d _mm_cmpeq_sd(__m128d a, __m128d b)
__m128d _mm_cmplt_sd(__m128d a, __m128d b)
__m128d _mm_cmple_sd(__m128d a, __m128d b)
__m128d _mm_cmpgt_sd(__m128d a, __m128d b)
__m128d _mm_cmpge_sd(__m128d a, __m128d b)
__m128 _mm_cmpneq_sd(__m128d a, __m128d b)
__m128 _mm_cmpnlt_sd(__m128d a, __m128d b)
__m128d _mm_cmpnle_sd(__m128d a, __m128d b)
__m128d _mm_cmpngt_sd(__m128d a, __m128d b)
__m128d _mm_cmpnge_sd(__m128d a, __m128d b)
__m128d _mm_cmpord_sd(__m128d a, __m128d b)
__m128d _mm_cmpunord_sd(__m128d a, __m128d b)
CMPSS
__m128 _mm_cmpeq_ss(__m128 a, __m128 b)
__m128 _mm_cmplt_ss(__m128 a, __m128 b)
__m128 _mm_cmple_ss(__m128 a, __m128 b)
__m128 _mm_cmpgt_ss(__m128 a, __m128 b)
__m128 _mm_cmpge_ss(__m128 a, __m128 b)
Vol. 2D C-3
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
__m128 _mm_cmpneq_ss(__m128 a, __m128 b)
__m128 _mm_cmpnlt_ss(__m128 a, __m128 b)
__m128 _mm_cmpnle_ss(__m128 a, __m128 b)
__m128 _mm_cmpngt_ss(__m128 a, __m128 b)
__m128 _mm_cmpnge_ss(__m128 a, __m128 b)
__m128 _mm_cmpord_ss(__m128 a, __m128 b)
__m128 _mm_cmpunord_ss(__m128 a, __m128 b)
COMISD
int _mm_comieq_sd(__m128d a, __m128d b)
int _mm_comilt_sd(__m128d a, __m128d b)
int _mm_comile_sd(__m128d a, __m128d b)
int _mm_comigt_sd(__m128d a, __m128d b)
int _mm_comige_sd(__m128d a, __m128d b)
int _mm_comineq_sd(__m128d a, __m128d b)
COMISS
int _mm_comieq_ss(__m128 a, __m128 b)
int _mm_comilt_ss(__m128 a, __m128 b)
int _mm_comile_ss(__m128 a, __m128 b)
int _mm_comigt_ss(__m128 a, __m128 b)
int _mm_comige_ss(__m128 a, __m128 b)
int _mm_comineq_ss(__m128 a, __m128 b)
CRC32
unsigned int _mm_crc32_u8(unsigned int crc, unsigned char data)
unsigned int _mm_crc32_u16(unsigned int crc, unsigned short data)
unsigned int _mm_crc32_u32(unsigned int crc, unsigned int data)
unsigned __int64 _mm_crc32_u64(unsigned __int64 crc, unsigned __int64 data)
CVTDQ2PD
__m128d _mm_cvtepi32_pd(__m128i a)
CVTDQ2PS
__m128 _mm_cvtepi32_ps(__m128i a)
CVTPD2DQ
__m128i _mm_cvtpd_epi32(__m128d a)
CVTPD2PI
__m64 _mm_cvtpd_pi32(__m128d a)
CVTPD2PS
__m128 _mm_cvtpd_ps(__m128d a)
CVTPI2PD
__m128d _mm_cvtpi32_pd(__m64 a)
CVTPI2PS
__m128 _mm_cvt_pi2ps(__m128 a, __m64 b)
__m128 _mm_cvtpi32_ps(__m128 a, __m64 b)
CVTPS2DQ
__m128i _mm_cvtps_epi32(__m128 a)
CVTPS2PD
__m128d _mm_cvtps_pd(__m128 a)
CVTPS2PI
__m64 _mm_cvt_ps2pi(__m128 a)
__m64 _mm_cvtps_pi32(__m128 a)
CVTSD2SI
int _mm_cvtsd_si32(__m128d a)
CVTSD2SS
__m128 _mm_cvtsd_ss(__m128 a, __m128d b)
CVTSI2SD
__m128d _mm_cvtsi32_sd(__m128d a, int b)
CVTSI2SS
__m128 _mm_cvt_si2ss(__m128 a, int b)
__m128 _mm_cvtsi32_ss(__m128 a, int b)
__m128 _mm_cvtsi64_ss(__m128 a, __int64 b)
CVTSS2SD
__m128d _mm_cvtss_sd(__m128d a, __m128 b)
C-4
Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
CVTSS2SI
int _mm_cvt_ss2si(__m128 a)
int _mm_cvtss_si32(__m128 a)
CVTTPD2DQ
__m128i _mm_cvttpd_epi32(__m128d a)
CVTTPD2PI
__m64 _mm_cvttpd_pi32(__m128d a)
CVTTPS2DQ
__m128i _mm_cvttps_epi32(__m128 a)
CVTTPS2PI
__m64 _mm_cvtt_ps2pi(__m128 a)
__m64 _mm_cvttps_pi32(__m128 a)
CVTTSD2SI
int _mm_cvttsd_si32(__m128d a)
CVTTSS2SI
int _mm_cvtt_ss2si(__m128 a)
int _mm_cvttss_si32(__m128 a)
__m64 _mm_cvtsi32_si64(int i)
int _mm_cvtsi64_si32(__m64 m)
DIVPD
__m128d _mm_div_pd(__m128d a, __m128d b)
DIVPS
__m128 _mm_div_ps(__m128 a, __m128 b)
DIVSD
__m128d _mm_div_sd(__m128d a, __m128d b)
DIVSS
__m128 _mm_div_ss(__m128 a, __m128 b)
DPPD
__m128d _mm_dp_pd(__m128d a, __m128d b, const int mask)
DPPS
__m128 _mm_dp_ps(__m128 a, __m128 b, const int mask)
EMMS
void _mm_empty()
EXTRACTPS
int _mm_extract_ps(__m128 src, const int ndx)
HADDPD
__m128d _mm_hadd_pd(__m128d a, __m128d b)
HADDPS
__m128 _mm_hadd_ps(__m128 a, __m128 b)
HSUBPD
__m128d _mm_hsub_pd(__m128d a, __m128d b)
HSUBPS
__m128 _mm_hsub_ps(__m128 a, __m128 b)
INSERTPS
__m128 _mm_insert_ps(__m128 dst, __m128 src, const int ndx)
LDDQU
__m128i _mm_lddqu_si128(__m128i const *p)
LDMXCSR
__mm_setcsr(unsigned int i)
LFENCE
void _mm_lfence(void)
MASKMOVDQU
void _mm_maskmoveu_si128(__m128i d, __m128i n, char *p)
MASKMOVQ
void _mm_maskmove_si64(__m64 d, __m64 n, char *p)
MAXPD
__m128d _mm_max_pd(__m128d a, __m128d b)
MAXPS
__m128 _mm_max_ps(__m128 a, __m128 b)
MAXSD
__m128d _mm_max_sd(__m128d a, __m128d b)
MAXSS
__m128 _mm_max_ss(__m128 a, __m128 b)
MFENCE
void _mm_mfence(void)
MINPD
__m128d _mm_min_pd(__m128d a, __m128d b)
MINPS
__m128 _mm_min_ps(__m128 a, __m128 b)
MINSD
__m128d _mm_min_sd(__m128d a, __m128d b)
MINSS
__m128 _mm_min_ss(__m128 a, __m128 b)
MONITOR
void _mm_monitor(void const *p, unsigned extensions, unsigned hints)
MOVAPD
__m128d _mm_load_pd(double * p)
void_mm_store_pd(double *p, __m128d a)
Vol. 2D C-5
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
MOVAPS
__m128 _mm_load_ps(float * p)
void_mm_store_ps(float *p, __m128 a)
MOVD
__m128i _mm_cvtsi32_si128(int a)
int _mm_cvtsi128_si32(__m128i a)
__m64 _mm_cvtsi32_si64(int a)
int _mm_cvtsi64_si32(__m64 a)
MOVDDUP
__m128d _mm_movedup_pd(__m128d a)
__m128d _mm_loaddup_pd(double const * dp)
MOVDQA
__m128i _mm_load_si128(__m128i * p)
void_mm_store_si128(__m128i *p, __m128i a)
MOVDQU
__m128i _mm_loadu_si128(__m128i * p)
void_mm_storeu_si128(__m128i *p, __m128i a)
MOVDQ2Q
__m64 _mm_movepi64_pi64(__m128i a)
MOVHLPS
__m128 _mm_movehl_ps(__m128 a, __m128 b)
MOVHPD
__m128d _mm_loadh_pd(__m128d a, double * p)
void _mm_storeh_pd(double * p, __m128d a)
MOVHPS
__m128 _mm_loadh_pi(__m128 a, __m64 * p)
void _mm_storeh_pi(__m64 * p, __m128 a)
MOVLPD
__m128d _mm_loadl_pd(__m128d a, double * p)
void _mm_storel_pd(double * p, __m128d a)
MOVLPS
__m128 _mm_loadl_pi(__m128 a, __m64 *p)
void_mm_storel_pi(__m64 * p, __m128 a)
MOVLHPS
__m128 _mm_movelh_ps(__m128 a, __m128 b)
MOVMSKPD
int _mm_movemask_pd(__m128d a)
MOVMSKPS
int _mm_movemask_ps(__m128 a)
MOVNTDQA
__m128i _mm_stream_load_si128(__m128i *p)
MOVNTDQ
void_mm_stream_si128(__m128i * p, __m128i a)
MOVNTPD
void_mm_stream_pd(double * p, __m128d a)
MOVNTPS
void_mm_stream_ps(float * p, __m128 a)
MOVNTI
void_mm_stream_si32(int * p, int a)
MOVNTQ
void_mm_stream_pi(__m64 * p, __m64 a)
MOVQ
__m128i _mm_loadl_epi64(__m128i * p)
void_mm_storel_epi64(_m128i * p, __m128i a)
__m128i _mm_move_epi64(__m128i a)
MOVQ2DQ
__m128i _mm_movpi64_epi64(__m64 a)
MOVSD
__m128d _mm_load_sd(double * p)
void_mm_store_sd(double * p, __m128d a)
__m128d _mm_move_sd(__m128d a, __m128d b)
MOVSHDUP
__m128 _mm_movehdup_ps(__m128 a)
MOVSLDUP
__m128 _mm_moveldup_ps(__m128 a)
MOVSS
__m128 _mm_load_ss(float * p)
C-6
Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
void_mm_store_ss(float * p, __m128 a)
__m128 _mm_move_ss(__m128 a, __m128 b)
MOVUPD
__m128d _mm_loadu_pd(double * p)
void_mm_storeu_pd(double *p, __m128d a)
MOVUPS
__m128 _mm_loadu_ps(float * p)
void_mm_storeu_ps(float *p, __m128 a)
MPSADBW
__m128i _mm_mpsadbw_epu8(__m128i s1, __m128i s2, const int mask)
MULPD
__m128d _mm_mul_pd(__m128d a, __m128d b)
MULPS
__m128 _mm_mul_ss(__m128 a, __m128 b)
MULSD
__m128d _mm_mul_sd(__m128d a, __m128d b)
MULSS
__m128 _mm_mul_ss(__m128 a, __m128 b)
MWAIT
void _mm_mwait(unsigned extensions, unsigned hints)
ORPD
__m128d _mm_or_pd(__m128d a, __m128d b)
ORPS
__m128 _mm_or_ps(__m128 a, __m128 b)
PABSB
__m64 _mm_abs_pi8 (__m64 a)
__m128i _mm_abs_epi8 (__m128i a)
PABSD
__m64 _mm_abs_pi32 (__m64 a)
__m128i _mm_abs_epi32 (__m128i a)
PABSW
__m64 _mm_abs_pi16 (__m64 a)
__m128i _mm_abs_epi16 (__m128i a)
PACKSSWB
__m128i _mm_packs_epi16(__m128i m1, __m128i m2)
PACKSSWB
__m64 _mm_packs_pi16(__m64 m1, __m64 m2)
PACKSSDW
__m128i _mm_packs_epi32 (__m128i m1, __m128i m2)
PACKSSDW
__m64 _mm_packs_pi32 (__m64 m1, __m64 m2)
PACKUSDW
__m128i _mm_packus_epi32(__m128i m1, __m128i m2)
PACKUSWB
__m128i _mm_packus_epi16(__m128i m1, __m128i m2)
PACKUSWB
__m64 _mm_packs_pu16(__m64 m1, __m64 m2)
PADDB
__m128i _mm_add_epi8(__m128i m1, __m128i m2)
PADDB
__m64 _mm_add_pi8(__m64 m1, __m64 m2)
PADDW
__m128i _mm_add_epi16(__m128i m1, __m128i m2)
PADDW
__m64 _mm_add_pi16(__m64 m1, __m64 m2)
PADDD
__m128i _mm_add_epi32(__m128i m1, __m128i m2)
PADDD
__m64 _mm_add_pi32(__m64 m1, __m64 m2)
PADDQ
__m128i _mm_add_epi64(__m128i m1, __m128i m2)
PADDQ
__m64 _mm_add_si64(__m64 m1, __m64 m2)
PADDSB
__m128i _mm_adds_epi8(__m128i m1, __m128i m2)
PADDSB
__m64 _mm_adds_pi8(__m64 m1, __m64 m2)
PADDSW
__m128i _mm_adds_epi16(__m128i m1, __m128i m2)
PADDSW
__m64 _mm_adds_pi16(__m64 m1, __m64 m2)
PADDUSB
__m128i _mm_adds_epu8(__m128i m1, __m128i m2)
PADDUSB
__m64 _mm_adds_pu8(__m64 m1, __m64 m2)
Vol. 2D C-7
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
PADDUSW
__m128i _mm_adds_epu16(__m128i m1, __m128i m2)
PADDUSW
__m64 _mm_adds_pu16(__m64 m1, __m64 m2)
PALIGNR
__m64 _mm_alignr_pi8 (__m64 a, __m64 b, int n)
__m128i _mm_alignr_epi8 (__m128i a, __m128i b, int n)
PAND
__m128i _mm_and_si128(__m128i m1, __m128i m2)
PAND
__m64 _mm_and_si64(__m64 m1, __m64 m2)
PANDN
__m128i _mm_andnot_si128(__m128i m1, __m128i m2)
PANDN
__m64 _mm_andnot_si64(__m64 m1, __m64 m2)
PAUSE
void _mm_pause(void)
PAVGB
__m128i _mm_avg_epu8(__m128i a, __m128i b)
PAVGB
__m64 _mm_avg_pu8(__m64 a, __m64 b)
PAVGW
__m128i _mm_avg_epu16(__m128i a, __m128i b)
PAVGW
__m64 _mm_avg_pu16(__m64 a, __m64 b)
PBLENDVB
__m128i _mm_blendv_epi (__m128i v1, __m128i v2, __m128i mask)
PBLENDW
__m128i _mm_blend_epi16(__m128i v1, __m128i v2, const int mask)
PCLMULQDQ
__m128i _mm_clmulepi64_si128 (__m128i, __m128i, const int)
PCMPEQB
__m128i _mm_cmpeq_epi8(__m128i m1, __m128i m2)
PCMPEQB
__m64 _mm_cmpeq_pi8(__m64 m1, __m64 m2)
PCMPEQQ
__m128i _mm_cmpeq_epi64(__m128i a, __m128i b)
PCMPEQW
__m128i _mm_cmpeq_epi16 (__m128i m1, __m128i m2)
PCMPEQW
__m64 _mm_cmpeq_pi16 (__m64 m1, __m64 m2)
PCMPEQD
__m128i _mm_cmpeq_epi32(__m128i m1, __m128i m2)
PCMPEQD
__m64 _mm_cmpeq_pi32(__m64 m1, __m64 m2)
PCMPESTRI
int _mm_cmpestri (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestro (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrz (__m128i a, int la, __m128i b, int lb, const int mode)
PCMPESTRM
__m128i _mm_cmpestrm (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestro (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrz (__m128i a, int la, __m128i b, int lb, const int mode)
PCMPGTB
__m128i _mm_cmpgt_epi8 (__m128i m1, __m128i m2)
PCMPGTB
__m64 _mm_cmpgt_pi8 (__m64 m1, __m64 m2)
PCMPGTW
__m128i _mm_cmpgt_epi16(__m128i m1, __m128i m2)
PCMPGTW
__m64 _mm_cmpgt_pi16 (__m64 m1, __m64 m2)
PCMPGTD
__m128i _mm_cmpgt_epi32(__m128i m1, __m128i m2)
PCMPGTD
__m64 _mm_cmpgt_pi32(__m64 m1, __m64 m2)
C-8
Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
PCMPISTRI
__m128i _mm_cmpestrm (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestro (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode)
int _mm_cmpistrz (__m128i a, __m128i b, const int mode)
PCMPISTRM
__m128i _mm_cmpistrm (__m128i a, __m128i b, const int mode)
int _mm_cmpistra (__m128i a, __m128i b, const int mode)
int _mm_cmpistrc (__m128i a, __m128i b, const int mode)
int _mm_cmpistro (__m128i a, __m128i b, const int mode)
int _mm_cmpistrs (__m128i a, __m128i b, const int mode)
int _mm_cmpistrz (__m128i a, __m128i b, const int mode)
PCMPGTQ
__m128i _mm_cmpgt_epi64(__m128i a, __m128i b)
PEXTRB
int _mm_extract_epi8 (__m128i src, const int ndx)
PEXTRD
int _mm_extract_epi32 (__m128i src, const int ndx)
PEXTRQ
__int64 _mm_extract_epi64 (__m128i src, const int ndx)
PEXTRW
int _mm_extract_epi16(__m128i a, int n)
PEXTRW
int _mm_extract_pi16(__m64 a, int n)
int _mm_extract_epi16 (__m128i src, int ndx)
PHADDD
__m64 _mm_hadd_pi32 (__m64 a, __m64 b)
__m128i _mm_hadd_epi32 (__m128i a, __m128i b)
PHADDSW
__m64 _mm_hadds_pi16 (__m64 a, __m64 b)
__m128i _mm_hadds_epi16 (__m128i a, __m128i b)
PHADDW
__m64 _mm_hadd_pi16 (__m64 a, __m64 b)
__m128i _mm_hadd_epi16 (__m128i a, __m128i b)
PHMINPOSUW
__m128i _mm_minpos_epu16( __m128i packed_words)
PHSUBD
__m64 _mm_hsub_pi32 (__m64 a, __m64 b)
__m128i _mm_hsub_epi32 (__m128i a, __m128i b)
PHSUBSW
__m64 _mm_hsubs_pi16 (__m64 a, __m64 b)
__m128i _mm_hsubs_epi16 (__m128i a, __m128i b)
PHSUBW
__m64 _mm_hsub_pi16 (__m64 a, __m64 b)
__m128i _mm_hsub_epi16 (__m128i a, __m128i b)
PINSRB
__m128i _mm_insert_epi8(__m128i s1, int s2, const int ndx)
PINSRD
__m128i _mm_insert_epi32(__m128i s2, int s, const int ndx)
PINSRQ
__m128i _mm_insert_epi64(__m128i s2, __int64 s, const int ndx)
PINSRW
__m128i _mm_insert_epi16(__m128i a, int d, int n)
PINSRW
__m64 _mm_insert_pi16(__m64 a, int d, int n)
PMADDUBSW
__m64 _mm_maddubs_pi16 (__m64 a, __m64 b)
__m128i _mm_maddubs_epi16 (__m128i a, __m128i b)
PMADDWD
__m128i _mm_madd_epi16(__m128i m1 __m128i m2)
PMADDWD
__m64 _mm_madd_pi16(__m64 m1, __m64 m2)
Vol. 2D C-9
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
PMAXSB
__m128i _mm_max_epi8( __m128i a, __m128i b)
PMAXSD
__m128i _mm_max_epi32( __m128i a, __m128i b)
PMAXSW
__m128i _mm_max_epi16(__m128i a, __m128i b)
PMAXSW
__m64 _mm_max_pi16(__m64 a, __m64 b)
PMAXUB
__m128i _mm_max_epu8(__m128i a, __m128i b)
PMAXUB
__m64 _mm_max_pu8(__m64 a, __m64 b)
PMAXUD
__m128i _mm_max_epu32( __m128i a, __m128i b)
PMAXUW
__m128i _mm_max_epu16( __m128i a, __m128i b)
PMINSB
_m128i _mm_min_epi8( __m128i a, __m128i b)
PMINSD
__m128i _mm_min_epi32( __m128i a, __m128i b)
PMINSW
__m128i _mm_min_epi16(__m128i a, __m128i b)
PMINSW
__m64 _mm_min_pi16(__m64 a, __m64 b)
PMINUB
__m128i _mm_min_epu8(__m128i a, __m128i b)
PMINUB
__m64 _mm_min_pu8(__m64 a, __m64 b)
PMINUD
__m128i _mm_min_epu32 ( __m128i a, __m128i b)
PMINUW
__m128i _mm_min_epu16 ( __m128i a, __m128i b)
PMOVMSKB
int _mm_movemask_epi8(__m128i a)
PMOVMSKB
int _mm_movemask_pi8(__m64 a)
PMOVSXBW
__m128i _mm_ cvtepi8_epi16( __m128i a)
PMOVSXBD
__m128i _mm_ cvtepi8_epi32( __m128i a)
PMOVSXBQ
__m128i _mm_ cvtepi8_epi64( __m128i a)
PMOVSXWD
__m128i _mm_ cvtepi16_epi32( __m128i a)
PMOVSXWQ
__m128i _mm_ cvtepi16_epi64( __m128i a)
PMOVSXDQ
__m128i _mm_ cvtepi32_epi64( __m128i a)
PMOVZXBW
__m128i _mm_ cvtepu8_epi16( __m128i a)
PMOVZXBD
__m128i _mm_ cvtepu8_epi32( __m128i a)
PMOVZXBQ
__m128i _mm_ cvtepu8_epi64( __m128i a)
PMOVZXWD
__m128i _mm_ cvtepu16_epi32( __m128i a)
PMOVZXWQ
__m128i _mm_ cvtepu16_epi64( __m128i a)
PMOVZXDQ
__m128i _mm_ cvtepu32_epi64( __m128i a)
PMULDQ
__m128i _mm_mul_epi32( __m128i a, __m128i b)
PMULHRSW
__m64 _mm_mulhrs_pi16 (__m64 a, __m64 b)
__m128i _mm_mulhrs_epi16 (__m128i a, __m128i b)
PMULHUW
__m128i _mm_mulhi_epu16(__m128i a, __m128i b)
PMULHUW
__m64 _mm_mulhi_pu16(__m64 a, __m64 b)
PMULHW
__m128i _mm_mulhi_epi16(__m128i m1, __m128i m2)
PMULHW
__m64 _mm_mulhi_pi16(__m64 m1, __m64 m2)
PMULLUD
__m128i _mm_mullo_epi32(__m128i a, __m128i b)
PMULLW
__m128i _mm_mullo_epi16(__m128i m1, __m128i m2)
PMULLW
__m64 _mm_mullo_pi16(__m64 m1, __m64 m2)
C-10
Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
PMULUDQ
__m64 _mm_mul_su32(__m64 m1, __m64 m2)
__m128i _mm_mul_epu32(__m128i m1, __m128i m2)
POPCNT
int _mm_popcnt_u32(unsigned int a)
int64_t _mm_popcnt_u64(unsigned __int64 a)
POR
__m64 _mm_or_si64(__m64 m1, __m64 m2)
POR
__m128i _mm_or_si128(__m128i m1, __m128i m2)
PREFETCHh
void _mm_prefetch(char *a, int sel)
PSADBW
__m128i _mm_sad_epu8(__m128i a, __m128i b)
PSADBW
__m64 _mm_sad_pu8(__m64 a, __m64 b)
PSHUFB
__m64 _mm_shuffle_pi8 (__m64 a, __m64 b)
__m128i _mm_shuffle_epi8 (__m128i a, __m128i b)
PSHUFD
__m128i _mm_shuffle_epi32(__m128i a, int n)
PSHUFHW
__m128i _mm_shufflehi_epi16(__m128i a, int n)
PSHUFLW
__m128i _mm_shufflelo_epi16(__m128i a, int n)
PSHUFW
__m64 _mm_shuffle_pi16(__m64 a, int n)
PSIGNB
__m64 _mm_sign_pi8 (__m64 a, __m64 b)
__m128i _mm_sign_epi8 (__m128i a, __m128i b)
PSIGND
__m64 _mm_sign_pi32 (__m64 a, __m64 b)
__m128i _mm_sign_epi32 (__m128i a, __m128i b)
PSIGNW
__m64 _mm_sign_pi16 (__m64 a, __m64 b)
__m128i _mm_sign_epi16 (__m128i a, __m128i b)
PSLLW
__m128i _mm_sll_epi16(__m128i m, __m128i count)
PSLLW
__m128i _mm_slli_epi16(__m128i m, int count)
PSLLW
__m64 _mm_sll_pi16(__m64 m, __m64 count)
__m64 _mm_slli_pi16(__m64 m, int count)
PSLLD
__m128i _mm_slli_epi32(__m128i m, int count)
__m128i _mm_sll_epi32(__m128i m, __m128i count)
PSLLD
__m64 _mm_slli_pi32(__m64 m, int count)
__m64 _mm_sll_pi32(__m64 m, __m64 count)
PSLLQ
__m64 _mm_sll_si64(__m64 m, __m64 count)
__m64 _mm_slli_si64(__m64 m, int count)
PSLLQ
__m128i _mm_sll_epi64(__m128i m, __m128i count)
__m128i _mm_slli_epi64(__m128i m, int count)
PSLLDQ
__m128i _mm_slli_si128(__m128i m, int imm)
PSRAW
__m128i _mm_sra_epi16(__m128i m, __m128i count)
__m128i _mm_srai_epi16(__m128i m, int count)
PSRAW
__m64 _mm_sra_pi16(__m64 m, __m64 count)
__m64 _mm_srai_pi16(__m64 m, int count)
PSRAD
__m128i _mm_sra_epi32 (__m128i m, __m128i count)
__m128i _mm_srai_epi32 (__m128i m, int count)
PSRAD
__m64 _mm_sra_pi32 (__m64 m, __m64 count)
Vol. 2D C-11
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
__m64 _mm_srai_pi32 (__m64 m, int count)
PSRLW
_m128i _mm_srl_epi16 (__m128i m, __m128i count)
__m128i _mm_srli_epi16 (__m128i m, int count)
__m64 _mm_srl_pi16 (__m64 m, __m64 count)
__m64 _mm_srli_pi16(__m64 m, int count)
PSRLD
__m128i _mm_srl_epi32 (__m128i m, __m128i count)
__m128i _mm_srli_epi32 (__m128i m, int count)
PSRLD
__m64 _mm_srl_pi32 (__m64 m, __m64 count)
__m64 _mm_srli_pi32 (__m64 m, int count)
PSRLQ
__m128i _mm_srl_epi64 (__m128i m, __m128i count)
__m128i _mm_srli_epi64 (__m128i m, int count)
PSRLQ
__m64 _mm_srl_si64 (__m64 m, __m64 count)
__m64 _mm_srli_si64 (__m64 m, int count)
PSRLDQ
__m128i _mm_srli_si128(__m128i m, int imm)
PSUBB
__m128i _mm_sub_epi8(__m128i m1, __m128i m2)
PSUBB
__m64 _mm_sub_pi8(__m64 m1, __m64 m2)
PSUBW
__m128i _mm_sub_epi16(__m128i m1, __m128i m2)
PSUBW
__m64 _mm_sub_pi16(__m64 m1, __m64 m2)
PSUBD
__m128i _mm_sub_epi32(__m128i m1, __m128i m2)
PSUBD
__m64 _mm_sub_pi32(__m64 m1, __m64 m2)
PSUBQ
__m128i _mm_sub_epi64(__m128i m1, __m128i m2)
PSUBQ
__m64 _mm_sub_si64(__m64 m1, __m64 m2)
PSUBSB
__m128i _mm_subs_epi8(__m128i m1, __m128i m2)
PSUBSB
__m64 _mm_subs_pi8(__m64 m1, __m64 m2)
PSUBSW
__m128i _mm_subs_epi16(__m128i m1, __m128i m2)
PSUBSW
__m64 _mm_subs_pi16(__m64 m1, __m64 m2)
PSUBUSB
__m128i _mm_subs_epu8(__m128i m1, __m128i m2)
PSUBUSB
__m64 _mm_subs_pu8(__m64 m1, __m64 m2)
PSUBUSW
__m128i _mm_subs_epu16(__m128i m1, __m128i m2)
PSUBUSW
__m64 _mm_subs_pu16(__m64 m1, __m64 m2)
PTEST
int _mm_testz_si128(__m128i s1, __m128i s2)
int _mm_testc_si128(__m128i s1, __m128i s2)
int _mm_testnzc_si128(__m128i s1, __m128i s2)
PUNPCKHBW
__m64 _mm_unpackhi_pi8(__m64 m1, __m64 m2)
PUNPCKHBW
__m128i _mm_unpackhi_epi8(__m128i m1, __m128i m2)
PUNPCKHWD
__m64 _mm_unpackhi_pi16(__m64 m1,__m64 m2)
PUNPCKHWD
__m128i _mm_unpackhi_epi16(__m128i m1, __m128i m2)
PUNPCKHDQ
___m64 _mm_unpackhi_pi32(__m64 m1, __m64 m2)
PUNPCKHDQ
__m128i _mm_unpackhi_epi32(__m128i m1, __m128i m2)
PUNPCKHQDQ
__m128i _mm_unpackhi_epi64(__m128i m1, __m128i m2)
PUNPCKLBW
__m64 _mm_unpacklo_pi8 (__m64 m1, __m64 m2)
C-12
Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
PUNPCKLBW
__m128i _mm_unpacklo_epi8 (__m128i m1, __m128i m2)
PUNPCKLWD
__m64 _mm_unpacklo_pi16(__m64 m1, __m64 m2)
PUNPCKLWD
__m128i _mm_unpacklo_epi16(__m128i m1, __m128i m2)
PUNPCKLDQ
__m64 _mm_unpacklo_pi32(__m64 m1, __m64 m2)
PUNPCKLDQ
__m128i _mm_unpacklo_epi32(__m128i m1, __m128i m2)
PUNPCKLQDQ
__m128i _mm_unpacklo_epi64(__m128i m1, __m128i m2)
PXOR
__m64 _mm_xor_si64(__m64 m1, __m64 m2)
PXOR
__m128i _mm_xor_si128(__m128i m1, __m128i m2)
RCPPS
__m128 _mm_rcp_ps(__m128 a)
RCPSS
__m128 _mm_rcp_ss(__m128 a)
ROUNDPD
__m128 mm_round_pd(__m128d s1, int iRoundMode)
__m128 mm_floor_pd(__m128d s1)
__m128 mm_ceil_pd(__m128d s1)
ROUNDPS
__m128 mm_round_ps(__m128 s1, int iRoundMode)
__m128 mm_floor_ps(__m128 s1)
__m128 mm_ceil_ps(__m128 s1)
ROUNDSD
__m128d mm_round_sd(__m128d dst, __m128d s1, int iRoundMode)
__m128d mm_floor_sd(__m128d dst, __m128d s1)
__m128d mm_ceil_sd(__m128d dst, __m128d s1)
ROUNDSS
__m128 mm_round_ss(__m128 dst, __m128 s1, int iRoundMode)
__m128 mm_floor_ss(__m128 dst, __m128 s1)
__m128 mm_ceil_ss(__m128 dst, __m128 s1)
RSQRTPS
__m128 _mm_rsqrt_ps(__m128 a)
RSQRTSS
__m128 _mm_rsqrt_ss(__m128 a)
SFENCE
void_mm_sfence(void)
SHUFPD
__m128d _mm_shuffle_pd(__m128d a, __m128d b, unsigned int imm8)
SHUFPS
__m128 _mm_shuffle_ps(__m128 a, __m128 b, unsigned int imm8)
SQRTPD
__m128d _mm_sqrt_pd(__m128d a)
SQRTPS
__m128 _mm_sqrt_ps(__m128 a)
SQRTSD
__m128d _mm_sqrt_sd(__m128d a)
SQRTSS
__m128 _mm_sqrt_ss(__m128 a)
STMXCSR
_mm_getcsr(void)
SUBPD
__m128d _mm_sub_pd(__m128d a, __m128d b)
SUBPS
__m128 _mm_sub_ps(__m128 a, __m128 b)
SUBSD
__m128d _mm_sub_sd(__m128d a, __m128d b)
SUBSS
__m128 _mm_sub_ss(__m128 a, __m128 b)
UCOMISD
int _mm_ucomieq_sd(__m128d a, __m128d b)
int _mm_ucomilt_sd(__m128d a, __m128d b)
int _mm_ucomile_sd(__m128d a, __m128d b)
int _mm_ucomigt_sd(__m128d a, __m128d b)
int _mm_ucomige_sd(__m128d a, __m128d b)
Vol. 2D C-13
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-1. Simple Intrinsics (Contd.)
Mnemonic
Intrinsic
int _mm_ucomineq_sd(__m128d a, __m128d b)
UCOMISS
int _mm_ucomieq_ss(__m128 a, __m128 b)
int _mm_ucomilt_ss(__m128 a, __m128 b)
int _mm_ucomile_ss(__m128 a, __m128 b)
int _mm_ucomigt_ss(__m128 a, __m128 b)
int _mm_ucomige_ss(__m128 a, __m128 b)
int _mm_ucomineq_ss(__m128 a, __m128 b)
UNPCKHPD
__m128d _mm_unpackhi_pd(__m128d a, __m128d b)
UNPCKHPS
__m128 _mm_unpackhi_ps(__m128 a, __m128 b)
UNPCKLPD
__m128d _mm_unpacklo_pd(__m128d a, __m128d b)
UNPCKLPS
__m128 _mm_unpacklo_ps(__m128 a, __m128 b)
XORPD
__m128d _mm_xor_pd(__m128d a, __m128d b)
XORPS
__m128 _mm_xor_ps(__m128 a, __m128 b)
C.2
COMPOSITE INTRINSICS
Table C-2. Composite Intrinsics
Mnemonic
Intrinsic
(composite)
__m128i _mm_set_epi64(__m64 q1, __m64 q0)
(composite)
__m128i _mm_set_epi32(int i3, int i2, int i1, int i0)
(composite)
__m128i _mm_set_epi16(short w7,short w6, short w5, short w4, short w3, short w2,
short w1,short w0)
(composite)
__m128i _mm_set_epi8(char w15,char w14, char w13, char w12, char w11, char w10,
char w9, char w8, char w7,char w6, char w5, char w4, char w3, char w2,char w1, char w0)
(composite)
__m128i _mm_set1_epi64(__m64 q)
(composite)
__m128i _mm_set1_epi32(int a)
(composite)
__m128i _mm_set1_epi16(short a)
(composite)
__m128i _mm_set1_epi8(char a)
(composite)
__m128i _mm_setr_epi64(__m64 q1, __m64 q0)
(composite)
__m128i _mm_setr_epi32(int i3, int i2, int i1, int i0)
(composite)
__m128i _mm_setr_epi16(short w7,short w6, short w5, short w4, short w3, short w2, short w,
short w0)
(composite)
__m128i _mm_setr_epi8(char w15,char w14, char w13, char w12, char w11, char w10,
char w9, char w8,char w7, char w6,char w5, char w4, char w3, char w2,char w1,char w0)
(composite)
__m128i _mm_setzero_si128()
(composite)
__m128 _mm_set_ps1(float w)
__m128 _mm_set1_ps(float w)
(composite)
__m128cmm_set1_pd(double w)
(composite)
__m128d _mm_set_sd(double w)
(composite)
__m128d _mm_set_pd(double z, double y)
(composite)
__m128 _mm_set_ps(float z, float y, float x, float w)
(composite)
__m128d _mm_setr_pd(double z, double y)
(composite)
__m128 _mm_setr_ps(float z, float y, float x, float w)
C-14
Vol. 2D
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
Table C-2. Composite Intrinsics (Contd.)
Mnemonic
Intrinsic
(composite)
__m128d _mm_setzero_pd(void)
(composite)
__m128 _mm_setzero_ps(void)
MOVSD + shuffle
__m128d _mm_load_pd(double * p)
__m128d _mm_load1_pd(double *p)
MOVSS + shuffle
__m128 _mm_load_ps1(float * p)
__m128 _mm_load1_ps(float *p)
MOVAPD + shuffle
__m128d _mm_loadr_pd(double * p)
MOVAPS + shuffle
__m128 _mm_loadr_ps(float * p)
MOVSD + shuffle
void _mm_store1_pd(double *p, __m128d a)
MOVSS + shuffle
void _mm_store_ps1(float * p, __m128 a)
void _mm_store1_ps(float *p, __m128 a)
MOVAPD + shuffle
_mm_storer_pd(double * p, __m128d a)
MOVAPS + shuffle
_mm_storer_ps(float * p, __m128 a)
Vol. 2D C-15

 

 

 

 

 

 

 

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