Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 99
INSTRUCTION SET REFERENCE, V
Other Exceptions
EVEX-encoded instructions, see Table 2-49, “Type E4 Class Exception Conditions.”
VFPCLASSPH—Test Types of Packed FP16 Values
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5-327
INSTRUCTION SET REFERENCE, V
VFPCLASSPS—Tests Types of Packed Float32 Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F3A.W0 66 /r ib
A
V/V
AVX512VL
Tests the input for the following categories: NaN, +0, -0,
VFPCLASSPS k2 {k1},
AVX512DQ
+Infinity, -Infinity, denormal, finite negative. The immediate
xmm2/m128/m32bcst, imm8
field provides a mask bit for each of these category tests. The
masked test results are OR-ed together to form a mask result.
EVEX.256.66.0F3A.W0 66 /r ib
A
V/V
AVX512VL
Tests the input for the following categories: NaN, +0, -0,
VFPCLASSPS k2 {k1},
AVX512DQ
+Infinity, -Infinity, denormal, finite negative. The immediate
ymm2/m256/m32bcst, imm8
field provides a mask bit for each of these category tests. The
masked test results are OR-ed together to form a mask result.
EVEX.512.66.0F3A.W0 66 /r ib
A
V/V
AVX512DQ
Tests the input for the following categories: NaN, +0, -0,
VFPCLASSPS k2 {k1},
+Infinity, -Infinity, denormal, finite negative. The immediate
zmm2/m512/m32bcst, imm8
field provides a mask bit for each of these category tests. The
masked test results are OR-ed together to form a mask result.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
The FPCLASSPS instruction checks the packed single-precision floating-point values for special categories, speci-
fied by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input
data element is classified against. The classified results of all specified categories of an input value are ORed
together to form the final boolean result for the input element. The result of each element is written to the corre-
sponding bit in a mask register k2 according to the writemask k1. Bits [MAX_KL-1:16/8/4] of the destination are
cleared.
The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category
is listed in Table 5-4.
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector
broadcasted from a 32-bit memory location.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
CheckFPClassSP (tsrc[31:0], imm8[7:0]){
//* Start checking the source operand for special type *//
NegNum := tsrc[31];
IF (tsrc[30:23]=0FFh) Then ExpAllOnes := 1; FI;
IF (tsrc[30:23]=0h) Then ExpAllZeros := 1;
IF (ExpAllZeros AND MXCSR.DAZ) Then
MantAllZeros := 1;
ELSIF (tsrc[22:0]=0h) Then
MantAllZeros := 1;
FI;
ZeroNumber= ExpAllZeros AND MantAllZeros
SignalingBit= tsrc[22];
sNaN_res := ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit); // sNaN
qNaN_res := ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit; // qNaN
Pzero_res := NOT(NegNum) AND ExpAllZeros AND MantAllZeros; // +0
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VFPCLASSPS—Tests Types of Packed Float32 Values
INSTRUCTION SET REFERENCE, V
Nzero_res := NegNum AND ExpAllZeros AND MantAllZeros; // -0
PInf_res := NOT(NegNum) AND ExpAllOnes AND MantAllZeros; // +Inf
NInf_res := NegNum AND ExpAllOnes AND MantAllZeros; // -Inf
Denorm_res := ExpAllZeros AND NOT(MantAllZeros); // denorm
FinNeg_res := NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber); // -finite
bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR
( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR
( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR
( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res );
Return bResult;
} //* end of CheckSPClassSP() *//
VFPCLASSPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1) AND (SRC *is memory*)
THEN
DEST[j] := CheckFPClassDP(SRC1[31:0], imm8[7:0]);
ELSE
DEST[j] := CheckFPClassDP(SRC1[i+31:i], imm8[7:0]);
FI;
ELSE DEST[j] := 0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VFPCLASSPS __mmask16 _mm512_fpclass_ps_mask( __m512 a, int c);
VFPCLASSPS __mmask16 _mm512_mask_fpclass_ps_mask( __mmask16 m, __m512 a, int c)
VFPCLASSPS __mmask8 _mm256_fpclass_ps_mask( __m256 a, int c)
VFPCLASSPS __mmask8 _mm256_mask_fpclass_ps_mask( __mmask8 m, __m256 a, int c)
VFPCLASSPS __mmask8 _mm_fpclass_ps_mask( __m128 a, int c)
VFPCLASSPS __mmask8 _mm_mask_fpclass_ps_mask( __mmask8 m, __m128 a, int c)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-49, “Type E4 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VFPCLASSPS—Tests Types of Packed Float32 Values
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5-329
INSTRUCTION SET REFERENCE, V
VFPCLASSSD—Tests Type of a Scalar Float64 Value
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.LLIG.66.0F3A.W1 67 /r ib
A
V/V
AVX512DQ
Tests the input for the following categories: NaN, +0, -0,
VFPCLASSSD k2 {k1},
+Infinity, -Infinity, denormal, finite negative. The immediate
xmm2/m64, imm8
field provides a mask bit for each of these category tests. The
masked test results are OR-ed together to form a mask result.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
The FPCLASSSD instruction checks the low double precision floating-point value in the source operand for special
categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point
values that the input data element is classified against. The classified results of all specified categories of an input
value are ORed together to form the final boolean result for the input element. The result is written to the low bit in
a mask register k2 according to the writemask k1. Bits MAX_KL-1: 1 of the destination are cleared.
The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category
is listed in Table 5-4.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
CheckFPClassDP (tsrc[63:0], imm8[7:0]){
NegNum := tsrc[63];
IF (tsrc[62:52]=07FFh) Then ExpAllOnes := 1; FI;
IF (tsrc[62:52]=0h) Then ExpAllZeros := 1;
IF (ExpAllZeros AND MXCSR.DAZ) Then
MantAllZeros := 1;
ELSIF (tsrc[51:0]=0h) Then
MantAllZeros := 1;
FI;
ZeroNumber := ExpAllZeros AND MantAllZeros
SignalingBit := tsrc[51];
sNaN_res := ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit); // sNaN
qNaN_res := ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit; // qNaN
Pzero_res := NOT(NegNum) AND ExpAllZeros AND MantAllZeros; // +0
Nzero_res := NegNum AND ExpAllZeros AND MantAllZeros; // -0
PInf_res := NOT(NegNum) AND ExpAllOnes AND MantAllZeros; // +Inf
NInf_res := NegNum AND ExpAllOnes AND MantAllZeros; // -Inf
Denorm_res := ExpAllZeros AND NOT(MantAllZeros); // denorm
FinNeg_res := NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber); // -finite
bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR
( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR
( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR
( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res );
Return bResult;
} //* end of CheckFPClassDP() *//
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VFPCLASSSD—Tests Type of a Scalar Float64 Value
INSTRUCTION SET REFERENCE, V
VFPCLASSSD (EVEX encoded version)
IF k1[0] OR *no writemask*
THEN DEST[0] :=
CheckFPClassDP(SRC1[63:0], imm8[7:0])
ELSE DEST[0] := 0
; zeroing-masking only
FI;
DEST[MAX_KL-1:1] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VFPCLASSSD __mmask8 _mm_fpclass_sd_mask( __m128d a, int c)
VFPCLASSSD __mmask8 _mm_mask_fpclass_sd_mask( __mmask8 m, __m128d a, int c)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-53, “Type E6 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VFPCLASSSD—Tests Type of a Scalar Float64 Value
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INSTRUCTION SET REFERENCE, V
VFPCLASSSH—Test Types of Scalar FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.NP.0F3A.W0 67 /r /ib
A
V/V
AVX512-FP16
Test the input for the following categories: NaN,
VFPCLASSSH k1{k2}, xmm1/m16,
+0, -0, +Infinity, -Infinity, denormal, finite
imm8
negative. The immediate field provides a mask
bit for each of these category tests. The masked
test results are OR-ed together to form a mask
result.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
ModRM:r/m (r)
imm8 (r)
N/A
Description
This instruction checks the low FP16 value in the source operand for special categories, specified by the set bits in
the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input data element is clas-
sified against; see Table 5-8 for the categories. The classified results of all specified categories of an input value are
ORed together to form the final boolean result for the input element. The result is written to the low bit in the desti-
nation mask register according to the writemask. The other bits in the destination mask register are zeroed.
Operation
VFPCLASSSH dest{k2}, src, imm8
IF k2[0] or *no writemask*:
DEST.bit[0] := check_fp_class_fp16(src.fp16[0], imm8)
// see VFPCLASSPH
ELSE:
DEST.bit[0] := 0
DEST[MAXKL-1:1] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VFPCLASSSH __mmask8 _mm_fpclass_sh_mask (__m128h a, int imm8);
VFPCLASSSH __mmask8 _mm_mask_fpclass_sh_mask (__mmask8 k1, __m128h a, int imm8);
SIMD Floating-Point Exceptions
None
Other Exceptions
EVEX-encoded instructions, see Table 2-58, “Type E10 Class Exception Conditions.”
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Vol. 2C
VFPCLASSSH—Test Types of Scalar FP16 Values
INSTRUCTION SET REFERENCE, V
VFPCLASSSS—Tests Type of a Scalar Float32 Value
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.LLIG.66.0F3A.W0 67 /r
A
V/V
AVX512DQ
Tests the input for the following categories: NaN, +0, -0,
VFPCLASSSS k2 {k1},
+Infinity, -Infinity, denormal, finite negative. The immediate
xmm2/m32, imm8
field provides a mask bit for each of these category tests. The
masked test results are OR-ed together to form a mask result.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
The FPCLASSSS instruction checks the low single-precision floating-point value in the source operand for special
categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point
values that the input data element is classified against. The classified results of all specified categories of an input
value are ORed together to form the final boolean result for the input element. The result is written to the low bit
in a mask register k2 according to the writemask k1. Bits MAX_KL-1: 1 of the destination are cleared.
The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category
is listed in Table 5-4.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Operation
CheckFPClassSP (tsrc[31:0], imm8[7:0]){
//* Start checking the source operand for special type *//
NegNum := tsrc[31];
IF (tsrc[30:23]=0FFh) Then ExpAllOnes := 1; FI;
IF (tsrc[30:23]=0h) Then ExpAllZeros := 1;
IF (ExpAllZeros AND MXCSR.DAZ) Then
MantAllZeros := 1;
ELSIF (tsrc[22:0]=0h) Then
MantAllZeros := 1;
FI;
ZeroNumber= ExpAllZeros AND MantAllZeros
SignalingBit= tsrc[22];
sNaN_res := ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit); // sNaN
qNaN_res := ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit; // qNaN
Pzero_res := NOT(NegNum) AND ExpAllZeros AND MantAllZeros; // +0
Nzero_res := NegNum AND ExpAllZeros AND MantAllZeros; // -0
PInf_res := NOT(NegNum) AND ExpAllOnes AND MantAllZeros; // +Inf
NInf_res := NegNum AND ExpAllOnes AND MantAllZeros; // -Inf
Denorm_res := ExpAllZeros AND NOT(MantAllZeros); // denorm
FinNeg_res := NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber); // -finite
bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR
( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR
( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR
( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res );
Return bResult;
VFPCLASSSS—Tests Type of a Scalar Float32 Value
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5-333
INSTRUCTION SET REFERENCE, V
} //* end of CheckSPClassSP() *//
VFPCLASSSS (EVEX encoded version)
IF k1[0] OR *no writemask*
THEN DEST[0] :=
CheckFPClassSP(SRC1[31:0], imm8[7:0])
ELSE DEST[0] := 0
; zeroing-masking only
FI;
DEST[MAX_KL-1:1] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VFPCLASSSS __mmask8 _mm_fpclass_ss_mask( __m128 a, int c)
VFPCLASSSS __mmask8 _mm_mask_fpclass_ss_mask( __mmask8 m, __m128 a, int c)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-53, “Type E6 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
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VFPCLASSSS—Tests Type of a Scalar Float32 Value
INSTRUCTION SET REFERENCE, V
VGATHERDPD/VGATHERQPD—Gather Packed Double Precision Floating-Point Values Using
Signed Dword/Qword Indices
Opcode/
Op/
64/3
CPUID
Description
Instruction
En
2-bit
Feature
Mode
Flag
VEX.128.66.0F38.W1 92 /r
RMV
V/V
AVX2
Using dword indices specified in vm32x, gather double pre-
VGATHERDPD xmm1, vm32x, xmm2
cision floating-point values from memory conditioned on
mask specified by xmm2. Conditionally gathered elements
are merged into xmm1.
VEX.128.66.0F38.W1 93 /r
RMV
V/V
AVX2
Using qword indices specified in vm64x, gather double pre-
VGATHERQPD xmm1, vm64x, xmm2
cision floating-point values from memory conditioned on
mask specified by xmm2. Conditionally gathered elements
are merged into xmm1.
VEX.256.66.0F38.W1 92 /r
RMV
V/V
AVX2
Using dword indices specified in vm32x, gather double pre-
VGATHERDPD ymm1, vm32x, ymm2
cision floating-point values from memory conditioned on
mask specified by ymm2. Conditionally gathered elements
are merged into ymm1.
VEX.256.66.0F38.W1 93 /r
RMV
V/V
AVX2
Using qword indices specified in vm64y, gather double pre-
VGATHERQPD ymm1, vm64y, ymm2
cision floating-point values from memory conditioned on
mask specified by ymm2. Conditionally gathered elements
are merged into ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMV
ModRM:reg (r,w)
BaseReg (R): VSIB:base,
VEX.vvvv (r, w)
N/A
VectorReg(R): VSIB:index
Description
The instruction conditionally loads up to 2 or 4 double precision floating-point values from memory addresses spec-
ified by the memory operand (the second operand) and using qword indices. The memory operand uses the VSIB
form of the SIB byte to specify a general purpose register operand as the common base, a vector register for an
array of indices relative to the base and a constant scale factor.
The mask operand (the third operand) specifies the conditional load operation from each memory address and the
corresponding update of each data element of the destination operand (the first operand). Conditionality is speci-
fied by the most significant bit of each data element of the mask register. If an element’s mask bit is not set, the
corresponding element of the destination register is left unchanged. The width of data element in the destination
register and mask register are identical. The entire mask register will be set to zero by this instruction unless the
instruction causes an exception.
Using dword indices in the lower half of the mask register, the instruction conditionally loads up to 2 or 4 double
precision floating-point values from the VSIB addressing memory operand, and updates the destination register.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask operand are partially updated; those elements that have been gathered are placed into the
destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gath-
ered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
If the data size and index size are different, part of the destination register and part of the mask register do not
correspond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both
of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception
before gathering any elements.
VEX.128 version: The instruction will gather two double precision floating-point values. For dword indices, only the
lower two indices in the vector index register are used.
VGATHERDPD/VGATHERQPD—Gather Packed Double Precision Floating-Point Values Using Signed Dword/Qword Indices
Vol. 2C
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INSTRUCTION SET REFERENCE, V
VEX.256 version: The instruction will gather four double precision floating-point values. For dword indices, only the
lower four indices in the vector index register are used.
Note that:
• If any pair of the index, mask, or destination registers are the same, this instruction results a #UD fault.
• The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
64 memory-ordering model.
• Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer
to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the
conventional order.
• Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
• This instruction does not perform AC checks, and so will never deliver an AC fault.
• This instruction will cause a #UD if the address size attribute is 16-bit.
• This instruction will cause a #UD if the memory operand is encoded without the SIB byte.
• This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does
is implementation specific, and some implementations may use loads larger than the data element size or load
elements an indeterminate number of times.
• The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-
bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address
bits are ignored.
Operation
DEST := SRC1;
BASE_ADDR: base register encoded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;
SCALE: scale factor encoded by SIB:[7:6];
DISP: optional 1, 4 byte displacement;
MASK := SRC3;
VGATHERDPD (VEX.128 version)
MASK[MAXVL-1:128] := 0;
FOR j := 0 to 1
i := j * 64;
IF MASK[63+i] THEN
MASK[i +63:i] := FFFFFFFF_FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +63:i] := 0;
FI;
ENDFOR
FOR j := 0 to 1
k := j * 32;
i := j * 64;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX[k+31:k])*SCALE + DISP;
IF MASK[63+i] THEN
DEST[i +63:i] := FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +63: i] := 0;
ENDFOR
DEST[MAXVL-1:128] := 0;
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VGATHERDPD/VGATHERQPD—Gather Packed Double Precision Floating-Point Values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V
VGATHERQPD (VEX.128 version)
MASK[MAXVL-1:128] := 0;
FOR j := 0 to 1
i := j * 64;
IF MASK[63+i] THEN
MASK[i +63:i] := FFFFFFFF_FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +63:i] := 0;
FI;
ENDFOR
FOR j := 0 to 1
i := j * 64;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;
IF MASK[63+i] THEN
DEST[i +63:i] := FETCH_64BITS(DATA_ADDR); // a fault exits this instruction
FI;
MASK[i +63: i] := 0;
ENDFOR
DEST[MAXVL-1:128] := 0;
VGATHERQPD (VEX.256 version)
MASK[MAXVL-1:256] := 0;
FOR j := 0 to 3
i := j * 64;
IF MASK[63+i] THEN
MASK[i +63:i] := FFFFFFFF_FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +63:i] := 0;
FI;
ENDFOR
FOR j := 0 to 3
i := j * 64;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;
IF MASK[63+i] THEN
DEST[i +63:i] := FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +63: i] := 0;
ENDFOR
DEST[MAXVL-1:256] := 0;
VGATHERDPD (VEX.256 version)
MASK[MAXVL-1:256] := 0;
FOR j := 0 to 3
i := j * 64;
IF MASK[63+i] THEN
MASK[i +63:i] := FFFFFFFF_FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +63:i] := 0;
FI;
ENDFOR
FOR j := 0 to 3
k := j * 32;
i := j * 64;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[k+31:k])*SCALE + DISP;
VGATHERDPD/VGATHERQPD—Gather Packed Double Precision Floating-Point Values Using Signed Dword/Qword Indices
Vol. 2C
5-337
INSTRUCTION SET REFERENCE, V
IF MASK[63+i] THEN
DEST[i +63:i] := FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +63:i] := 0;
ENDFOR
DEST[MAXVL-1:256] := 0;
Intel C/C++ Compiler Intrinsic Equivalent
VGATHERDPD: __m128d _mm_i32gather_pd (double const * base, __m128i index, const int scale);
VGATHERDPD: __m128d _mm_mask_i32gather_pd (__m128d src, double const * base, __m128i index, __m128d mask, const int
scale);
VGATHERDPD: __m256d _mm256_i32gather_pd (double const * base, __m128i index, const int scale);
VGATHERDPD: __m256d _mm256_mask_i32gather_pd (__m256d src, double const * base, __m128i index, __m256d mask, const int
scale);
VGATHERQPD: __m128d _mm_i64gather_pd (double const * base, __m128i index, const int scale);
VGATHERQPD: __m128d _mm_mask_i64gather_pd (__m128d src, double const * base, __m128i index, __m128d mask, const int
scale);
VGATHERQPD: __m256d _mm256_i64gather_pd (double const * base, __m256i index, const int scale);
VGATHERQPD: __m256d _mm256_mask_i64gather_pd (__m256d src, double const * base, __m256i index, __m256d mask, const int
scale);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-27, “Type 12 Class Exception Conditions.”
5-338
Vol. 2C
VGATHERDPD/VGATHERQPD—Gather Packed Double Precision Floating-Point Values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V
VGATHERDPS/VGATHERQPS—Gather Packed Single Precision Floating-Point Values Using
Signed Dword/Qword Indices
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
-bit
Feature
Mode
Flag
VEX.128.66.0F38.W0 92 /r
A
V/V
AVX2
Using dword indices specified in vm32x, gather single-preci-
VGATHERDPS xmm1, vm32x, xmm2
sion floating-point values from memory conditioned on mask
specified by xmm2. Conditionally gathered elements are
merged into xmm1.
VEX.128.66.0F38.W0 93 /r
A
V/V
AVX2
Using qword indices specified in vm64x, gather single-preci-
VGATHERQPS xmm1, vm64x, xmm2
sion floating-point values from memory conditioned on mask
specified by xmm2. Conditionally gathered elements are
merged into xmm1.
VEX.256.66.0F38.W0 92 /r
A
V/V
AVX2
Using dword indices specified in vm32y, gather single-preci-
VGATHERDPS ymm1, vm32y, ymm2
sion floating-point values from memory conditioned on mask
specified by ymm2. Conditionally gathered elements are
merged into ymm1.
VEX.256.66.0F38.W0 93 /r
A
V/V
AVX2
Using qword indices specified in vm64y, gather single-preci-
VGATHERQPS xmm1, vm64y, xmm2
sion floating-point values from memory conditioned on mask
specified by xmm2. Conditionally gathered elements are
merged into xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
A
ModRM:reg (r,w)
BaseReg (R): VSIB:base,
VEX.vvvv (r, w)
N/A
VectorReg(R): VSIB:index
Description
The instruction conditionally loads up to 4 or 8 single-precision floating-point values from memory addresses spec-
ified by the memory operand (the second operand) and using dword indices. The memory operand uses the VSIB
form of the SIB byte to specify a general purpose register operand as the common base, a vector register for an
array of indices relative to the base and a constant scale factor.
The mask operand (the third operand) specifies the conditional load operation from each memory address and the
corresponding update of each data element of the destination operand (the first operand). Conditionality is speci-
fied by the most significant bit of each data element of the mask register. If an element’s mask bit is not set, the
corresponding element of the destination register is left unchanged. The width of data element in the destination
register and mask register are identical. The entire mask register will be set to zero by this instruction unless the
instruction causes an exception.
Using qword indices, the instruction conditionally loads up to 2 or 4 single-precision floating-point values from the
VSIB addressing memory operand, and updates the lower half of the destination register. The upper 128 or 256 bits
of the destination register are zero’ed with qword indices.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask operand are partially updated; those elements that have been gathered are placed into the
destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gath-
ered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
If the data size and index size are different, part of the destination register and part of the mask register do not
correspond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both
of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception
before gathering any elements.
VEX.128 version: For dword indices, the instruction will gather four single-precision floating-point values. For
qword indices, the instruction will gather two values and zero the upper 64 bits of the destination.
VGATHERDPS/VGATHERQPS—Gather Packed Single Precision Floating-Point Values Using Signed Dword/Qword Indices
Vol. 2C
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INSTRUCTION SET REFERENCE, V
VEX.256 version: For dword indices, the instruction will gather eight single-precision floating-point values. For
qword indices, the instruction will gather four values and zero the upper 128 bits of the destination.
Note that:
• If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault.
• The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
64 memory-ordering model.
• Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer
to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the
conventional order.
• Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
• This instruction does not perform AC checks, and so will never deliver an AC fault.
• This instruction will cause a #UD if the address size attribute is 16-bit.
• This instruction will cause a #UD if the memory operand is encoded without the SIB byte.
• This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does
is implementation specific, and some implementations may use loads larger than the data element size or load
elements an indeterminate number of times.
• The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-
bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address
bits are ignored.
Operation
DEST := SRC1;
BASE_ADDR: base register encoded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;
SCALE: scale factor encoded by SIB:[7:6];
DISP: optional 1, 4 byte displacement;
MASK := SRC3;
VGATHERDPS (VEX.128 version)
MASK[MAXVL-1:128] := 0;
FOR j := 0 to 3
i := j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] := FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] := 0;
FI;
ENDFOR
FOR j := 0 to 3
i := j * 32;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX[i+31:i])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] := FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] := 0;
ENDFOR
DEST[MAXVL-1:128] := 0;
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VGATHERDPS/VGATHERQPS—Gather Packed Single Precision Floating-Point Values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V
VGATHERQPS (VEX.128 version)
MASK[MAXVL-1:64] := 0;
FOR j := 0 to 3
i := j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] := FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] := 0;
FI;
ENDFOR
FOR j := 0 to 1
k := j * 64;
i := j * 32;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] := FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] := 0;
ENDFOR
DEST[MAXVL-1:64] := 0;
VGATHERDPS (VEX.256 version)
MASK[MAXVL-1:256] := 0;
FOR j := 0 to 7
i := j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] := FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] := 0;
FI;
ENDFOR
FOR j := 0 to 7
i := j * 32;
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[i+31:i])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] := FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] := 0;
ENDFOR
DEST[MAXVL-1:256] := 0;
VGATHERQPS (VEX.256 version)
MASK[MAXVL-1:128] := 0;
FOR j := 0 to 7
i := j * 32;
IF MASK[31+i] THEN
MASK[i +31:i] := FFFFFFFFH; // extend from most significant bit
ELSE
MASK[i +31:i] := 0;
FI;
ENDFOR
FOR j := 0 to 3
k := j * 64;
i := j * 32;
VGATHERDPS/VGATHERQPS—Gather Packed Single Precision Floating-Point Values Using Signed Dword/Qword Indices
Vol. 2C
5-341
INSTRUCTION SET REFERENCE, V
DATA_ADDR := BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
IF MASK[31+i] THEN
DEST[i +31:i] := FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
FI;
MASK[i +31:i] := 0;
ENDFOR
DEST[MAXVL-1:128] := 0;
Intel C/C++ Compiler Intrinsic Equivalent
VGATHERDPS:
__m128 _mm_i32gather_ps (float const * base, __m128i index, const int scale);
VGATHERDPS:
__m128 _mm_mask_i32gather_ps (__m128 src, float const * base, __m128i index, __m128 mask, const int scale);
VGATHERDPS:
__m256 _mm256_i32gather_ps (float const * base, __m256i index, const int scale);
VGATHERDPS:
__m256 _mm256_mask_i32gather_ps (__m256 src, float const * base, __m256i index, __m256 mask, const int
scale);
VGATHERQPS:
__m128 _mm_i64gather_ps (float const * base, __m128i index, const int scale);
VGATHERQPS:
__m128 _mm_mask_i64gather_ps (__m128 src, float const * base, __m128i index, __m128 mask, const int scale);
VGATHERQPS:
__m128 _mm256_i64gather_ps (float const * base, __m256i index, const int scale);
VGATHERQPS:
__m128 _mm256_mask_i64gather_ps (__m128 src, float const * base, __m256i index, __m128 mask, const int
scale);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-27, “Type 12 Class Exception Conditions.”
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VGATHERDPS/VGATHERQPS—Gather Packed Single Precision Floating-Point Values Using Signed Dword/Qword Indices
INSTRUCTION SET REFERENCE, V
VGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with Signed Dword Indices
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W0 92 /vsib
A
V/V
AVX512VL
Using signed dword indices, gather single-precision floating-
VGATHERDPS xmm1 {k1}, vm32x
AVX512F
point values from memory using k1 as completion mask.
EVEX.256.66.0F38.W0 92 /vsib
A
V/V
AVX512VL
Using signed dword indices, gather single-precision floating-
VGATHERDPS ymm1 {k1}, vm32y
AVX512F
point values from memory using k1 as completion mask.
EVEX.512.66.0F38.W0 92 /vsib
A
V/V
AVX512F
Using signed dword indices, gather single-precision floating-
VGATHERDPS zmm1 {k1}, vm32z
point values from memory using k1 as completion mask.
EVEX.128.66.0F38.W1 92 /vsib
A
V/V
AVX512VL
Using signed dword indices, gather float64 vector into
VGATHERDPD xmm1 {k1},
AVX512F
float64 vector xmm1 using k1 as completion mask.
vm32x
EVEX.256.66.0F38.W1 92 /vsib
A
V/V
AVX512VL
Using signed dword indices, gather float64 vector into
VGATHERDPD ymm1 {k1},
AVX512F
float64 vector ymm1 using k1 as completion mask.
vm32x
EVEX.512.66.0F38.W1 92 /vsib
A
V/V
AVX512F
Using signed dword indices, gather float64 vector into
VGATHERDPD zmm1 {k1}, vm32y
float64 vector zmm1 using k1 as completion mask.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
BaseReg (R): VSIB:base,
A
Tuple1 Scalar
ModRM:reg (w)
N/A
N/A
VectorReg(R): VSIB:index
Description
A set of single-precision/double precision faulting-point memory locations pointed by base address BASE_ADDR
and index vector V_INDEX with scale SCALE are gathered. The result is written into a vector register. The elements
are specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements will only
be loaded if their corresponding mask bit is one. If an element’s mask bit is not set, the corresponding element of
the destination register is left unchanged. The entire mask register will be set to zero by this instruction unless it
triggers an exception.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the right most one with its mask bit set). When this happens, the destination
register and the mask register (k1) are partially updated; those elements that have been gathered are placed into
the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already
gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruc-
tion breakpoint is not re-triggered when the instruction is continued.
If the data element size is less than the index element size, the higher part of the destination register and the mask
register do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may
update these unused elements to one or both of those registers even if the instruction triggers an exception, and
even if the instruction triggers the exception before gathering any elements.
Note that:
• The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
64 memory-ordering model.
• Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements
closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
in the conventional order.
• Elements may be gathered in any order, but faults must be delivered in a right-to left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
VGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with Signed Dword Indices
Vol. 2C
5-343
INSTRUCTION SET REFERENCE, V
• This instruction does not perform AC checks, and so will never deliver an AC fault.
• Not valid with 16-bit effective addresses. Will deliver a #UD fault.
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are
ignored.
The instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction
will #UD fault if the k0 mask register is specified.
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a vector register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1 or 4 byte displacement
VGATHERDPS (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j]
THEN DEST[i+31:i] :=
MEM[BASE_ADDR +
SignExtend(VINDEX[i+31:i]) * SCALE + DISP]
k1[j] := 0
ELSE *DEST[i+31:i] := remains unchanged*
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
DEST[MAXVL-1:VL] := 0
VGATHERDPD (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
k := j * 32
IF k1[j]
THEN DEST[i+63:i] := MEM[BASE_ADDR +
SignExtend(VINDEX[k+31:k]) * SCALE + DISP]
k1[j] := 0
ELSE *DEST[i+63:i] := remains unchanged*
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
DEST[MAXVL-1:VL] := 0
5-344
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VGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with Signed Dword Indices
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VGATHERDPD __m512d _mm512_i32gather_pd( __m256i vdx, void * base, int scale);
VGATHERDPD __m512d _mm512_mask_i32gather_pd(__m512d s, __mmask8 k, __m256i vdx, void * base, int scale);
VGATHERDPD __m256d _mm256_mmask_i32gather_pd(__m256d s, __mmask8 k, __m128i vdx, void * base, int scale);
VGATHERDPD __m128d _mm_mmask_i32gather_pd(__m128d s, __mmask8 k, __m128i vdx, void * base, int scale);
VGATHERDPS __m512 _mm512_i32gather_ps( __m512i vdx, void * base, int scale);
VGATHERDPS __m512 _mm512_mask_i32gather_ps(__m512 s, __mmask16 k, __m512i vdx, void * base, int scale);
VGATHERDPS __m256 _mm256_mmask_i32gather_ps(__m256 s, __mmask8 k, __m256i vdx, void * base, int scale);
GATHERDPS __m128 _mm_mmask_i32gather_ps(__m128 s, __mmask8 k, __m128i vdx, void * base, int scale);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-61, “Type E12 Class Exception Conditions.”
VGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with Signed Dword Indices
Vol. 2C
5-345
INSTRUCTION SET REFERENCE, V
VGATHERQPS/VGATHERQPD—Gather Packed Single, Packed Double with Signed Qword Indices
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W0 93 /vsib
A
V/V
AVX512VL
Using signed qword indices, gather single-precision
VGATHERQPS xmm1 {k1}, vm64x
AVX512F
floating-point values from memory using k1 as completion
mask.
EVEX.256.66.0F38.W0 93 /vsib
A
V/V
AVX512VL
Using signed qword indices, gather single-precision
VGATHERQPS xmm1 {k1}, vm64y
AVX512F
floating-point values from memory using k1 as completion
mask.
EVEX.512.66.0F38.W0 93 /vsib
A
V/V
AVX512F
Using signed qword indices, gather single-precision
VGATHERQPS ymm1 {k1}, vm64z
floating-point values from memory using k1 as completion
mask.
EVEX.128.66.0F38.W1 93 /vsib
A
V/V
AVX512VL
Using signed qword indices, gather float64 vector into
VGATHERQPD xmm1 {k1}, vm64x
AVX512F
float64 vector xmm1 using k1 as completion mask.
EVEX.256.66.0F38.W1 93 /vsib
A
V/V
AVX512VL
Using signed qword indices, gather float64 vector into
VGATHERQPD ymm1 {k1}, vm64y
AVX512F
float64 vector ymm1 using k1 as completion mask.
EVEX.512.66.0F38.W1 93 /vsib
A
V/V
AVX512F
Using signed qword indices, gather float64 vector into
VGATHERQPD zmm1 {k1}, vm64z
float64 vector zmm1 using k1 as completion mask.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
BaseReg (R): VSIB:base,
A
Tuple1 Scalar
ModRM:reg (w)
N/A
N/A
VectorReg(R): VSIB:index
Description
A set of 8 single-precision/double precision faulting-point memory locations pointed by base address BASE_ADDR
and index vector V_INDEX with scale SCALE are gathered. The result is written into vector a register. The elements
are specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements will only be
loaded if their corresponding mask bit is one. If an element’s mask bit is not set, the corresponding element of the
destination register is left unchanged. The entire mask register will be set to zero by this instruction unless it trig-
gers an exception.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask register (k1) are partially updated; those elements that have been gathered are placed into
the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already
gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruc-
tion breakpoint is not re-triggered when the instruction is continued.
If the data element size is less than the index element size, the higher part of the destination register and the mask
register do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may
update these unused elements to one or both of those registers even if the instruction triggers an exception, and
even if the instruction triggers the exception before gathering any elements.
Note that:
• The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
64 memory-ordering model.
• Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements
closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
in the conventional order.
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VGATHERQPS/VGATHERQPD—Gather Packed Single, Packed Double with Signed Qword Indices
INSTRUCTION SET REFERENCE, V
• Elements may be gathered in any order, but faults must be delivered in a right-to left order; thus, elements to
the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
instruction is repeatable - given the same input values and architectural state, the same set of elements to the
left of the faulting one will be gathered.
• This instruction does not perform AC checks, and so will never deliver an AC fault.
• Not valid with 16-bit effective addresses. Will deliver a #UD fault.
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are
ignored.
The instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction
will #UD fault if the k0 mask register is specified.
Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a ZMM register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1 or 4 byte displacement
VGATHERQPS (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 32
k := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] :=
MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP]
k1[j] := 0
ELSE *DEST[i+31:i] := remains unchanged*
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
DEST[MAXVL-1:VL/2] := 0
VGATHERQPD (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] := MEM[BASE_ADDR + (VINDEX[i+63:i]) * SCALE + DISP]
k1[j] := 0
ELSE *DEST[i+63:i] := remains unchanged*
FI;
ENDFOR
k1[MAX_KL-1:KL] := 0
DEST[MAXVL-1:VL] := 0
VGATHERQPS/VGATHERQPD—Gather Packed Single, Packed Double with Signed Qword Indices
Vol. 2C
5-347
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VGATHERQPD __m512d _mm512_i64gather_pd( __m512i vdx, void * base, int scale);
VGATHERQPD __m512d _mm512_mask_i64gather_pd(__m512d s, __mmask8 k, __m512i vdx, void * base, int scale);
VGATHERQPD __m256d _mm256_mask_i64gather_pd(__m256d s, __mmask8 k, __m256i vdx, void * base, int scale);
VGATHERQPD __m128d _mm_mask_i64gather_pd(__m128d s, __mmask8 k, __m128i vdx, void * base, int scale);
VGATHERQPS __m256 _mm512_i64gather_ps( __m512i vdx, void * base, int scale);
VGATHERQPS __m256 _mm512_mask_i64gather_ps(__m256 s, __mmask16 k, __m512i vdx, void * base, int scale);
VGATHERQPS __m128 _mm256_mask_i64gather_ps(__m128 s, __mmask8 k, __m256i vdx, void * base, int scale);
VGATHERQPS __m128 _mm_mask_i64gather_ps(__m128 s, __mmask8 k, __m128i vdx, void * base, int scale);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-61, “Type E12 Class Exception Conditions.”
5-348
Vol. 2C
VGATHERQPS/VGATHERQPD—Gather Packed Single, Packed Double with Signed Qword Indices
INSTRUCTION SET REFERENCE, V
VGETEXPPD—Convert Exponents of Packed Double Precision Floating-Point Values to Double
Precision Floating-Point Values
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W1 42 /r
A
V/V
AVX512VL
Convert the exponent of packed double precision floating-point
VGETEXPPD xmm1 {k1}{z},
AVX512F
values in the source operand to double precision floating-point
xmm2/m128/m64bcst
results representing unbiased integer exponents and stores the
results in the destination register.
EVEX.256.66.0F38.W1 42 /r
A
V/V
AVX512VL
Convert the exponent of packed double precision floating-point
VGETEXPPD ymm1 {k1}{z},
AVX512F
values in the source operand to double precision floating-point
ymm2/m256/m64bcst
results representing unbiased integer exponents and stores the
results in the destination register.
EVEX.512.66.0F38.W1 42 /r
A
V/V
AVX512F
Convert the exponent of packed double precision floating-point
VGETEXPPD zmm1 {k1}{z},
values in the source operand to double precision floating-point
zmm2/m512/m64bcst{sae}
results representing unbiased integer exponents and stores the
results in the destination under writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Extracts the biased exponents from the normalized double precision floating-point representation of each qword
data element of the source operand (the second operand) as unbiased signed integer value, or convert the
denormal representation of input data to unbiased negative integer values. Each integer value of the unbiased
exponent is converted to double precision floating-point value and written to the corresponding qword elements of
the destination operand (the first operand) as double precision floating-point numbers.
The destination operand is a ZMM/YMM/XMM register and updated under the writemask. The source operand can
be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from
a 64-bit memory location.
EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Each GETEXP operation converts the exponent value into a floating-point number (permitting input value in
denormal representation). Special cases of input values are listed in Table 5-5.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for the greatest integer not exceeding real number x.
Table 5-5. VGETEXPPD/SD Special Cases
Input Operand
Result
Comments
src1 = NaN
QNaN(src1)
If (SRC = SNaN) then #IE
0 < |src1| < INF
floor(log2(|src1|))
If (SRC = denormal) then #DE
| src1| = +INF
+INF
| src1| = 0
-INF
VGETEXPPD—Convert Exponents of Packed Double Precision Floating-Point Values to Double Precision Floating-Point Values
Vol. 2C
5-349
INSTRUCTION SET REFERENCE, V
Operation
NormalizeExpTinyDPFP(SRC[63:0])
{
// Jbit is the hidden integral bit of a floating-point number. In case of denormal number it has the value of ZERO.
Src.Jbit := 0;
Dst.exp := 1;
Dst.fraction := SRC[51:0];
WHILE(Src.Jbit = 0)
{
Src.Jbit := Dst.fraction[51];
// Get the fraction MSB
Dst.fraction := Dst.fraction << 1 ;
// One bit shift left
Dst.exp-- ;
// Decrement the exponent
}
Dst.fraction := 0;
// zero out fraction bits
Dst.sign := 1;
// Return negative sign
TMP[63:0] := MXCSR.DAZ? 0 : (Dst.sign << 63) OR (Dst.exp << 52) OR (Dst.fraction) ;
Return (TMP[63:0]);
}
ConvertExpDPFP(SRC[63:0])
{
Src.sign := 0;
// Zero out sign bit
Src.exp := SRC[62:52];
Src.fraction := SRC[51:0];
// Check for NaN
IF (SRC = NaN)
{
IF ( SRC = SNAN ) SET IE;
Return QNAN(SRC);
}
// Check for +INF
IF (Src = +INF) RETURN (Src);
// check if zero operand
IF ((Src.exp = 0) AND ((Src.fraction = 0) OR (MXCSR.DAZ = 1))) Return (-INF);
}
ELSE
// check if denormal operand (notice that MXCSR.DAZ = 0)
{
IF ((Src.exp = 0) AND (Src.fraction != 0))
{
TMP[63:0] := NormalizeExpTinyDPFP(SRC[63:0]) ;
// Get Normalized Exponent
Set #DE
}
ELSE
// exponent value is correct
{
TMP[63:0] := (Src.sign << 63) OR (Src.exp << 52) OR (Src.fraction) ;
}
TMP := SAR(TMP, 52) ;
// Shift Arithmetic Right
TMP := TMP - 1023;
// Subtract Bias
Return CvtI2D(TMP);
// Convert INT to double precision floating-point number
}
}
VGETEXPPD—Convert Exponents of Packed Double Precision Floating-Point Values to Double Precision Floating-Point Values
5-350
Vol. 2C
INSTRUCTION SET REFERENCE, V
VGETEXPPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN
DEST[i+63:i] :=
ConvertExpDPFP(SRC[63:0])
ELSE
DEST[i+63:i] :=
ConvertExpDPFP(SRC[i+63:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPPD __m512d _mm512_getexp_pd(__m512d a);
VGETEXPPD __m512d _mm512_mask_getexp_pd(__m512d s, __mmask8 k, __m512d a);
VGETEXPPD __m512d _mm512_maskz_getexp_pd( __mmask8 k, __m512d a);
VGETEXPPD __m512d _mm512_getexp_round_pd(__m512d a, int sae);
VGETEXPPD __m512d _mm512_mask_getexp_round_pd(__m512d s, __mmask8 k, __m512d a, int sae);
VGETEXPPD __m512d _mm512_maskz_getexp_round_pd( __mmask8 k, __m512d a, int sae);
VGETEXPPD __m256d _mm256_getexp_pd(__m256d a);
VGETEXPPD __m256d _mm256_mask_getexp_pd(__m256d s, __mmask8 k, __m256d a);
VGETEXPPD __m256d _mm256_maskz_getexp_pd( __mmask8 k, __m256d a);
VGETEXPPD __m128d _mm_getexp_pd(__m128d a);
VGETEXPPD __m128d _mm_mask_getexp_pd(__m128d s, __mmask8 k, __m128d a);
VGETEXPPD __m128d _mm_maskz_getexp_pd( __mmask8 k, __m128d a);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
See Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VGETEXPPD—Convert Exponents of Packed Double Precision Floating-Point Values to Double Precision Floating-Point Values
Vol. 2C
5-351
INSTRUCTION SET REFERENCE, V
VGETEXPPH—Convert Exponents of Packed FP16 Values to FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.66.MAP6.W0 42 /r
A
V/V
AVX512-FP16
Convert the exponent of FP16 values in the source
VGETEXPPH xmm1{k1}{z}, xmm2/
AVX512VL
operand to FP16 results representing unbiased
m128/m16bcst
integer exponents and stores the results in the
destination register subject to writemask k1.
EVEX.256.66.MAP6.W0 42 /r
A
V/V
AVX512-FP16
Convert the exponent of FP16 values in the source
VGETEXPPH ymm1{k1}{z}, ymm2/
AVX512VL
operand to FP16 results representing unbiased
m256/m16bcst
integer exponents and stores the results in the
destination register subject to writemask k1.
EVEX.512.66.MAP6.W0 42 /r
A
V/V
AVX512-FP16
Convert the exponent of FP16 values in the source
VGETEXPPH zmm1{k1}{z}, zmm2/
operand to FP16 results representing unbiased
m512/m16bcst {sae}
integer exponents and stores the results in the
destination register subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
This instruction extracts the biased exponents from the normalized FP16 representation of each word element of the
source operand (the second operand) as unbiased signed integer value, or convert the denormal representation of
input data to unbiased negative integer values. Each integer value of the unbiased exponent is converted to an
FP16 value and written to the corresponding word elements of the destination operand (the first operand) as FP16
numbers.
The destination elements are updated according to the writemask.
Each GETEXP operation converts the exponent value into a floating-point number (permitting input value in
denormal representation). Special cases of input values are listed in Table 5-5.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for maximal integer not exceeding real number x.
Software usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation
and GETMANT operation (see VGETMANTPH). Thus, the VGETEXPPH instruction does not require software to
handle SIMD floating-point exceptions.
Table 5-6. VGETEXPPH/VGETEXPSH Special Cases
Input Operand
Result
Comments
src1 = NaN
QNaN(src1)
If (SRC = SNaN), then #IE.
0 < |src1| < INF
floor(log2(|src1|))
If (SRC = denormal), then #DE.
| src1| = +INF
+INF
| src1| = 0
-INF
5-352
Vol. 2C
VGETEXPPH—Convert Exponents of Packed FP16 Values to FP16 Values
INSTRUCTION SET REFERENCE, V
Operation
def normalize_exponent_tiny_fp16(src):
jbit := 0
// src & dst are FP16 numbers with sign(1b), exp(5b) and fraction (10b) fields
dst.exp := 1
// write bits 14:10
dst.fraction := src.fraction // copy bits 9:0
while jbit == 0:
jbit := dst.fraction[9]
// msb of the fraction
dst.fraction := dst.fraction << 1
dst.exp := dst.exp - 1
dst.fraction := 0
return dst
def getexp_fp16(src):
src.sign := 0
// make positive
exponent_all_ones := (src[14:10] == 0x1F)
exponent_all_zeros := (src[14:10] == 0)
mantissa_all_zeros := (src[9:0] == 0)
zero := exponent_all_zeros and mantissa_all_zeros
signaling_bit := src[9]
nan := exponent_all_ones and not(mantissa_all_zeros)
snan := nan and not(signaling_bit)
qnan := nan and signaling_bit
positive_infinity := not(negative) and exponent_all_ones and mantissa_all_zeros
denormal := exponent_all_zeros and not(mantissa_all_zeros)
if nan:
if snan:
MXCSR.IE := 1
return qnan(src)
// convert snan to a qnan
if positive_infinity:
return src
if zero:
return -INF
if denormal:
tmp := normalize_exponent_tiny_fp16(src)
MXCSR.DE := 1
else:
tmp := src
tmp := SAR(tmp, 10)
// shift arithmetic right
tmp := tmp - 15
// subtract bias
return convert_integer_to_fp16(tmp)
VGETEXPPH—Convert Exponents of Packed FP16 Values to FP16 Values
Vol. 2C
5-353
INSTRUCTION SET REFERENCE, V
VGETEXPPH dest{k1}, src
VL = 128, 256 or 512
KL := VL/16
FOR i := 0 to KL-1:
IF k1[i] or *no writemask*:
IF SRC is memory and (EVEX.b = 1):
tsrc := src.fp16[0]
ELSE:
tsrc := src.fp16[i]
DEST.fp16[i] := getexp_fp16(tsrc)
ELSE IF *zeroing*:
DEST.fp16[i] := 0
//else DEST.fp16[i] remains unchanged
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPPH __m128h _mm_getexp_ph (__m128h a);
VGETEXPPH __m128h _mm_mask_getexp_ph (__m128h src, __mmask8 k, __m128h a);
VGETEXPPH __m128h _mm_maskz_getexp_ph (__mmask8 k, __m128h a);
VGETEXPPH __m256h _mm256_getexp_ph (__m256h a);
VGETEXPPH __m256h _mm256_mask_getexp_ph (__m256h src, __mmask16 k, __m256h a);
VGETEXPPH __m256h _mm256_maskz_getexp_ph (__mmask16 k, __m256h a);
VGETEXPPH __m512h _mm512_getexp_ph (__m512h a);
VGETEXPPH __m512h _mm512_mask_getexp_ph (__m512h src, __mmask32 k, __m512h a);
VGETEXPPH __m512h _mm512_maskz_getexp_ph (__mmask32 k, __m512h a);
VGETEXPPH __m512h _mm512_getexp_round_ph (__m512h a, const int sae);
VGETEXPPH __m512h _mm512_mask_getexp_round_ph (__m512h src, __mmask32 k, __m512h a, const int sae);
VGETEXPPH __m512h _mm512_maskz_getexp_round_ph (__mmask32 k, __m512h a, const int sae);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
5-354
Vol. 2C
VGETEXPPH—Convert Exponents of Packed FP16 Values to FP16 Values
INSTRUCTION SET REFERENCE, V
VGETEXPPS—Convert Exponents of Packed Single Precision Floating-Point Values to Single
Precision Floating-Point Values
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F38.W0 42 /r
A
V/V
AVX512VL
Convert the exponent of packed single-precision floating-point
VGETEXPPS xmm1 {k1}{z},
AVX512F
values in the source operand to single-precision floating-point
xmm2/m128/m32bcst
results representing unbiased integer exponents and stores the
results in the destination register.
EVEX.256.66.0F38.W0 42 /r
A
V/V
AVX512VL
Convert the exponent of packed single-precision floating-point
VGETEXPPS ymm1 {k1}{z},
AVX512F
values in the source operand to single-precision floating-point
ymm2/m256/m32bcst
results representing unbiased integer exponents and stores the
results in the destination register.
EVEX.512.66.0F38.W0 42 /r
A
V/V
AVX512F
Convert the exponent of packed single-precision floating-point
VGETEXPPS zmm1 {k1}{z},
values in the source operand to single-precision floating-point
zmm2/m512/m32bcst{sae}
results representing unbiased integer exponents and stores the
results in the destination register.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Extracts the biased exponents from the normalized single-precision floating-point representation of each dword
element of the source operand (the second operand) as unbiased signed integer value, or convert the denormal
representation of input data to unbiased negative integer values. Each integer value of the unbiased exponent is
converted to single-precision floating-point value and written to the corresponding dword elements of the destina-
tion operand (the first operand) as single-precision floating-point numbers.
The destination operand is a ZMM/YMM/XMM register and updated under the writemask. The source operand can
be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from
a 32-bit memory location.
EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Each GETEXP operation converts the exponent value into a floating-point number (permitting input value in
denormal representation). Special cases of input values are listed in Table 5-7.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for maximal integer not exceeding real number x.
Software usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation
and GETMANT operation (see VGETMANTPD). Thus VGETEXPxx instruction do not require software to handle SIMD
floating-point exceptions.
Table 5-7. VGETEXPPS/SS Special Cases
Input Operand
Result
Comments
src1 = NaN
QNaN(src1)
If (SRC = SNaN) then #IE
0 < |src1| < INF
floor(log2(|src1|))
If (SRC = denormal) then #DE
| src1| = +INF
+INF
| src1| = 0
-INF
VGETEXPPS—Convert Exponents of Packed Single Precision Floating-Point Values to Single Precision Floating-Point Values
Vol. 2C
5-355
INSTRUCTION SET REFERENCE, V
Figure 5-14 illustrates the VGETEXPPS functionality on input values with normalized representation.
31
30 29 28 27 26 25 24 23
22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
s
exp
Fraction
Src = 2^1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SAR Src, 23 = 080h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
-Bias
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
Tmp - Bias = 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Cvt_PI2PS(01h) = 2^0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-14. VGETEXPPS Functionality On Normal Input values
Operation
NormalizeExpTinySPFP(SRC[31:0])
{
// Jbit is the hidden integral bit of a floating-point number. In case of denormal number it has the value of ZERO.
Src.Jbit := 0;
Dst.exp := 1;
Dst.fraction := SRC[22:0];
WHILE(Src.Jbit = 0)
{
Src.Jbit := Dst.fraction[22];
// Get the fraction MSB
Dst.fraction := Dst.fraction << 1 ;
// One bit shift left
Dst.exp-- ;
// Decrement the exponent
}
Dst.fraction := 0;
// zero out fraction bits
Dst.sign := 1;
// Return negative sign
TMP[31:0] := MXCSR.DAZ? 0 : (Dst.sign << 31) OR (Dst.exp << 23) OR (Dst.fraction) ;
Return (TMP[31:0]);
}
ConvertExpSPFP(SRC[31:0])
{
Src.sign := 0;
// Zero out sign bit
Src.exp := SRC[30:23];
Src.fraction := SRC[22:0];
// Check for NaN
IF (SRC = NaN)
{
IF ( SRC = SNAN ) SET IE;
Return QNAN(SRC);
}
// Check for +INF
IF (Src = +INF) RETURN (Src);
// check if zero operand
IF ((Src.exp = 0) AND ((Src.fraction = 0) OR (MXCSR.DAZ = 1))) Return (-INF);
}
ELSE
// check if denormal operand (notice that MXCSR.DAZ = 0)
{
5-356
Vol. 2C
VGETEXPPS—Convert Exponents of Packed Single Precision Floating-Point Values to Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V
IF ((Src.exp = 0) AND (Src.fraction != 0))
{
TMP[31:0] := NormalizeExpTinySPFP(SRC[31:0]) ;
// Get Normalized Exponent
Set #DE
}
ELSE
// exponent value is correct
{
TMP[31:0] := (Src.sign << 31) OR (Src.exp << 23) OR (Src.fraction) ;
}
TMP := SAR(TMP, 23) ;
// Shift Arithmetic Right
TMP := TMP - 127;
// Subtract Bias
Return CvtI2S(TMP);
// Convert INT to single precision floating-point number
}
}
VGETEXPPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC *is memory*)
THEN
DEST[i+31:i] :=
ConvertExpSPFP(SRC[31:0])
ELSE
DEST[i+31:i] :=
ConvertExpSPFP(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VGETEXPPS—Convert Exponents of Packed Single Precision Floating-Point Values to Single Precision Floating-Point Values
Vol. 2C
5-357
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPPS __m512 _mm512_getexp_ps( __m512 a);
VGETEXPPS __m512 _mm512_mask_getexp_ps(__m512 s, __mmask16 k, __m512 a);
VGETEXPPS __m512 _mm512_maskz_getexp_ps( __mmask16 k, __m512 a);
VGETEXPPS __m512 _mm512_getexp_round_ps( __m512 a, int sae);
VGETEXPPS __m512 _mm512_mask_getexp_round_ps(__m512 s, __mmask16 k, __m512 a, int sae);
VGETEXPPS __m512 _mm512_maskz_getexp_round_ps( __mmask16 k, __m512 a, int sae);
VGETEXPPS __m256 _mm256_getexp_ps(__m256 a);
VGETEXPPS __m256 _mm256_mask_getexp_ps(__m256 s, __mmask8 k, __m256 a);
VGETEXPPS __m256 _mm256_maskz_getexp_ps( __mmask8 k, __m256 a);
VGETEXPPS __m128 _mm_getexp_ps(__m128 a);
VGETEXPPS __m128 _mm_mask_getexp_ps(__m128 s, __mmask8 k, __m128 a);
VGETEXPPS __m128 _mm_maskz_getexp_ps( __mmask8 k, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
See Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
5-358
Vol. 2C
VGETEXPPS—Convert Exponents of Packed Single Precision Floating-Point Values to Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, V
VGETEXPSD—Convert Exponents of Scalar Double Precision Floating-Point Value to Double
Precision Floating-Point Value
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.LLIG.66.0F38.W1 43 /r
A
V/V
AVX512F
Convert the biased exponent (bits 62:52) of the low double
VGETEXPSD xmm1 {k1}{z},
precision floating-point value in xmm3/m64 to a double
xmm2, xmm3/m64{sae}
precision floating-point value representing unbiased integer
exponent. Stores the result to the low 64-bit of xmm1 under
the writemask k1 and merge with the other elements of
xmm2.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Extracts the biased exponent from the normalized double precision floating-point representation of the low qword
data element of the source operand (the third operand) as unbiased signed integer value, or convert the denormal
representation of input data to unbiased negative integer values. The integer value of the unbiased exponent is
converted to double precision floating-point value and written to the destination operand (the first operand) as
double precision floating-point numbers. Bits (127:64) of the XMM register destination are copied from corre-
sponding bits in the first source operand.
The destination must be a XMM register, the source operand can be a XMM register or a float64 memory location.
If writemasking is used, the low quadword element of the destination operand is conditionally updated depending
on the value of writemask register k1. If writemasking is not used, the low quadword element of the destination
operand is unconditionally updated.
Each GETEXP operation converts the exponent value into a floating-point number (permitting input value in
denormal representation). Special cases of input values are listed in Table 5-5.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for maximal integer not exceeding real number x.
Operation
// NormalizeExpTinyDPFP(SRC[63:0]) is defined in the Operation section of VGETEXPPD
// ConvertExpDPFP(SRC[63:0]) is defined in the Operation section of VGETEXPPD
VGETEXPSD (EVEX encoded version)
IF k1[0] OR *no writemask*
THEN DEST[63:0] :=
ConvertExpDPFP(SRC2[63:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
DEST[63:0] := 0
FI
FI;
DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0
VGETEXPSD—Convert Exponents of Scalar Double Precision Floating-Point Value to Double Precision Floating-Point Value
Vol. 2C
5-359
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPSD __m128d _mm_getexp_sd( __m128d a, __m128d b);
VGETEXPSD __m128d _mm_mask_getexp_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VGETEXPSD __m128d _mm_maskz_getexp_sd( __mmask8 k, __m128d a, __m128d b);
VGETEXPSD __m128d _mm_getexp_round_sd( __m128d a, __m128d b, int sae);
VGETEXPSD __m128d _mm_mask_getexp_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int sae);
VGETEXPSD __m128d _mm_maskz_getexp_round_sd( __mmask8 k, __m128d a, __m128d b, int sae);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
See Table 2-47, “Type E3 Class Exception Conditions.”
5-360
Vol. 2C
VGETEXPSD—Convert Exponents of Scalar Double Precision Floating-Point Value to Double Precision Floating-Point Value
INSTRUCTION SET REFERENCE, V
VGETEXPSH—Convert Exponents of Scalar FP16 Values to FP16 Values
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.LLIG.66.MAP6.W0 43 /r
A
V/V
AVX512-FP16
Convert the exponent of FP16 values in the low
VGETEXPSH xmm1{k1}{z}, xmm2,
word of the source operand to FP16 results
xmm3/m16 {sae}
representing unbiased integer exponents, and stores
the results in the low word of the destination
register subject to writemask k1. Bits 127:16 of
xmm2 are copied to xmm1[127:16].
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Scalar
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction extracts the biased exponents from the normalized FP16 representation of the low word element of
the source operand (the second operand) as unbiased signed integer value, or convert the denormal representa-
tion of input data to an unbiased negative integer value. The integer value of the unbiased exponent is converted
to an FP16 value and written to the low word element of the destination operand (the first operand) as an FP16
number.
Bits 127:16 of the destination operand are copied from the corresponding bits of the first source operand. Bits
MAXVL-1:128 of the destination operand are zeroed. The low FP16 element of the destination is updated according
to the writemask.
Each GETEXP operation converts the exponent value into a floating-point number (permitting input value in
denormal representation). Special cases of input values are listed in Table 5-6.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for maximal integer not exceeding real number x.
Software usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation
and GETMANT operation (see VGETMANTSH). Thus, the VGETEXPSH instruction does not require software to
handle SIMD floating-point exceptions.
Operation
VGETEXPSH dest{k1}, src1, src2
IF k1[0] or *no writemask*:
DEST.fp16[0] := getexp_fp16(src2.fp16[0]) // see VGETEXPPH
ELSE IF *zeroing*:
DEST.fp16[0] := 0
//else DEST.fp16[0] remains unchanged
DEST[127:16] := src1[127:16]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPSH __m128h _mm_getexp_round_sh (__m128h a, __m128h b, const int sae);
VGETEXPSH __m128h _mm_mask_getexp_round_sh (__m128h src, __mmask8 k, __m128h a, __m128h b, const int sae);
VGETEXPSH __m128h _mm_maskz_getexp_round_sh (__mmask8 k, __m128h a, __m128h b, const int sae);
VGETEXPSH __m128h _mm_getexp_sh (__m128h a, __m128h b);
VGETEXPSH __m128h _mm_mask_getexp_sh (__m128h src, __mmask8 k, __m128h a, __m128h b);
VGETEXPSH __m128h _mm_maskz_getexp_sh (__mmask8 k, __m128h a, __m128h b);
VGETEXPSH—Convert Exponents of Scalar FP16 Values to FP16 Values
Vol. 2C
5-361
INSTRUCTION SET REFERENCE, V
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”
5-362
Vol. 2C
VGETEXPSH—Convert Exponents of Scalar FP16 Values to FP16 Values
INSTRUCTION SET REFERENCE, V
VGETEXPSS—Convert Exponents of Scalar Single Precision Floating-Point Value to Single
Precision Floating-Point Value
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.LLIG.66.0F38.W0 43 /r
A
V/V
AVX512F
Convert the biased exponent (bits 30:23) of the low single-
VGETEXPSS xmm1 {k1}{z}, xmm2,
precision floating-point value in xmm3/m32 to a single-
xmm3/m32{sae}
precision floating-point value representing unbiased integer
exponent. Stores the result to xmm1 under the writemask
k1 and merge with the other elements of xmm2.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Extracts the biased exponent from the normalized single-precision floating-point representation of the low double-
word data element of the source operand (the third operand) as unbiased signed integer value, or convert the
denormal representation of input data to unbiased negative integer values. The integer value of the unbiased expo-
nent is converted to single-precision floating-point value and written to the destination operand (the first operand)
as single-precision floating-point numbers. Bits (127:32) of the XMM register destination are copied from corre-
sponding bits in the first source operand.
The destination must be a XMM register, the source operand can be a XMM register or a float32 memory location.
If writemasking is used, the low doubleword element of the destination operand is conditionally updated depending
on the value of writemask register k1. If writemasking is not used, the low doubleword element of the destination
operand is unconditionally updated.
Each GETEXP operation converts the exponent value into a floating-point number (permitting input value in
denormal representation). Special cases of input values are listed in Table 5-7.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for maximal integer not exceeding real number x.
Software usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation
and GETMANT operation (see VGETMANTPD). Thus VGETEXPxx instruction do not require software to handle SIMD
floating-point exceptions.
Operation
// NormalizeExpTinySPFP(SRC[31:0]) is defined in the Operation section of VGETEXPPS
// ConvertExpSPFP(SRC[31:0]) is defined in the Operation section of VGETEXPPS
VGETEXPSS (EVEX encoded version)
IF k1[0] OR *no writemask*
THEN DEST[31:0] :=
ConvertExpDPFP(SRC2[31:0])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
DEST[31:0]:= 0
FI
FI;
ENDFOR
VGETEXPSS—Convert Exponents of Scalar Single Precision Floating-Point Value to Single Precision Floating-Point Value
Vol. 2C
5-363
INSTRUCTION SET REFERENCE, V
DEST[127:32] := SRC1[127:32]
DEST[MAXVL-1:128] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPSS __m128 _mm_getexp_ss( __m128 a, __m128 b);
VGETEXPSS __m128 _mm_mask_getexp_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);
VGETEXPSS __m128 _mm_maskz_getexp_ss( __mmask8 k, __m128 a, __m128 b);
VGETEXPSS __m128 _mm_getexp_round_ss( __m128 a, __m128 b, int sae);
VGETEXPSS __m128 _mm_mask_getexp_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int sae);
VGETEXPSS __m128 _mm_maskz_getexp_round_ss( __mmask8 k, __m128 a, __m128 b, int sae);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
See Table 2-47, “Type E3 Class Exception Conditions.”
5-364
Vol. 2C
VGETEXPSS—Convert Exponents of Scalar Single Precision Floating-Point Value to Single Precision Floating-Point Value
INSTRUCTION SET REFERENCE, V
VGETMANTPD—Extract Float64 Vector of Normalized Mantissas From Float64 Vector
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F3A.W1 26 /r ib
A
V/V
AVX512VL
Get Normalized Mantissa from float64 vector
VGETMANTPD xmm1 {k1}{z},
AVX512F
xmm2/m128/m64bcst and store the result in xmm1, using
xmm2/m128/m64bcst, imm8
imm8 for sign control and mantissa interval normalization,
under writemask.
EVEX.256.66.0F3A.W1 26 /r ib
A
V/V
AVX512VL
Get Normalized Mantissa from float64 vector
VGETMANTPD ymm1 {k1}{z},
AVX512F
ymm2/m256/m64bcst and store the result in ymm1, using
ymm2/m256/m64bcst, imm8
imm8 for sign control and mantissa interval normalization,
under writemask.
EVEX.512.66.0F3A.W1 26 /r ib
A
V/V
AVX512F
Get Normalized Mantissa from float64 vector
VGETMANTPD zmm1 {k1}{z},
zmm2/m512/m64bcst and store the result in zmm1, using
zmm2/m512/m64bcst{sae},
imm8 for sign control and mantissa interval normalization,
imm8
under writemask.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
imm8
N/A
Description
Convert double precision floating values in the source operand (the second operand) to double precision floating-
point values with the mantissa normalization and sign control specified by the imm8 byte, see Figure 5-15. The
converted results are written to the destination operand (the first operand) using writemask k1. The normalized
mantissa is specified by interv (imm8[1:0]) and the sign control (sc) is specified by bits 3:2 of the immediate byte.
The destination operand is a ZMM/YMM/XMM register updated under the writemask. The source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-
bit memory location.
7
6
5
4
3
2
1
0
imm8
Must Be Zero
Sign Control (SC)
Normaiization Interval
Imm8[1:0] = 00b : Interval is [ 1, 2)
Imm8[3:2] = 00b : sign(SRC)
Imm8[1:0] = 01b : Interval is [1/2, 2)
Imm8[3:2] = 01b : 0
Imm8[1:0] = 10b : Interval is [ 1/2, 1)
Imm8[3] = 1b : qNan_Indefinite if sign(SRC) != 0, regardless of imm8[2].
Imm8[1:0] = 11b : Interval is [3/4, 3/2)
Figure 5-15. Imm8 Controls for VGETMANTPD/SD/PS/SS
For each input double precision floating-point value x, The conversion operation is:
GetMant(x) = ±2k|x.significand|
where:
1 <= |x.significand| < 2
Unbiased exponent k can be either 0 or -1, depending on the interval range defined by interv, the range of the
significand and whether the exponent of the source is even or odd. The sign of the final result is determined by sc
and the source sign. The encoded value of imm8[1:0] and sign control are shown in Figure 5-15.
VGETMANTPD—Extract Float64 Vector of Normalized Mantissas From Float64 Vector
Vol. 2C
5-365
INSTRUCTION SET REFERENCE, V
Each converted double precision floating-point result is encoded according to the sign control, the unbiased expo-
nent k (adding bias) and a mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-8 when dealing with floating-point special numbers.
This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1
are computed and stored into the destination. Elements in zmm1 with the corresponding bit clear in k1 retain their
previous values.
Note: EVEX.vvvv is reserved and must be 1111b; otherwise instructions will #UD.
Table 5-8. GetMant() Special Float Values Behavior
Input
Result
Exceptions / Comments
NaN
QNaN(SRC)
Ignore interv
If (SRC = SNaN) then #IE
+∞
1.0
Ignore interv
+0
1.0
Ignore interv
-0
IF (SC[0]) THEN +1.0
Ignore interv
ELSE -1.0
-∞
IF (SC[1]) THEN {QNaN_Indefinite}
Ignore interv
ELSE {
If (SC[1]) then #IE
IF (SC[0]) THEN +1.0
ELSE -1.0
negative
SC[1] ? QNaN_Indefinite : Getmant(SRC)1
If (SC[1]) then #IE
NOTES:
1. In case SC[1]==0, the sign of Getmant(SRC) is declared according to SC[0].
Operation
def getmant_fp64(src, sign_control, normalization_interval):
bias := 1023
dst.sign := sign_control[0] ? 0 : src.sign
signed_one := sign_control[0] ? +1.0 : -1.0
dst.exp := src.exp
dst.fraction := src.fraction
zero := (dst.exp = 0) and ((dst.fraction = 0) or (MXCSR.DAZ=1))
denormal := (dst.exp = 0) and (dst.fraction != 0) and (MXCSR.DAZ=0)
infinity := (dst.exp = 0x7FF) and (dst.fraction = 0)
nan := (dst.exp = 0x7FF) and (dst.fraction != 0)
src_signaling := src.fraction[51]
snan := nan and (src_signaling = 0)
positive := (src.sign = 0)
negative := (src.sign = 1)
if nan:
if snan:
MXCSR.IE := 1
return qnan(src)
if positive and (zero or infinity):
return 1.0
if negative:
if zero:
return signed_one
if infinity:
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Vol. 2C
VGETMANTPD—Extract Float64 Vector of Normalized Mantissas From Float64 Vector
INSTRUCTION SET REFERENCE, V
if sign_control[1]:
MXCSR.IE := 1
return QNaN_Indefinite
return signed_one
if sign_control[1]:
MXCSR.IE := 1
return QNaN_Indefinite
if denormal:
jbit := 0
dst.exp := bias
while jbit = 0:
jbit := dst.fraction[51]
dst.fraction := dst.fraction << 1
dst.exp : = dst.exp - 1
MXCSR.DE := 1
unbiased_exp := dst.exp - bias
odd_exp := unbiased_exp[0]
signaling_bit := dst.fraction[51]
if normalization_interval = 0b00:
dst.exp := bias
else if normalization_interval = 0b01:
dst.exp := odd_exp ? bias-1 : bias
else if normalization_interval = 0b10:
dst.exp := bias-1
else if normalization_interval = 0b11:
dst.exp := signaling_bit ? bias-1 : bias
return dst
VGETMANTPD (EVEX encoded versions)
VGETMANTPD dest{k1}, src, imm8
VL = 128, 256, or 512
KL := VL / 64
sign_control := imm8[3:2]
normalization_interval := imm8[1:0]
FOR i := 0 to KL-1:
IF k1[i] or *no writemask*:
IF SRC is memory and (EVEX.b = 1):
tsrc := src.double[0]
ELSE:
tsrc := src.double[i]
DEST.double[i] := getmant_fp64(tsrc, sign_control, normalization_interval)
ELSE IF *zeroing*:
DEST.double[i] := 0
//else DEST.double[i] remains unchanged
DEST[MAX_VL-1:VL] := 0
VGETMANTPD—Extract Float64 Vector of Normalized Mantissas From Float64 Vector
Vol. 2C
5-367
INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTPD __m512d _mm512_getmant_pd( __m512d a, enum intv, enum sgn);
VGETMANTPD __m512d _mm512_mask_getmant_pd(__m512d s, __mmask8 k, __m512d a, enum intv, enum sgn);
VGETMANTPD __m512d _mm512_maskz_getmant_pd( __mmask8 k, __m512d a, enum intv, enum sgn);
VGETMANTPD __m512d _mm512_getmant_round_pd( __m512d a, enum intv, enum sgn, int r);
VGETMANTPD __m512d _mm512_mask_getmant_round_pd(__m512d s, __mmask8 k, __m512d a, enum intv, enum sgn, int r);
VGETMANTPD __m512d _mm512_maskz_getmant_round_pd( __mmask8 k, __m512d a, enum intv, enum sgn, int r);
VGETMANTPD __m256d _mm256_getmant_pd( __m256d a, enum intv, enum sgn);
VGETMANTPD __m256d _mm256_mask_getmant_pd(__m256d s, __mmask8 k, __m256d a, enum intv, enum sgn);
VGETMANTPD __m256d _mm256_maskz_getmant_pd( __mmask8 k, __m256d a, enum intv, enum sgn);
VGETMANTPD __m128d _mm_getmant_pd( __m128d a, enum intv, enum sgn);
VGETMANTPD __m128d _mm_mask_getmant_pd(__m128d s, __mmask8 k, __m128d a, enum intv, enum sgn);
VGETMANTPD __m128d _mm_maskz_getmant_pd( __mmask8 k, __m128d a, enum intv, enum sgn);
SIMD Floating-Point Exceptions
Denormal, Invalid
Other Exceptions
See Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
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Vol. 2C
VGETMANTPD—Extract Float64 Vector of Normalized Mantissas From Float64 Vector
INSTRUCTION SET REFERENCE, V
VGETMANTPH—Extract FP16 Vector of Normalized Mantissas from FP16 Vector
Opcode/
Op/
64/32
CPUID Feature
Description
Instruction
En
bit Mode
Flag
Support
EVEX.128.NP.0F3A.W0 26 /r /ib
A
V/V
AVX512-FP16
Get normalized mantissa from FP16 vector
VGETMANTPH xmm1{k1}{z}, xmm2/
AVX512VL
xmm2/m128/m16bcst and store the result in
m128/m16bcst, imm8
xmm1, using imm8 for sign control and mantissa
interval normalization, subject to writemask k1.
EVEX.256.NP.0F3A.W0 26 /r /ib
A
V/V
AVX512-FP16
Get normalized mantissa from FP16 vector
VGETMANTPH ymm1{k1}{z}, ymm2/
AVX512VL
ymm2/m256/m16bcst and store the result in
m256/m16bcst, imm8
ymm1, using imm8 for sign control and mantissa
interval normalization, subject to writemask k1.
EVEX.512.NP.0F3A.W0 26 /r /ib
A
V/V
AVX512-FP16
Get normalized mantissa from FP16 vector
VGETMANTPH zmm1{k1}{z}, zmm2/
zmm2/m512/m16bcst and store the result in
m512/m16bcst {sae}, imm8
zmm1, using imm8 for sign control and mantissa
interval normalization, subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
imm8 (r)
N/A
Description
This instruction converts the FP16 values in the source operand (the second operand) to FP16 values with the
mantissa normalization and sign control specified by the imm8 byte, see Table 5-9. The converted results are
written to the destination operand (the first operand) using writemask k1. The normalized mantissa is specified by
interv (imm8[1:0]) and the sign control (SC) is specified by bits 3:2 of the immediate byte.
The destination elements are updated according to the writemask.
Table 5-9. imm8 Controls for VGETMANTPH/VGETMANTSH
imm8 Bits
Definition
imm8[7:4]
Must be zero.
imm8[3:2]
Sign Control (SC)
0b00: Sign(SRC)
0b01: 0
0b1x: QNaN_Indefinite if sign(SRC)!=0
imm8[1:0]
Interv
0b00: Interval is [1, 2)
0b01: Interval is [1/2, 2)
0b10: Interval is [1/2, 1)
0b11: Interval is [3/4, 3/2)
For each input FP16 value x, The conversion operation is:
GetMant(x) = ±2k|x.significand|
where:
1 ≤ |x.significand| < 2
VGETMANTPH—Extract FP16 Vector of Normalized Mantissas from FP16 Vector
Vol. 2C
5-369
INSTRUCTION SET REFERENCE, V
Unbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is
even or odd. The sign of the final result is determined by the sign control and the source sign and the leading frac-
tion bit.
The encoded value of imm8[1:0] and sign control are shown in Table 5-9.
Each converted FP16 result is encoded according to the sign control, the unbiased exponent k (adding bias) and a
mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-10 when dealing with floating-point special numbers.
Table 5-10. GetMant() Special Float Values Behavior
Input
Result
Exceptions / Comments
NaN
QNaN(SRC)
Ignore interv.
If (SRC = SNaN), then #IE.
+∞
1.0
Ignore interv.
+0
1.0
Ignore interv.
-0
IF (SC[0]) THEN +1.0
Ignore interv.
ELSE -1.0
-∞
IF (SC[1]) THEN {QNaN_Indefinite}
Ignore interv.
ELSE {
If (SC[1]), then #IE.
IF (SC[0]) THEN +1.0
ELSE -1.0
negative
SC[1] ? QNaN_Indefinite : Getmant(SRC)1
If (SC[1]), then #IE.
NOTES:
1. In case SC[1]==0, the sign of Getmant(SRC) is declared according to SC[0].
Operation
def getmant_fp16(src, sign_control, normalization_interval):
bias := 15
dst.sign := sign_control[0] ? 0 : src.sign
signed_one := sign_control[0] ? +1.0 : -1.0
dst.exp := src.exp
dst.fraction := src.fraction
zero := (dst.exp = 0) and (dst.fraction = 0)
denormal := (dst.exp = 0) and (dst.fraction != 0)
infinity := (dst.exp = 0x1F) and (dst.fraction = 0)
nan := (dst.exp = 0x1F) and (dst.fraction != 0)
src_signaling := src.fraction[9]
snan := nan and (src_signaling = 0)
positive := (src.sign = 0)
negative := (src.sign = 1)
if nan:
if snan:
MXCSR.IE := 1
return qnan(src)
if positive and (zero or infinity):
return 1.0
if negative:
if zero:
return signed_one
if infinity:
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VGETMANTPH—Extract FP16 Vector of Normalized Mantissas from FP16 Vector
INSTRUCTION SET REFERENCE, V
if sign_control[1]:
MXCSR.IE := 1
return QNaN_Indefinite
return signed_one
if sign_control[1]:
MXCSR.IE := 1
return QNaN_Indefinite
if denormal:
jbit := 0
dst.exp := bias
// set exponent to bias value
while jbit = 0:
jbit := dst.fraction[9]
dst.fraction := dst.fraction << 1
dst.exp : = dst.exp - 1
MXCSR.DE := 1
unbaiased_exp := dst.exp - bias
odd_exp := unbaiased_exp[0]
signaling_bit := dst.fraction[9]
if normalization_interval = 0b00:
dst.exp := bias
else if normalization_interval = 0b01:
dst.exp := odd_exp ? bias-1 : bias
else if normalization_interval = 0b10:
dst.exp := bias-1
else if normalization_interval = 0b11:
dst.exp := signaling_bit ? bias-1 : bias
return dst
VGETMANTPH dest{k1}, src, imm8
VL = 128, 256 or 512
KL := VL/16
sign_control := imm8[3:2]
normalization_interval := imm8[1:0]
FOR i := 0 to KL-1:
IF k1[i] or *no writemask*:
IF SRC is memory and (EVEX.b = 1):
tsrc := src.fp16[0]
ELSE:
tsrc := src.fp16[i]
DEST.fp16[i] := getmant_fp16(tsrc, sign_control, normalization_interval)
ELSE IF *zeroing*:
DEST.fp16[i] := 0
//else DEST.fp16[i] remains unchanged
DEST[MAXVL-1:VL] := 0
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INSTRUCTION SET REFERENCE, V
Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTPH __m128h _mm_getmant_ph (__m128h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m128h _mm_mask_getmant_ph (__m128h src, __mmask8 k, __m128h a, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m128h _mm_maskz_getmant_ph (__mmask8 k, __m128h a, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m256h _mm256_getmant_ph (__m256h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m256h _mm256_mask_getmant_ph (__m256h src, __mmask16 k, __m256h a, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m256h _mm256_maskz_getmant_ph (__mmask16 k, __m256h a, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m512h _mm512_getmant_ph (__m512h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m512h _mm512_mask_getmant_ph (__m512h src, __mmask32 k, __m512h a, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m512h _mm512_maskz_getmant_ph (__mmask32 k, __m512h a, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign);
VGETMANTPH __m512h _mm512_getmant_round_ph (__m512h a, _MM_MANTISSA_NORM_ENUM norm, _MM_MANTISSA_SIGN_ENUM
sign, const int sae);
VGETMANTPH __m512h _mm512_mask_getmant_round_ph (__m512h src, __mmask32 k, __m512h a, _MM_MANTISSA_NORM_ENUM
norm, _MM_MANTISSA_SIGN_ENUM sign, const int sae);
VGETMANTPH __m512h _mm512_maskz_getmant_round_ph (__mmask32 k, __m512h a, _MM_MANTISSA_NORM_ENUM norm,
_MM_MANTISSA_SIGN_ENUM sign, const int sae);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”
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INSTRUCTION SET REFERENCE, V
VGETMANTPS—Extract Float32 Vector of Normalized Mantissas From Float32 Vector
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.128.66.0F3A.W0 26 /r ib
A
V/V
AVX512VL
Get normalized mantissa from float32 vector
VGETMANTPS xmm1 {k1}{z},
AVX512F
xmm2/m128/m32bcst and store the result in xmm1, using
xmm2/m128/m32bcst, imm8
imm8 for sign control and mantissa interval normalization,
under writemask.
EVEX.256.66.0F3A.W0 26 /r ib
A
V/V
AVX512VL
Get normalized mantissa from float32 vector
VGETMANTPS ymm1 {k1}{z},
AVX512F
ymm2/m256/m32bcst and store the result in ymm1, using
ymm2/m256/m32bcst, imm8
imm8 for sign control and mantissa interval normalization,
under writemask.
EVEX.512.66.0F3A.W0 26 /r ib
A
V/V
AVX512F
Get normalized mantissa from float32 vector
VGETMANTPS zmm1 {k1}{z},
zmm2/m512/m32bcst and store the result in zmm1, using
zmm2/m512/m32bcst{sae},
imm8 for sign control and mantissa interval normalization,
imm8
under writemask.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Full
ModRM:reg (w)
ModRM:r/m (r)
imm8
N/A
Description
Convert single-precision floating values in the source operand (the second operand) to single-precision floating-
point values with the mantissa normalization and sign control specified by the imm8 byte, see Figure 5-15. The
converted results are written to the destination operand (the first operand) using writemask k1. The normalized
mantissa is specified by interv (imm8[1:0]) and the sign control (sc) is specified by bits 3:2 of the immediate byte.
The destination operand is a ZMM/YMM/XMM register updated under the writemask. The source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-
bit memory location.
For each input single-precision floating-point value x, The conversion operation is:
GetMant(x) = ±2k|x.significand|
where:
1 <= |x.significand| < 2
Unbiased exponent k can be either 0 or -1, depending on the interval range defined by interv, the range of the
significand and whether the exponent of the source is even or odd. The sign of the final result is determined by sc
and the source sign. The encoded value of imm8[1:0] and sign control are shown in Figure 5-15.
Each converted single-precision floating-point result is encoded according to the sign control, the unbiased expo-
nent k (adding bias) and a mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-8 when dealing with floating-point special numbers.
This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1
are computed and stored into the destination. Elements in zmm1 with the corresponding bit clear in k1 retain their
previous values.
Note: EVEX.vvvv is reserved and must be 1111b, VEX.L must be 0; otherwise instructions will #UD.
VGETMANTPS—Extract Float32 Vector of Normalized Mantissas From Float32 Vector
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INSTRUCTION SET REFERENCE, V
Operation
def getmant_fp32(src, sign_control, normalization_interval):
bias := 127
dst.sign := sign_control[0] ? 0 : src.sign
signed_one := sign_control[0] ? +1.0 : -1.0
dst.exp := src.exp
dst.fraction := src.fraction
zero := (dst.exp = 0) and ((dst.fraction = 0) or (MXCSR.DAZ=1))
denormal := (dst.exp = 0) and (dst.fraction != 0) and (MXCSR.DAZ=0)
infinity := (dst.exp = 0xFF) and (dst.fraction = 0)
nan := (dst.exp = 0xFF) and (dst.fraction != 0)
src_signaling := src.fraction[22]
snan := nan and (src_signaling = 0)
positive := (src.sign = 0)
negative := (src.sign = 1)
if nan:
if snan:
MXCSR.IE := 1
return qnan(src)
if positive and (zero or infinity):
return 1.0
if negative:
if zero:
return signed_one
if infinity:
if sign_control[1]:
MXCSR.IE := 1
return QNaN_Indefinite
return signed_one
if sign_control[1]:
MXCSR.IE := 1
return QNaN_Indefinite
if denormal:
jbit := 0
dst.exp := bias
while jbit = 0:
jbit := dst.fraction[22]
dst.fraction := dst.fraction << 1
dst.exp : = dst.exp - 1
MXCSR.DE := 1
unbiased_exp := dst.exp - bias
odd_exp := unbiased_exp[0]
signaling_bit := dst.fraction[22]
if normalization_interval = 0b00:
dst.exp := bias
else if normalization_interval = 0b01:
dst.exp := odd_exp ? bias-1 : bias
else if normalization_interval = 0b10:
dst.exp := bias-1
else if normalization_interval = 0b11:
dst.exp := signaling_bit ? bias-1 : bias
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INSTRUCTION SET REFERENCE, V
return dst
VGETMANTPS (EVEX encoded versions)
VGETMANTPS dest{k1}, src, imm8
VL = 128, 256, or 512
KL := VL / 32
sign_control := imm8[3:2]
normalization_interval := imm8[1:0]
FOR i := 0 to KL-1:
IF k1[i] or *no writemask*:
IF SRC is memory and (EVEX.b = 1):
tsrc := src.float[0]
ELSE:
tsrc := src.float[i]
DEST.float[i] := getmant_fp32(tsrc, sign_control, normalization_interval)
ELSE IF *zeroing*:
DEST.float[i] := 0
//else DEST.float[i] remains unchanged
DEST[MAX_VL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTPS __m512 _mm512_getmant_ps( __m512 a, enum intv, enum sgn);
VGETMANTPS __m512 _mm512_mask_getmant_ps(__m512 s, __mmask16 k, __m512 a, enum intv, enum sgn;
VGETMANTPS __m512 _mm512_maskz_getmant_ps(__mmask16 k, __m512 a, enum intv, enum sgn);
VGETMANTPS __m512 _mm512_getmant_round_ps( __m512 a, enum intv, enum sgn, int r);
VGETMANTPS __m512 _mm512_mask_getmant_round_ps(__m512 s, __mmask16 k, __m512 a, enum intv, enum sgn, int r);
VGETMANTPS __m512 _mm512_maskz_getmant_round_ps(__mmask16 k, __m512 a, enum intv, enum sgn, int r);
VGETMANTPS __m256 _mm256_getmant_ps( __m256 a, enum intv, enum sgn);
VGETMANTPS __m256 _mm256_mask_getmant_ps(__m256 s, __mmask8 k, __m256 a, enum intv, enum sgn);
VGETMANTPS __m256 _mm256_maskz_getmant_ps( __mmask8 k, __m256 a, enum intv, enum sgn);
VGETMANTPS __m128 _mm_getmant_ps( __m128 a, enum intv, enum sgn);
VGETMANTPS __m128 _mm_mask_getmant_ps(__m128 s, __mmask8 k, __m128 a, enum intv, enum sgn);
VGETMANTPS __m128 _mm_maskz_getmant_ps( __mmask8 k, __m128 a, enum intv, enum sgn);
SIMD Floating-Point Exceptions
Denormal, Invalid
Other Exceptions
See Table 2-46, “Type E2 Class Exception Conditions.”
Additionally:
#UD
If EVEX.vvvv != 1111B.
VGETMANTPS—Extract Float32 Vector of Normalized Mantissas From Float32 Vector
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INSTRUCTION SET REFERENCE, V
VGETMANTSD—Extract Float64 of Normalized Mantissas From Float64 Scalar
Opcode/
Op/
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
EVEX.LLIG.66.0F3A.W1 27 /r ib
A
V/V
AVX512F
Extract the normalized mantissa of the low float64
VGETMANTSD xmm1 {k1}{z}, xmm2,
element in xmm3/m64 using imm8 for sign control and
xmm3/m64{sae}, imm8
mantissa interval normalization. Store the mantissa to
xmm1 under the writemask k1 and merge with the
other elements of xmm2.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
Tuple1 Scalar
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Convert the double precision floating values in the low quadword element of the second source operand (the third
operand) to double precision floating-point value with the mantissa normalization and sign control specified by the
imm8 byte, see Figure 5-15. The converted result is written to the low quadword element of the destination
operand (the first operand) using writemask k1. Bits (127:64) of the XMM register destination are copied from
corresponding bits in the first source operand. The normalized mantissa is specified by interv (imm8[1:0]) and the
sign control (sc) is specified by bits 3:2 of the immediate byte.
The conversion operation is:
GetMant(x) = ±2k|x.significand|
where:
1 <= |x.significand| < 2
Unbiased exponent k can be either 0 or -1, depending on the interval range defined by interv, the range of the
significand and whether the exponent of the source is even or odd. The sign of the final result is determined by sc
and the source sign. The encoded value of imm8[1:0] and sign control are shown in Figure 5-15.
The converted double precision floating-point result is encoded according to the sign control, the unbiased expo-
nent k (adding bias) and a mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-8 when dealing with floating-point special numbers.
If writemasking is used, the low quadword element of the destination operand is conditionally updated depending
on the value of writemask register k1. If writemasking is not used, the low quadword element of the destination
operand is unconditionally updated.
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