Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 65
INSTRUCTION SET REFERENCE, A-L
Operation
VADDSD (EVEX encoded version)
IF (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
IF k1[0] or *no writemask*
THEN DEST[63:0] := SRC1[63:0] + SRC2[63:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] := 0
FI;
FI;
DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0
VADDSD (VEX.128 encoded version)
DEST[63:0] := SRC1[63:0] + SRC2[63:0]
DEST[127:64] := SRC1[127:64]
DEST[MAXVL-1:128] := 0
ADDSD (128-bit Legacy SSE version)
DEST[63:0] := DEST[63:0] + SRC[63:0]
DEST[MAXVL-1:64] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VADDSD __m128d _mm_mask_add_sd (__m128d s, __mmask8 k, __m128d a, __m128d b);
VADDSD __m128d _mm_maskz_add_sd (__mmask8 k, __m128d a, __m128d b);
VADDSD __m128d _mm_add_round_sd (__m128d a, __m128d b, int);
VADDSD __m128d _mm_mask_add_round_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VADDSD __m128d _mm_maskz_add_round_sd (__mmask8 k, __m128d a, __m128d b, int);
ADDSD __m128d _mm_add_sd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instruction, see Table 2-20, “Type 3 Class Exception Conditions”.
EVEX-encoded instruction, see Table 2-47, “Type E3 Class Exception Conditions”.
ADDSD—Add Scalar Double Precision Floating-Point Values
Vol. 2A
3-41
INSTRUCTION SET REFERENCE, A-L
ADDSS—Add Scalar Single Precision Floating-Point Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
F3 0F 58 /r
A
V/V
SSE
Add the low single precision floating-point value from
ADDSS xmm1, xmm2/m32
xmm2/mem to xmm1 and store the result in xmm1.
VEX.LIG.F3.0F.WIG 58 /r
B
V/V
AVX
Add the low single precision floating-point value from
VADDSS xmm1,xmm2,
xmm3/mem to xmm2 and store the result in xmm1.
xmm3/m32
EVEX.LLIG.F3.0F.W0 58 /r
C
V/V
AVX512F
Add the low single precision floating-point value from
VADDSS xmm1{k1}{z}, xmm2,
xmm3/m32 to xmm2 and store the result in xmm1with
xmm3/m32{er}
writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Tuple1 Scalar
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Adds the low single precision floating-point values from the second source operand and the first source operand,
and stores the double precision floating-point result in the destination operand.
The second source operand can be an XMM register or a 64-bit memory location. The first source and destination
operands are XMM registers.
128-bit Legacy SSE version: The first source and destination operands are the same. Bits (MAXVL-1:32) of the
corresponding the destination register remain unchanged.
EVEX and VEX.128 encoded version: The first source operand is encoded by EVEX.vvvv/VEX.vvvv. Bits (127:32) of
the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAXVL-1:128) of
the destination register are zeroed.
EVEX version: The low doubleword element of the destination is updated according to the writemask.
Software should ensure VADDSS is encoded with VEX.L=0. Encoding VADDSS with VEX.L=1 may encounter unpre-
dictable behavior across different processor generations.
3-42
Vol. 2A
ADDSS—Add Scalar Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Operation
VADDSS (EVEX encoded versions)
IF (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);
ELSE
SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);
FI;
IF k1[0] or *no writemask*
THEN DEST[31:0] := SRC1[31:0] + SRC2[31:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0] := 0
FI;
FI;
DEST[127:32] := SRC1[127:32]
DEST[MAXVL-1:128] := 0
VADDSS DEST, SRC1, SRC2 (VEX.128 encoded version)
DEST[31:0] := SRC1[31:0] + SRC2[31:0]
DEST[127:32] := SRC1[127:32]
DEST[MAXVL-1:128] := 0
ADDSS DEST, SRC (128-bit Legacy SSE version)
DEST[31:0] := DEST[31:0] + SRC[31:0]
DEST[MAXVL-1:32] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VADDSS __m128 _mm_mask_add_ss (__m128 s, __mmask8 k, __m128 a, __m128 b);
VADDSS __m128 _mm_maskz_add_ss (__mmask8 k, __m128 a, __m128 b);
VADDSS __m128 _mm_add_round_ss (__m128 a, __m128 b, int);
VADDSS __m128 _mm_mask_add_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VADDSS __m128 _mm_maskz_add_round_ss (__mmask8 k, __m128 a, __m128 b, int);
ADDSS __m128 _mm_add_ss (__m128 a, __m128 b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instruction, see Table 2-20, “Type 3 Class Exception Conditions”.
EVEX-encoded instruction, see Table 2-47, “Type E3 Class Exception Conditions”.
ADDSS—Add Scalar Single Precision Floating-Point Values
Vol. 2A
3-43
INSTRUCTION SET REFERENCE, A-L
ADDSUBPD—Packed Double Precision Floating-Point Add/Subtract
Opcode/
Op/
64/32-bit
CPUID
Description
Instruction
En
Mode
Feature
Flag
66 0F D0 /r
RM
V/V
SSE3
Add/subtract double precision floating-point
values from xmm2/m128 to xmm1.
ADDSUBPD xmm1, xmm2/m128
VEX.128.66.0F.WIG D0 /r
RVM
V/V
AVX
Add/subtract packed double precision
floating-point values from xmm3/mem to
VADDSUBPD xmm1, xmm2, xmm3/m128
xmm2 and stores result in xmm1.
VEX.256.66.0F.WIG D0 /r
RVM
V/V
AVX
Add / subtract packed double precision
floating-point values from ymm3/mem to
VADDSUBPD ymm1, ymm2, ymm3/m256
ymm2 and stores result in ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Adds odd-numbered double precision floating-point values of the first source operand (second operand) with the
corresponding double precision floating-point values from the second source operand (third operand); stores the
result in the odd-numbered values of the destination operand (first operand). Subtracts the even-numbered double
precision floating-point values from the second source operand from the corresponding double precision floating
values in the first source operand; stores the result into the even-numbered values of the destination operand.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding
YMM register destination are unmodified. See Figure 3-3.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
3-44
Vol. 2A
ADDSUBPD—Packed Double Precision Floating-Point Add/Subtract
INSTRUCTION SET REFERENCE, A-L
ADDSUBPD xmm1, xmm2/m128
[127:64]
[63:0]
xmm2/m128
RESULT:
xmm1[127:64] + xmm2/m128[127:64]
xmm1[63:0] - xmm2/m128[63:0]
xmm1
[127:64]
[63:0]
Figure 3-3. ADDSUBPD—Packed Double Precision Floating-Point Add/Subtract
Operation
ADDSUBPD (128-bit Legacy SSE version)
DEST[63:0] := DEST[63:0] - SRC[63:0]
DEST[127:64] := DEST[127:64] + SRC[127:64]
DEST[MAXVL-1:128] (Unmodified)
VADDSUBPD (VEX.128 encoded version)
DEST[63:0] := SRC1[63:0] - SRC2[63:0]
DEST[127:64] := SRC1[127:64] + SRC2[127:64]
DEST[MAXVL-1:128] := 0
VADDSUBPD (VEX.256 encoded version)
DEST[63:0] := SRC1[63:0] - SRC2[63:0]
DEST[127:64] := SRC1[127:64] + SRC2[127:64]
DEST[191:128] := SRC1[191:128] - SRC2[191:128]
DEST[255:192] := SRC1[255:192] + SRC2[255:192]
Intel C/C++ Compiler Intrinsic Equivalent
ADDSUBPD:
__m128d _mm_addsub_pd(__m128d a, __m128d b)
VADDSUBPD:
__m256d _mm256_addsub_pd (__m256d a, __m256d b)
Exceptions
When the source operand is a memory operand, it must be aligned on a 16-byte boundary or a general-protection
exception (#GP) will be generated.
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal.
Other Exceptions
See Table 2-19, “Type 2 Class Exception Conditions”.
ADDSUBPD—Packed Double Precision Floating-Point Add/Subtract
Vol. 2A
3-45
INSTRUCTION SET REFERENCE, A-L
ADDSUBPS—Packed Single Precision Floating-Point Add/Subtract
Opcode/
Op/
64/32-bit
CPUID
Description
Instruction
En
Mode
Feature
Flag
F2 0F D0 /r
RM
V/V
SSE3
Add/subtract single precision floating-point
values from xmm2/m128 to xmm1.
ADDSUBPS xmm1, xmm2/m128
VEX.128.F2.0F.WIG D0 /r
RVM
V/V
AVX
Add/subtract single precision floating-point
values from xmm3/mem to xmm2 and stores
VADDSUBPS xmm1, xmm2, xmm3/m128
result in xmm1.
VEX.256.F2.0F.WIG D0 /r
RVM
V/V
AVX
Add / subtract single precision floating-point
values from ymm3/mem to ymm2 and stores
VADDSUBPS ymm1, ymm2, ymm3/m256
result in ymm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Adds odd-numbered single precision floating-point values of the first source operand (second operand) with the
corresponding single precision floating-point values from the second source operand (third operand); stores the
result in the odd-numbered values of the destination operand (first operand). Subtracts the even-numbered single
precision floating-point values from the second source operand from the corresponding single precision floating
values in the first source operand; stores the result into the even-numbered values of the destination operand.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding
YMM register destination are unmodified. See Figure 3-4.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
3-46
Vol. 2A
ADDSUBPS—Packed Single Precision Floating-Point Add/Subtract
INSTRUCTION SET REFERENCE, A-L
ADDSUBPS xmm1, xmm2/m128
xmm2/
[127:96]
[95:64]
[63:32]
[31:0]
m128
xmm1[127:96] +
xmm1[95:64] - xmm2/
xmm1[63:32] +
xmm1[31:0] -
RESULT:
xmm2/m128[127:96]
m128[95:64]
xmm2/m128[63:32]
xmm2/m128[31:0]
xmm1
[127:96]
[95:64]
[63:32]
[31:0]
OM15992
Figure 3-4. ADDSUBPS—Packed Single Precision Floating-Point Add/Subtract
Operation
ADDSUBPS (128-bit Legacy SSE version)
DEST[31:0] := DEST[31:0] - SRC[31:0]
DEST[63:32] := DEST[63:32] + SRC[63:32]
DEST[95:64] := DEST[95:64] - SRC[95:64]
DEST[127:96] := DEST[127:96] + SRC[127:96]
DEST[MAXVL-1:128] (Unmodified)
VADDSUBPS (VEX.128 encoded version)
DEST[31:0] := SRC1[31:0] - SRC2[31:0]
DEST[63:32] := SRC1[63:32] + SRC2[63:32]
DEST[95:64] := SRC1[95:64] - SRC2[95:64]
DEST[127:96] := SRC1[127:96] + SRC2[127:96]
DEST[MAXVL-1:128] := 0
VADDSUBPS (VEX.256 encoded version)
DEST[31:0] := SRC1[31:0] - SRC2[31:0]
DEST[63:32] := SRC1[63:32] + SRC2[63:32]
DEST[95:64] := SRC1[95:64] - SRC2[95:64]
DEST[127:96] := SRC1[127:96] + SRC2[127:96]
DEST[159:128] := SRC1[159:128] - SRC2[159:128]
DEST[191:160] := SRC1[191:160] + SRC2[191:160]
DEST[223:192] := SRC1[223:192] - SRC2[223:192]
DEST[255:224] := SRC1[255:224] + SRC2[255:224].
Intel C/C++ Compiler Intrinsic Equivalent
ADDSUBPS:
__m128 _mm_addsub_ps(__m128 a, __m128 b)
VADDSUBPS:
__m256 _mm256_addsub_ps (__m256 a, __m256 b)
Exceptions
When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-
protection exception (#GP) will be generated.
ADDSUBPS—Packed Single Precision Floating-Point Add/Subtract
Vol. 2A
3-47
INSTRUCTION SET REFERENCE, A-L
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal.
Other Exceptions
See Table 2-19, “Type 2 Class Exception Conditions”.
3-48
Vol. 2A
ADDSUBPS—Packed Single Precision Floating-Point Add/Subtract
INSTRUCTION SET REFERENCE, A-L
ADOX — Unsigned Integer Addition of Two Operands With Overflow Flag
Opcode/
Op/
64/32bit
CPUID
Description
Instruction
En
Mode
Feature
Support
Flag
F3 0F 38 F6 /r
RM
V/V
ADX
Unsigned addition of r32 with OF, r/m32 to r32, writes OF.
ADOX r32, r/m32
F3 REX.w 0F 38 F6 /r
RM
V/NE
ADX
Unsigned addition of r64 with OF, r/m64 to r64, writes OF.
ADOX r64, r/m64
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
Description
Performs an unsigned addition of the destination operand (first operand), the source operand (second operand)
and the overflow-flag (OF) and stores the result in the destination operand. The destination operand is a general-
purpose register, whereas the source operand can be a general-purpose register or memory location. The state of
OF represents a carry from a previous addition. The instruction sets the OF flag with the carry generated by the
unsigned addition of the operands.
The ADOX instruction is executed in the context of multi-precision addition, where we add a series of operands with
a carry-chain. At the beginning of a chain of additions, we execute an instruction to zero the OF (e.g. XOR).
This instruction is supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-
bit mode.
In 64-bit mode, the default operation size is 32 bits. Using a REX Prefix in the form of REX.R permits access to addi-
tional registers (R8-15). Using REX Prefix in the form of REX.W promotes operation to 64-bits.
ADOX executes normally either inside or outside a transaction region.
Note: ADOX defines the CF and OF flags differently than the ADD/ADC instructions as defined in Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 2A.
Operation
IF OperandSize is 64-bit
THEN OF:DEST[63:0] := DEST[63:0] + SRC[63:0] + OF;
ELSE OF:DEST[31:0] := DEST[31:0] + SRC[31:0] + OF;
FI;
Flags Affected
OF is updated based on result. CF, SF, ZF, AF, and PF flags are unmodified.
Intel C/C++ Compiler Intrinsic Equivalent
unsigned char _addcarryx_u32 (unsigned char c_in, unsigned int src1, unsigned int src2, unsigned int *sum_out);
unsigned char _addcarryx_u64 (unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64 *sum_out);
SIMD Floating-Point Exceptions
None
ADOX — Unsigned Integer Addition of Two Operands With Overflow Flag
Vol. 2A
3-49
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
For an illegal address in the SS segment.
#GP(0)
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If the DS, ES, FS, or GS register is used to access memory and it contains a null segment
selector.
#PF(fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
For an illegal address in the SS segment.
#GP(0)
If any part of the operand lies outside the effective address space from 0 to FFFFH.
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
For an illegal address in the SS segment.
#GP(0)
If any part of the operand lies outside the effective address space from 0 to FFFFH.
#PF(fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
3-50
Vol. 2A
ADOX — Unsigned Integer Addition of Two Operands With Overflow Flag
INSTRUCTION SET REFERENCE, A-L
AESDEC—Perform One Round of an AES Decryption Flow
Opcode/
Op/
64/32-bit
CPUID
Description
Instruction
En
Mode
Feature
Flag
66 0F 38 DE /r
A
V/V
AES
Perform one round of an AES decryption flow, using
AESDEC xmm1, xmm2/m128
the Equivalent Inverse Cipher, using one 128-bit data
(state) from xmm1 with one 128-bit round key from
xmm2/m128.
VEX.128.66.0F38.WIG DE /r
B
V/V
AES
Perform one round of an AES decryption flow, using
VAESDEC xmm1, xmm2, xmm3/m128
AVX
the Equivalent Inverse Cipher, using one 128-bit data
(state) from xmm2 with one 128-bit round key from
xmm3/m128; store the result in xmm1.
VEX.256.66.0F38.WIG DE /r
B
V/V
VAES
Perform one round of an AES decryption flow, using
VAESDEC ymm1, ymm2, ymm3/m256
the Equivalent Inverse Cipher, using two 128-bit data
(state) from ymm2 with two 128-bit round keys from
ymm3/m256; store the result in ymm1.
EVEX.128.66.0F38.WIG DE /r
C
V/V
VAES
Perform one round of an AES decryption flow, using
VAESDEC xmm1, xmm2, xmm3/m128
AVX512VL
the Equivalent Inverse Cipher, using one 128-bit data
(state) from xmm2 with one 128-bit round key from
xmm3/m128; store the result in xmm1.
EVEX.256.66.0F38.WIG DE /r
C
V/V
VAES
Perform one round of an AES decryption flow, using
VAESDEC ymm1, ymm2, ymm3/m256
AVX512VL
the Equivalent Inverse Cipher, using two 128-bit data
(state) from ymm2 with two 128-bit round keys from
ymm3/m256; store the result in ymm1.
EVEX.512.66.0F38.WIG DE /r
C
V/V
VAES
Perform one round of an AES decryption flow, using
VAESDEC zmm1, zmm2, zmm3/m512
AVX512F
the Equivalent Inverse Cipher, using four 128-bit data
(state) from zmm2 with four 128-bit round keys from
zmm3/m512; store the result in zmm1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction performs a single round of the AES decryption flow using the Equivalent Inverse Cipher, using
one/two/four (depending on vector length) 128-bit data (state) from the first source operand with one/two/four
(depending on vector length) round key(s) from the second source operand, and stores the result in the destina-
tion operand.
Use the AESDEC instruction for all but the last decryption round. For the last decryption round, use the AESDE-
CLAST instruction.
VEX and EVEX encoded versions of the instruction allow 3-operand (non-destructive) operation. The legacy
encoded versions of the instruction require that the first source operand and the destination operand are the same
and must be an XMM register.
The EVEX encoded form of this instruction does not support memory fault suppression.
AESDEC—Perform One Round of an AES Decryption Flow
Vol. 2A
3-51
INSTRUCTION SET REFERENCE, A-L
Operation
AESDEC
STATE := SRC1;
RoundKey := SRC2;
STATE := InvShiftRows( STATE );
STATE := InvSubBytes( STATE );
STATE := InvMixColumns( STATE );
DEST[127:0] := STATE XOR RoundKey;
DEST[MAXVL-1:128] (Unmodified)
VAESDEC (128b and 256b VEX encoded versions)
(KL,VL) = (1,128), (2,256)
FOR i = 0 to KL-1:
STATE := SRC1.xmm[i]
RoundKey := SRC2.xmm[i]
STATE := InvShiftRows( STATE )
STATE := InvSubBytes( STATE )
STATE := InvMixColumns( STATE )
DEST.xmm[i] := STATE XOR RoundKey
DEST[MAXVL-1:VL] := 0
VAESDEC (EVEX encoded version)
(KL,VL) = (1,128), (2,256), (4,512)
FOR i = 0 to KL-1:
STATE := SRC1.xmm[i]
RoundKey := SRC2.xmm[i]
STATE := InvShiftRows( STATE )
STATE := InvSubBytes( STATE )
STATE := InvMixColumns( STATE )
DEST.xmm[i] := STATE XOR RoundKey
DEST[MAXVL-1:VL] :=0
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESDEC
__m128i _mm_aesdec (__m128i, __m128i)
VAESDEC
__m256i _mm256_aesdec_epi128(__m256i, __m256i);
VAESDEC
__m512i _mm512_aesdec_epi128(__m512i, __m512i);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-21, “Type 4 Class Exception Conditions”.
EVEX-encoded: See Table 2-50, “Type E4NF Class Exception Conditions”.
3-52
Vol. 2A
AESDEC—Perform One Round of an AES Decryption Flow
INSTRUCTION SET REFERENCE, A-L
AESDEC128KL—Perform Ten Rounds of AES Decryption Flow With Key Locker Using 128-Bit
Key
Opcode/
Op/
64/32-bit
CPUID
Description
Instruction
En
Mode
Feature
Flag
F3 0F 38 DD !(11):rrr:bbb
A
V/V
AESKLE
Decrypt xmm using 128-bit AES key indicated by han-
AESDEC128KL xmm, m384
dle at m384 and store result in xmm.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
Description
The AESDEC128KL1 instruction performs 10 rounds of AES to decrypt the first operand using the 128-bit key indi-
cated by the handle from the second operand. It stores the result in the first operand if the operation succeeds
(e.g., does not run into a handle violation failure).
Operation
AESDEC128KL
Handle := UnalignedLoad of 384 bit (SRC);
// Load is not guaranteed to be atomic.
Illegal Handle = (HandleReservedBitSet (Handle) ||
(Handle[0] AND (CPL > 0)) ||
Handle [2] ||
HandleKeyType (Handle) != HANDLE_KEY_TYPE_AES128);
IF (Illegal Handle) {
THEN RFLAGS.ZF := 1;
ELSE
(UnwrappedKey, Authentic) := UnwrapKeyAndAuthenticate384 (Handle[383:0], IWKey);
IF (Authentic == 0)
THEN RFLAGS.ZF := 1;
ELSE
DEST := AES128Decrypt (DEST, UnwrappedKey) ;
RFLAGS.ZF := 0;
FI;
FI;
RFLAGS.OF, SF, AF, PF, CF := 0;
Flags Affected
ZF is set to 0 if the operation succeeded and set to 1 if the operation failed due to a handle violation. The other
arithmetic flags (OF, SF, AF, PF, CF) are cleared to 0.
Intel C/C++ Compiler Intrinsic Equivalent
AESDEC128KL unsigned char _mm_aesdec128kl_u8(__m128i* odata, __m128i idata, const void* h);
1. Further details on Key Locker and usage of this instruction can be found here:
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
AESDEC128KL—Perform Ten Rounds of AES Decryption Flow With Key Locker Using 128-Bit Key
Vol. 2A
3-53
INSTRUCTION SET REFERENCE, A-L
Exceptions (All Operating Modes)
#UD
If the LOCK prefix is used.
If CPUID.07H:ECX.KL [bit 23] = 0.
If CR4.KL = 0.
If CPUID.19H:EBX.AESKLE [bit 0] = 0.
If CR0.EM = 1.
If CR4.OSFXSR = 0.
#NM
If CR0.TS = 1.
#PF
If a page fault occurs.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
If the memory address is in a non-canonical form.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
If a memory address referencing the SS segment is in a non-canonical form.
3-54
Vol. 2A
AESDEC128KL—Perform Ten Rounds of AES Decryption Flow With Key Locker Using 128-Bit Key
INSTRUCTION SET REFERENCE, A-L
AESDEC256KL—Perform 14 Rounds of AES Decryption Flow With Key Locker Using 256-Bit Key
Opcode/
Op/
64/32-bit
CPUID
Description
Instruction
En
Mode
Feature
Flag
F3 0F 38 DF !(11):rrr:bbb
A
V/V
AESKLE
Decrypt xmm using 256-bit AES key indicated by han-
AESDEC256KL xmm, m512
dle at m512 and store result in xmm.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
Description
The AESDEC256KL1 instruction performs 14 rounds of AES to decrypt the first operand using the 256-bit key indi-
cated by the handle from the second operand. It stores the result in the first operand if the operation succeeds
(e.g., does not run into a handle violation failure).
Operation
AESDEC256KL
Handle := UnalignedLoad of 512 bit (SRC);
// Load is not guaranteed to be atomic.
Illegal Handle = (HandleReservedBitSet (Handle) ||
(Handle[0] AND (CPL > 0)) ||
Handle [2] ||
HandleKeyType (Handle) != HANDLE_KEY_TYPE_AES256);
IF (Illegal Handle)
THEN RFLAGS.ZF := 1;
ELSE
(UnwrappedKey, Authentic) := UnwrapKeyAndAuthenticate512 (Handle[511:0], IWKey);
IF (Authentic == 0)
THEN RFLAGS.ZF := 1;
ELSE
DEST := AES256Decrypt (DEST, UnwrappedKey) ;
RFLAGS.ZF := 0;
FI;
FI;
RFLAGS.OF, SF, AF, PF, CF := 0;
Flags Affected
ZF is set to 0 if the operation succeeded and set to 1 if the operation failed due to a handle violation. The other
arithmetic flags (OF, SF, AF, PF, CF) are cleared to 0.
Intel C/C++ Compiler Intrinsic Equivalent
AESDEC256KL unsigned char _mm_aesdec256kl_u8(__m128i* odata, __m128i idata, const void* h);
1. Further details on Key Locker and usage of this instruction can be found here:
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
AESDEC256KL—Perform 14 Rounds of AES Decryption Flow With Key Locker Using 256-Bit Key
Vol. 2A
3-55
INSTRUCTION SET REFERENCE, A-L
Exceptions (All Operating Modes)
#UD
If the LOCK prefix is used.
If CPUID.07H:ECX.KL [bit 23] = 0.
If CR4.KL = 0.
If CPUID.19H:EBX.AESKLE [bit 0] = 0.
If CR0.EM = 1.
If CR4.OSFXSR = 0.
#NM
If CR0.TS = 1.
#PF
If a page fault occurs.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
If the memory address is in a non-canonical form.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
If a memory address referencing the SS segment is in a non-canonical form.
3-56
Vol. 2A
AESDEC256KL—Perform 14 Rounds of AES Decryption Flow With Key Locker Using 256-Bit Key
INSTRUCTION SET REFERENCE, A-L
AESDECLAST—Perform Last Round of an AES Decryption Flow
Opcode/
Op/
64/32-bit
CPUID
Description
Instruction
En
Mode
Feature
Flag
66 0F 38 DF /r
A
V/V
AES
Perform the last round of an AES decryption flow,
AESDECLAST xmm1, xmm2/m128
using the Equivalent Inverse Cipher, using one 128-bit
data (state) from xmm1 with one 128-bit round key
from xmm2/m128.
VEX.128.66.0F38.WIG DF /r
B
V/V
AES
Perform the last round of an AES decryption flow,
VAESDECLAST xmm1, xmm2, xmm3/m128
AVX
using the Equivalent Inverse Cipher, using one 128-bit
data (state) from xmm2 with one 128-bit round key
from xmm3/m128; store the result in xmm1.
VEX.256.66.0F38.WIG DF /r
B
V/V
VAES
Perform the last round of an AES decryption flow,
VAESDECLAST ymm1, ymm2, ymm3/m256
using the Equivalent Inverse Cipher, using two 128-
bit data (state) from ymm2 with two 128-bit round
keys from ymm3/m256; store the result in ymm1.
EVEX.128.66.0F38.WIG DF /r
C
V/V
VAES
Perform the last round of an AES decryption flow,
VAESDECLAST xmm1, xmm2, xmm3/m128
AVX512VL
using the Equivalent Inverse Cipher, using one 128-bit
data (state) from xmm2 with one 128-bit round key
from xmm3/m128; store the result in xmm1.
EVEX.256.66.0F38.WIG DF /r
C
V/V
VAES
Perform the last round of an AES decryption flow,
VAESDECLAST ymm1, ymm2, ymm3/m256
AVX512VL
using the Equivalent Inverse Cipher, using two 128-
bit data (state) from ymm2 with two 128-bit round
keys from ymm3/m256; store the result in ymm1.
EVEX.512.66.0F38.WIG DF /r
C
V/V
VAES
Perform the last round of an AES decryption flow,
VAESDECLAST zmm1, zmm2, zmm3/m512
AVX512F
using the Equivalent Inverse Cipher, using four128-bit
data (state) from zmm2 with four 128-bit round keys
from zmm3/m512; store the result in zmm1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction performs the last round of the AES decryption flow using the Equivalent Inverse Cipher, using
one/two/four (depending on vector length) 128-bit data (state) from the first source operand with one/two/four
(depending on vector length) round key(s) from the second source operand, and stores the result in the destina-
tion operand.
VEX and EVEX encoded versions of the instruction allow 3-operand (non-destructive) operation. The legacy
encoded versions of the instruction require that the first source operand and the destination operand are the same
and must be an XMM register.
The EVEX encoded form of this instruction does not support memory fault suppression.
AESDECLAST—Perform Last Round of an AES Decryption Flow
Vol. 2A
3-57
INSTRUCTION SET REFERENCE, A-L
Operation
AESDECLAST
STATE := SRC1;
RoundKey := SRC2;
STATE := InvShiftRows( STATE );
STATE := InvSubBytes( STATE );
DEST[127:0] := STATE XOR RoundKey;
DEST[MAXVL-1:128] (Unmodified)
VAESDECLAST (128b and 256b VEX encoded versions)
(KL,VL) = (1,128), (2,256)
FOR i = 0 to KL-1:
STATE := SRC1.xmm[i]
RoundKey := SRC2.xmm[i]
STATE := InvShiftRows( STATE )
STATE := InvSubBytes( STATE )
DEST.xmm[i] := STATE XOR RoundKey
DEST[MAXVL-1:VL] := 0
VAESDECLAST (EVEX encoded version)
(KL,VL) = (1,128), (2,256), (4,512)
FOR i = 0 to KL-1:
STATE := SRC1.xmm[i]
RoundKey := SRC2.xmm[i]
STATE := InvShiftRows( STATE )
STATE := InvSubBytes( STATE )
DEST.xmm[i] := STATE XOR RoundKey
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESDECLAST
__m128i _mm_aesdeclast (__m128i, __m128i)
VAESDECLAST
__m256i _mm256_aesdeclast_epi128(__m256i, __m256i);
VAESDECLAST
__m512i _mm512_aesdeclast_epi128(__m512i, __m512i);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-21, “Type 4 Class Exception Conditions”.
EVEX-encoded: See Table 2-50, “Type E4NF Class Exception Conditions”.
3-58
Vol. 2A
AESDECLAST—Perform Last Round of an AES Decryption Flow
INSTRUCTION SET REFERENCE, A-L
AESDECWIDE128KL—Perform Ten Rounds of AES Decryption Flow With Key Locker on 8 Blocks
Using 128-Bit Key
Opcode/
Op/
64/32-bit
CPUID Feature
Description
Instruction
En
Mode
Flag
F3 0F 38 D8 !(11):001:bbb
A
V/V
AESKLEWIDE_KL
Decrypt XMM0-7 using 128-bit AES key indicated
AESDECWIDE128KL m384, <XMM0-7>
by handle at m384 and store each resultant block
back to its corresponding register.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operands 2—9
A
N/A
ModRM:r/m (r)
Implicit XMM0-7 (r, w)
Description
The AESDECWIDE128KL1 instruction performs ten rounds of AES to decrypt each of the eight blocks in XMM0-7
using the 128-bit key indicated by the handle from the second operand. It replaces each input block in XMM0-7
with its corresponding decrypted block if the operation succeeds (e.g., does not run into a handle violation failure).
Operation
AESDECWIDE128KL
Handle := UnalignedLoad of 384 bit (SRC);
// Load is not guaranteed to be atomic.
Illegal Handle = (HandleReservedBitSet (Handle) ||
(Handle[0] AND (CPL > 0)) ||
Handle [2] ||
HandleKeyType (Handle) != HANDLE_KEY_TYPE_AES128);
IF (Illegal Handle)
THEN RFLAGS.ZF := 1;
ELSE
(UnwrappedKey, Authentic) := UnwrapKeyAndAuthenticate384 (Handle[383:0], IWKey);
IF Authentic == 0 {
THEN RFLAGS.ZF := 1;
ELSE
XMM0 := AES128Decrypt (XMM0, UnwrappedKey) ;
XMM1 := AES128Decrypt (XMM1, UnwrappedKey) ;
XMM2 := AES128Decrypt (XMM2, UnwrappedKey) ;
XMM3 := AES128Decrypt (XMM3, UnwrappedKey) ;
XMM4 := AES128Decrypt (XMM4, UnwrappedKey) ;
XMM5 := AES128Decrypt (XMM5, UnwrappedKey) ;
XMM6 := AES128Decrypt (XMM6, UnwrappedKey) ;
XMM7 := AES128Decrypt (XMM7, UnwrappedKey) ;
RFLAGS.ZF := 0;
FI;
FI;
RFLAGS.OF, SF, AF, PF, CF := 0;
Flags Affected
ZF is set to 0 if the operation succeeded and set to 1 if the operation failed due to a handle violation. The other
arithmetic flags (OF, SF, AF, PF, CF) are cleared to 0.
1. Further details on Key Locker and usage of this instruction can be found here:
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
AESDECWIDE128KL—Perform Ten Rounds of AES Decryption Flow With Key Locker on 8 Blocks Using 128-Bit Key
Vol. 2A
3-59
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
AESDECWIDE128KL
unsigned char _mm_aesdecwide128kl_u8(__m128i odata[8], const __m128i idata[8], const void* h);
Exceptions (All Operating Modes)
#UD
If the LOCK prefix is used.
If CPUID.07H:ECX.KL [bit 23] = 0.
If CR4.KL = 0.
If CPUID.19H:EBX.AESKLE [bit 0] = 0.
If CR0.EM = 1.
If CR4.OSFXSR = 0.
If CPUID.19H:EBX.WIDE_KL [bit 2] = 0.
#NM
If CR0.TS = 1.
#PF
If a page fault occurs.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
If the memory address is in a non-canonical form.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
If a memory address referencing the SS segment is in a non-canonical form.
3-60
Vol. 2A
AESDECWIDE128KL—Perform Ten Rounds of AES Decryption Flow With Key Locker on 8 Blocks Using 128-Bit Key
INSTRUCTION SET REFERENCE, A-L
AESDECWIDE256KL—Perform 14 Rounds of AES Decryption Flow With Key Locker on 8 Blocks
Using 256-Bit Key
Opcode/
Op/
64/32-bit
CPUID Feature
Description
Instruction
En
Mode
Flag
F3 0F 38 D8 !(11):011:bbb
A
V/V
AESKLEWIDE_KL
Decrypt XMM0-7 using 256-bit AES key indicated
AESDECWIDE256KL m512, <XMM0-7>
by handle at m512 and store each resultant block
back to its corresponding register.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operands 2—9
A
N/A
ModRM:r/m (r)
Implicit XMM0-7 (r, w)
Description
The AESDECWIDE256KL1 instruction performs 14 rounds of AES to decrypt each of the eight blocks in XMM0-7
using the 256-bit key indicated by the handle from the second operand. It replaces each input block in XMM0-7
with its corresponding decrypted block if the operation succeeds (e.g., does not run into a handle violation failure).
Operation
AESDECWIDE256KL
Handle := UnalignedLoad of 512 bit (SRC);
// Load is not guaranteed to be atomic.
Illegal Handle = (HandleReservedBitSet (Handle) ||
(Handle[0] AND (CPL > 0)) ||
Handle [2] ||
HandleKeyType (Handle) != HANDLE_KEY_TYPE_AES256);
IF (Illegal Handle) {
THEN RFLAGS.ZF := 1;
ELSE
(UnwrappedKey, Authentic) := UnwrapKeyAndAuthenticate512 (Handle[511:0], IWKey);
IF (Authentic == 0)
THEN RFLAGS.ZF := 1;
ELSE
XMM0 := AES256Decrypt (XMM0, UnwrappedKey) ;
XMM1 := AES256Decrypt (XMM1, UnwrappedKey) ;
XMM2 := AES256Decrypt (XMM2, UnwrappedKey) ;
XMM3 := AES256Decrypt (XMM3, UnwrappedKey) ;
XMM4 := AES256Decrypt (XMM4, UnwrappedKey) ;
XMM5 := AES256Decrypt (XMM5, UnwrappedKey) ;
XMM6 := AES256Decrypt (XMM6, UnwrappedKey) ;
XMM7 := AES256Decrypt (XMM7, UnwrappedKey) ;
RFLAGS.ZF := 0;
FI;
FI;
RFLAGS.OF, SF, AF, PF, CF := 0;
Flags Affected
ZF is set to 0 if the operation succeeded and set to 1 if the operation failed due to a handle violation. The other
arithmetic flags (OF, SF, AF, PF, CF) are cleared to 0.
1. Further details on Key Locker and usage of this instruction can be found here:
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
AESDECWIDE256KL—Perform 14 Rounds of AES Decryption Flow With Key Locker on 8 Blocks Using 256-Bit Key
Vol. 2A
3-61
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
AESDECWIDE256KL
unsigned char _mm_aesdecwide256kl_u8(__m128i odata[8], const __m128i idata[8], const void* h);
Exceptions (All Operating Modes)
#UD
If the LOCK prefix is used.
If CPUID.07H:ECX.KL [bit 23] = 0.
If CR4.KL = 0.
If CPUID.19H:EBX.AESKLE [bit 0] = 0.
If CR0.EM = 1.
If CR4.OSFXSR = 0.
If CPUID.19H:EBX.WIDE_KL [bit 2] = 0.
#NM
If CR0.TS = 1.
#PF
If a page fault occurs.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
If the memory address is in a non-canonical form.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
If a memory address referencing the SS segment is in a non-canonical form.
3-62
Vol. 2A
AESDECWIDE256KL—Perform 14 Rounds of AES Decryption Flow With Key Locker on 8 Blocks Using 256-Bit Key
INSTRUCTION SET REFERENCE, A-L
AESENC—Perform One Round of an AES Encryption Flow
Opcode/
Op/
64/32-bit
CPUID
Description
Instruction
En
Mode
Feature
Flag
66 0F 38 DC /r
A
V/V
AES
Perform one round of an AES encryption flow, using one
AESENC xmm1, xmm2/m128
128-bit data (state) from xmm1 with one 128-bit round
key from xmm2/m128.
VEX.128.66.0F38.WIG DC /r
B
V/V
AES
Perform one round of an AES encryption flow, using one
VAESENC xmm1, xmm2, xmm3/m128
AVX
128-bit data (state) from xmm2 with one 128-bit round
key from the xmm3/m128; store the result in xmm1.
VEX.256.66.0F38.WIG DC /r
B
V/V
VAES
Perform one round of an AES encryption flow, using two
VAESENC ymm1, ymm2, ymm3/m256
128-bit data (state) from ymm2 with two 128-bit round
keys from the ymm3/m256; store the result in ymm1.
EVEX.128.66.0F38.WIG DC /r
C
V/V
VAES
Perform one round of an AES encryption flow, using one
VAESENC xmm1, xmm2, xmm3/m128
AVX512VL
128-bit data (state) from xmm2 with one 128-bit round
key from the xmm3/m128; store the result in xmm1.
EVEX.256.66.0F38.WIG DC /r
C
V/V
VAES
Perform one round of an AES encryption flow, using two
VAESENC ymm1, ymm2, ymm3/m256
AVX512VL
128-bit data (state) from ymm2 with two 128-bit round
keys from the ymm3/m256; store the result in ymm1.
EVEX.512.66.0F38.WIG DC /r
C
V/V
VAES
Perform one round of an AES encryption flow, using four
VAESENC zmm1, zmm2, zmm3/m512
AVX512F
128-bit data (state) from zmm2 with four 128-bit round
keys from the zmm3/m512; store the result in zmm1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction performs a single round of an AES encryption flow using one/two/four (depending on vector
length) 128-bit data (state) from the first source operand with one/two/four (depending on vector length) round
key(s) from the second source operand, and stores the result in the destination operand.
Use the AESENC instruction for all but the last encryption rounds. For the last encryption round, use the AESENC-
CLAST instruction.
VEX and EVEX encoded versions of the instruction allow 3-operand (non-destructive) operation. The legacy
encoded versions of the instruction require that the first source operand and the destination operand are the same
and must be an XMM register.
The EVEX encoded form of this instruction does not support memory fault suppression.
Operation
AESENC
STATE := SRC1;
RoundKey := SRC2;
STATE := ShiftRows( STATE );
STATE := SubBytes( STATE );
STATE := MixColumns( STATE );
DEST[127:0] := STATE XOR RoundKey;
DEST[MAXVL-1:128] (Unmodified)
AESENC—Perform One Round of an AES Encryption Flow
Vol. 2A
3-63
INSTRUCTION SET REFERENCE, A-L
VAESENC (128b and 256b VEX encoded versions)
(KL,VL) = (1,128), (2,256)
FOR I := 0 to KL-1:
STATE := SRC1.xmm[i]
RoundKey := SRC2.xmm[i]
STATE := ShiftRows( STATE )
STATE := SubBytes( STATE )
STATE := MixColumns( STATE )
DEST.xmm[i] := STATE XOR RoundKey
DEST[MAXVL-1:VL] := 0
VAESENC (EVEX encoded version)
(KL,VL) = (1,128), (2,256), (4,512)
FOR i := 0 to KL-1:
STATE := SRC1.xmm[i] // xmm[i] is the i’th xmm word in the SIMD register
RoundKey := SRC2.xmm[i]
STATE := ShiftRows( STATE )
STATE := SubBytes( STATE )
STATE := MixColumns( STATE )
DEST.xmm[i] := STATE XOR RoundKey
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESENC:
__m128i _mm_aesenc (__m128i, __m128i)
VAESENC __m256i _mm256_aesenc_epi128(__m256i, __m256i);
VAESENC __m512i _mm512_aesenc_epi128(__m512i, __m512i);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-21, “Type 4 Class Exception Conditions”.
EVEX-encoded: See Table 2-50, “Type E4NF Class Exception Conditions”.
3-64
Vol. 2A
AESENC—Perform One Round of an AES Encryption Flow
INSTRUCTION SET REFERENCE, A-L
AESENC128KL—Perform Ten Rounds of AES Encryption Flow With Key Locker Using 128-Bit Key
Opcode/
Op/
64/32-bit
CPUID
Description
Instruction
En
Mode
Feature
Flag
F3 0F 38 DC !(11):rrr:bbb
A
V/V
AESKLE
Encrypt xmm using 128-bit AES key indicated by han-
AESENC128KL xmm, m384
dle at m384 and store result in xmm.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
Description
The AESENC128KL1 instruction performs ten rounds of AES to encrypt the first operand using the 128-bit key indi-
cated by the handle from the second operand. It stores the result in the first operand if the operation succeeds
(e.g., does not run into a handle violation failure).
Operation
AESENC128KL
Handle := UnalignedLoad of 384 bit (SRC);
// Load is not guaranteed to be atomic.
Illegal Handle = (
HandleReservedBitSet (Handle) ||
(Handle[0] AND (CPL > 0)) ||
Handle [1] ||
HandleKeyType (Handle) != HANDLE_KEY_TYPE_AES128
);
IF (Illegal Handle) {
THEN RFLAGS.ZF := 1;
ELSE
(UnwrappedKey, Authentic) := UnwrapKeyAndAuthenticate384 (Handle[383:0], IWKey);
IF (Authentic == 0)
THEN RFLAGS.ZF := 1;
ELSE
DEST := AES128Encrypt (DEST, UnwrappedKey) ;
RFLAGS.ZF := 0;
FI;
FI;
RFLAGS.OF, SF, AF, PF, CF := 0;
Flags Affected
ZF is set to 0 if the operation succeeded and set to 1 if the operation failed due to a handle violation. The other
arithmetic flags (OF, SF, AF, PF, CF) are cleared to 0.
Intel C/C++ Compiler Intrinsic Equivalent
AESENC128KL unsigned char _mm_aesenc128kl_u8(__m128i* odata, __m128i idata, const void* h);
1. Further details on Key Locker and usage of this instruction can be found here:
AESENC128KL—Perform Ten Rounds of AES Encryption Flow With Key Locker Using 128-Bit Key
Vol. 2A
3-65
INSTRUCTION SET REFERENCE, A-L
Exceptions (All Operating Modes)
#UD
If the LOCK prefix is used.
If CPUID.07H:ECX.KL [bit 23] = 0.
If CR4.KL = 0.
If CPUID.19H:EBX.AESKLE [bit 0] = 0.
If CR0.EM = 1.
If CR4.OSFXSR = 0.
#NM
If CR0.TS = 1.
#PF
If a page fault occurs.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
If the memory address is in a non-canonical form.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
If a memory address referencing the SS segment is in a non-canonical form.
3-66
Vol. 2A
AESENC128KL—Perform Ten Rounds of AES Encryption Flow With Key Locker Using 128-Bit Key
INSTRUCTION SET REFERENCE, A-L
AESENC256KL—Perform 14 Rounds of AES Encryption Flow With Key Locker Using 256-Bit Key
Opcode/
Op/
64/32-bit
CPUID
Description
Instruction
En
Mode
Feature
Flag
F3 0F 38 DE !(11):rrr:bbb
A
V/V
AESKLE
Encrypt xmm using 256-bit AES key indicated by han-
AESENC256KL xmm, m512
dle at m512 and store result in xmm.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
Description
The AESENC256KL1 instruction performs 14 rounds of AES to encrypt the first operand using the 256-bit key indi-
cated by the handle from the second operand. It stores the result in the first operand if the operation succeeds
(e.g., does not run into a handle violation failure).
Operation
AESENC256KL
Handle := UnalignedLoad of 512 bit (SRC);
// Load is not guaranteed to be atomic.
Illegal Handle = (
HandleReservedBitSet (Handle) ||
(Handle[0] AND (CPL > 0)) ||
Handle [1] ||
HandleKeyType (Handle) != HANDLE_KEY_TYPE_AES256
);
IF (Illegal Handle)
THEN RFLAGS.ZF := 1;
ELSE
(UnwrappedKey, Authentic) := UnwrapKeyAndAuthenticate512 (Handle[511:0], IWKey);
IF (Authentic == 0)
THEN RFLAGS.ZF := 1;
ELSE
DEST := AES256Encrypt (DEST, UnwrappedKey) ;
RFLAGS.ZF := 0;
FI;
FI;
RFLAGS.OF, SF, AF, PF, CF := 0;
Flags Affected
ZF is set to 0 if the operation succeeded and set to 1 if the operation failed due to a handle violation. The other
arithmetic flags (OF, SF, AF, PF, CF) are cleared to 0.
Intel C/C++ Compiler Intrinsic Equivalent
AESENC256KL unsigned char _mm_aesenc256kl_u8(__m128i* odata, __m128i idata, const void* h);
1. Further details on Key Locker and usage of this instruction can be found here:
AESENC256KL—Perform 14 Rounds of AES Encryption Flow With Key Locker Using 256-Bit Key
Vol. 2A
3-67
INSTRUCTION SET REFERENCE, A-L
Exceptions (All Operating Modes)
#UD
If the LOCK prefix is used.
If CPUID.07H:ECX.KL [bit 23] = 0.
If CR4.KL = 0.
If CPUID.19H:EBX.AESKLE [bit 0] = 0.
If CR0.EM = 1.
If CR4.OSFXSR = 0.
#NM
If CR0.TS = 1.
#PF
If a page fault occurs.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
If the memory address is in a non-canonical form.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
If a memory address referencing the SS segment is in a non-canonical form.
3-68
Vol. 2A
AESENC256KL—Perform 14 Rounds of AES Encryption Flow With Key Locker Using 256-Bit Key
INSTRUCTION SET REFERENCE, A-L
AESENCLAST—Perform Last Round of an AES Encryption Flow
Opcode/
Op/
64/32-bit
CPUID
Description
Instruction
En
Mode
Feature
Flag
66 0F 38 DD /r
A
V/V
AES
Perform the last round of an AES encryption flow,
AESENCLAST xmm1, xmm2/m128
using one 128-bit data (state) from xmm1 with one
128-bit round key from xmm2/m128.
VEX.128.66.0F38.WIG DD /r
B
V/V
AES
Perform the last round of an AES encryption flow,
VAESENCLAST xmm1, xmm2, xmm3/m128
AVX
using one 128-bit data (state) from xmm2 with one
128-bit round key from xmm3/m128; store the result
in xmm1.
VEX.256.66.0F38.WIG DD /r
B
V/V
VAES
Perform the last round of an AES encryption flow,
VAESENCLAST ymm1, ymm2, ymm3/m256
using two 128-bit data (state) from ymm2 with two
128-bit round keys from ymm3/m256; store the
result in ymm1.
EVEX.128.66.0F38.WIG DD /r
C
V/V
VAES
Perform the last round of an AES encryption flow,
VAESENCLAST xmm1, xmm2, xmm3/m128
AVX512VL
using one 128-bit data (state) from xmm2 with one
128-bit round key from xmm3/m128; store the result
in xmm1.
EVEX.256.66.0F38.WIG DD /r
C
V/V
VAES
Perform the last round of an AES encryption flow,
VAESENCLAST ymm1, ymm2, ymm3/m256
AVX512VL
using two 128-bit data (state) from ymm2 with two
128-bit round keys from ymm3/m256; store the
result in ymm1.
EVEX.512.66.0F38.WIG DD /r
C
V/V
VAES
Perform the last round of an AES encryption flow,
VAESENCLAST zmm1, zmm2, zmm3/m512
AVX512F
using four 128-bit data (state) from zmm2 with four
128-bit round keys from zmm3/m512; store the
result in zmm1.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full Mem
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
This instruction performs the last round of an AES encryption flow using one/two/four (depending on vector length)
128-bit data (state) from the first source operand with one/two/four (depending on vector length) round key(s)
from the second source operand, and stores the result in the destination operand.
VEX and EVEX encoded versions of the instruction allows 3-operand (non-destructive) operation. The legacy
encoded versions of the instruction require that the first source operand and the destination operand are the same
and must be an XMM register.
The EVEX encoded form of this instruction does not support memory fault suppression.
AESENCLAST—Perform Last Round of an AES Encryption Flow
Vol. 2A
3-69
INSTRUCTION SET REFERENCE, A-L
Operation
AESENCLAST
STATE := SRC1;
RoundKey := SRC2;
STATE := ShiftRows( STATE );
STATE := SubBytes( STATE );
DEST[127:0] := STATE XOR RoundKey;
DEST[MAXVL-1:128] (Unmodified)
VAESENCLAST (128b and 256b VEX encoded versions)
(KL, VL) = (1,128), (2,256)
FOR I=0 to KL-1:
STATE := SRC1.xmm[i]
RoundKey := SRC2.xmm[i]
STATE := ShiftRows( STATE )
STATE := SubBytes( STATE )
DEST.xmm[i] := STATE XOR RoundKey
DEST[MAXVL-1:VL] := 0
VAESENCLAST (EVEX encoded version)
(KL,VL) = (1,128), (2,256), (4,512)
FOR i = 0 to KL-1:
STATE := SRC1.xmm[i]
RoundKey := SRC2.xmm[i]
STATE := ShiftRows( STATE )
STATE := SubBytes( STATE )
DEST.xmm[i] := STATE XOR RoundKey
DEST[MAXVL-1:VL] := 0
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESENCLAST
__m128i _mm_aesenclast (__m128i, __m128i)
VAESENCLAST
__m256i _mm256_aesenclast_epi128(__m256i, __m256i);
VAESENCLAST
__m512i _mm512_aesenclast_epi128(__m512i, __m512i);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-21, “Type 4 Class Exception Conditions”.
EVEX-encoded: See Table 2-50, “Type E4NF Class Exception Conditions”.
3-70
Vol. 2A
AESENCLAST—Perform Last Round of an AES Encryption Flow
INSTRUCTION SET REFERENCE, A-L
AESENCWIDE128KL—Perform Ten Rounds of AES Encryption Flow With Key Locker on 8 Blocks
Using 128-Bit Key
Opcode/
Op/
64/32-bit
CPUID Feature
Description
Instruction
En
Mode
Flag
F3 0F 38 D8 !(11):000:bbb
A
V/V
AESKLE WIDE_KL
Encrypt XMM0-7 using 128-bit AES key indicated
AESENCWIDE128KL m384, <XMM0-7>
by handle at m384 and store each resultant block
back to its corresponding register.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operands 2—9
A
N/A
ModRM:r/m (r)
Implicit XMM0-7 (r, w)
Description
The AESENCWIDE128KL1 instruction performs ten rounds of AES to encrypt each of the eight blocks in XMM0-7
using the 128-bit key indicated by the handle from the second operand. It replaces each input block in XMM0-7
with its corresponding encrypted block if the operation succeeds (e.g., does not run into a handle violation failure).
Operation
AESENCWIDE128KL
Handle := UnalignedLoad of 384 bit (SRC);
// Load is not guaranteed to be atomic.
Illegal Handle = (
HandleReservedBitSet (Handle) ||
(Handle[0] AND (CPL > 0)) ||
Handle [1] ||
HandleKeyType (Handle) != HANDLE_KEY_TYPE_AES128
);
IF (Illegal Handle)
THEN RFLAGS.ZF := 1;
ELSE
(UnwrappedKey, Authentic) := UnwrapKeyAndAuthenticate384 (Handle[383:0], IWKey);
IF Authentic == 0
THEN RFLAGS.ZF := 1;
ELSE
XMM0 := AES128Encrypt (XMM0, UnwrappedKey) ;
XMM1 := AES128Encrypt (XMM1, UnwrappedKey) ;
XMM2 := AES128Encrypt (XMM2, UnwrappedKey) ;
XMM3 := AES128Encrypt (XMM3, UnwrappedKey) ;
XMM4 := AES128Encrypt (XMM4, UnwrappedKey) ;
XMM5 := AES128Encrypt (XMM5, UnwrappedKey) ;
XMM6 := AES128Encrypt (XMM6, UnwrappedKey) ;
XMM7 := AES128Encrypt (XMM7, UnwrappedKey) ;
RFLAGS.ZF := 0;
FI;
FI;
RFLAGS.OF, SF, AF, PF, CF := 0;
1. Further details on Key Locker and usage of this instruction can be found here:
AESENCWIDE128KL—Perform Ten Rounds of AES Encryption Flow With Key Locker on 8 Blocks Using 128-Bit Key
Vol. 2A
3-71
INSTRUCTION SET REFERENCE, A-L
Flags Affected
ZF is set to 0 if the operation succeeded and set to 1 if the operation failed due to a handle violation. The other
arithmetic flags (OF, SF, AF, PF, CF) are cleared to 0.
Intel C/C++ Compiler Intrinsic Equivalent
AESENCWIDE128KL
unsigned char _mm_aesencwide128kl_u8(__m128i odata[8], const __m128i idata[8], const void* h);
Exceptions (All Operating Modes)
#UD
If the LOCK prefix is used.
If CPUID.07H:ECX.KL [bit 23] = 0.
If CR4.KL = 0.
If CPUID.AESKLE = 0.
If CR0.EM = 1.
If CR4.OSFXSR = 0.
If CPUID.19H:EBX.WIDE_KL [bit 2] = 0.
#NM
If CR0.TS = 1.
#PF
If a page fault occurs.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
If the memory address is in a non-canonical form.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
If a memory address referencing the SS segment is in a non-canonical form.
3-72
Vol. 2A
AESENCWIDE128KL—Perform Ten Rounds of AES Encryption Flow With Key Locker on 8 Blocks Using 128-Bit Key
INSTRUCTION SET REFERENCE, A-L
AESENCWIDE256KL—Perform 14 Rounds of AES Encryption Flow With Key Locker on 8 Blocks
Using 256-Bit Key
Opcode/
Op/
64/32-bit
CPUID Feature
Description
Instruction
En
Mode
Flag
F3 0F 38 D8 !(11):010:bbb
A
V/V
AESKLE WIDE_KL
Encrypt XMM0-7 using 256-bit AES key indicated
AESENCWIDE256KL m512, <XMM0-7>
by handle at m512 and store each resultant block
back to its corresponding register.
Instruction Operand Encoding
Op/En
Tuple
Operand 1
Operands 2—9
A
N/A
ModRM:r/m (r)
Implicit XMM0-7 (r, w)
Description
The AESENCWIDE256KL1 instruction performs 14 rounds of AES to encrypt each of the eight blocks in XMM0-7
using the 256-bit key indicated by the handle from the second operand. It replaces each input block in XMM0-7
with its corresponding encrypted block if the operation succeeds (e.g., does not run into a handle violation failure).
Operation
AESENCWIDE256KL
Handle := UnalignedLoad of 512 bit (SRC);
// Load is not guaranteed to be atomic.
Illegal Handle = (
HandleReservedBitSet (Handle) ||
(Handle[0] AND (CPL > 0)) ||
Handle [1] ||
HandleKeyType (Handle) != HANDLE_KEY_TYPE_AES256
);
IF (Illegal Handle)
THEN RFLAGS.ZF := 1;
ELSE
(UnwrappedKey, Authentic) := UnwrapKeyAndAuthenticate512 (Handle[511:0], IWKey);
IF (Authentic == 0)
THEN RFLAGS.ZF := 1;
ELSE
XMM0 := AES256Encrypt (XMM0, UnwrappedKey) ;
XMM1 := AES256Encrypt (XMM1, UnwrappedKey) ;
XMM2 := AES256Encrypt (XMM2, UnwrappedKey) ;
XMM3 := AES256Encrypt (XMM3, UnwrappedKey) ;
XMM4 := AES256Encrypt (XMM4, UnwrappedKey) ;
XMM5 := AES256Encrypt (XMM5, UnwrappedKey) ;
XMM6 := AES256Encrypt (XMM6, UnwrappedKey) ;
XMM7 := AES256Encrypt (XMM7, UnwrappedKey) ;
RFLAGS.ZF := 0;
FI;
FI;
RFLAGS.OF, SF, AF, PF, CF := 0;
1. Further details on Key Locker and usage of this instruction can be found here:
AESENCWIDE256KL—Perform 14 Rounds of AES Encryption Flow With Key Locker on 8 Blocks Using 256-Bit Key
Vol. 2A
3-73
INSTRUCTION SET REFERENCE, A-L
Flags Affected
ZF is set to 0 if the operation succeeded and set to 1 if the operation failed due to a handle violation. The other
arithmetic flags (OF, SF, AF, PF, CF) are cleared to 0.
Intel C/C++ Compiler Intrinsic Equivalent
AESENCWIDE256KL
unsigned char _mm_aesencwide256kl_u8(__m128i odata[8], const __m128i idata[8], const void* h);
Exceptions (All Operating Modes)
#UD
If the LOCK prefix is used.
If CPUID.07H:ECX.KL [bit 23] = 0.
If CR4.KL = 0.
If CPUID.19H:EBX.AESKLE [bit 0] = 0.
If CR0.EM = 1.
If CR4.OSFXSR = 0.
If CPUID.19H:EBX.WIDE_KL [bit 2] = 0.
#NM
If CR0.TS = 1.
#PF
If a page fault occurs.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
If the memory address is in a non-canonical form.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
If a memory address referencing the SS segment is in a non-canonical form.
3-74
Vol. 2A
AESENCWIDE256KL—Perform 14 Rounds of AES Encryption Flow With Key Locker on 8 Blocks Using 256-Bit Key
INSTRUCTION SET REFERENCE, A-L
AESIMC—Perform the AES InvMixColumn Transformation
Opcode/
Op/
64/32-bit
CPUID
Description
Instruction
En
Mode
Feature
Flag
66 0F 38 DB /r
RM
V/V
AES
Perform the InvMixColumn transformation on
AESIMC xmm1, xmm2/m128
a 128-bit round key from xmm2/m128 and
store the result in xmm1.
VEX.128.66.0F38.WIG DB /r
RM
V/V
Both AES
Perform the InvMixColumn transformation on
VAESIMC xmm1, xmm2/m128
and
a 128-bit round key from xmm2/m128 and
AVX flags
store the result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
N/A
N/A
Description
Perform the InvMixColumns transformation on the source operand and store the result in the destination operand.
The destination operand is an XMM register. The source operand can be an XMM register or a 128-bit memory loca-
tion.
Note: the AESIMC instruction should be applied to the expanded AES round keys (except for the first and last round
key) in order to prepare them for decryption using the “Equivalent Inverse Cipher” (defined in FIPS 197).
128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: Bits (MAXVL-1:128) of the destination YMM register are zeroed.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
AESIMC
DEST[127:0] := InvMixColumns( SRC );
DEST[MAXVL-1:128] (Unmodified)
VAESIMC
DEST[127:0] := InvMixColumns( SRC );
DEST[MAXVL-1:128] := 0;
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESIMC:
__m128i _mm_aesimc (__m128i)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-21, “Type 4 Class Exception Conditions”; additionally:
#UD
If VEX.vvvv ≠ 1111B.
AESIMC—Perform the AES InvMixColumn Transformation
Vol. 2A
3-75
INSTRUCTION SET REFERENCE, A-L
AESKEYGENASSIST—AES Round Key Generation Assist
Opcode/
Op/
64/32-bit
CPUID
Description
Instruction
En
Mode
Feature
Flag
66 0F 3A DF /r ib
RMI
V/V
AES
Assist in AES round key generation using an 8
AESKEYGENASSIST xmm1, xmm2/m128, imm8
bits Round Constant (RCON) specified in the
immediate byte, operating on 128 bits of data
specified in xmm2/m128 and stores the
result in xmm1.
VEX.128.66.0F3A.WIG DF /r ib
RMI
V/V
Both AES
Assist in AES round key generation using 8
VAESKEYGENASSIST xmm1, xmm2/m128, imm8
and
bits Round Constant (RCON) specified in the
AVX flags
immediate byte, operating on 128 bits of data
specified in xmm2/m128 and stores the
result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (w)
ModRM:r/m (r)
imm8
N/A
Description
Assist in expanding the AES cipher key, by computing steps towards generating a round key for encryption, using
128-bit data specified in the source operand and an 8-bit round constant specified as an immediate, store the result
in the destination operand.
The destination operand is an XMM register. The source operand can be an XMM register or a 128-bit memory loca-
tion.
128-bit Legacy SSE version: Bits (MAXVL-1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: Bits (MAXVL-1:128) of the destination YMM register are zeroed.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
AESKEYGENASSIST
X3[31:0] := SRC [127: 96];
X2[31:0] := SRC [95: 64];
X1[31:0] := SRC [63: 32];
X0[31:0] := SRC [31: 0];
RCON[31:0] := ZeroExtend(imm8[7:0]);
DEST[31:0] := SubWord(X1);
DEST[63:32 ] := RotWord( SubWord(X1) ) XOR RCON;
DEST[95:64] := SubWord(X3);
DEST[127:96] := RotWord( SubWord(X3) ) XOR RCON;
DEST[MAXVL-1:128] (Unmodified)
3-76
Vol. 2A
AESKEYGENASSIST—AES Round Key Generation Assist
INSTRUCTION SET REFERENCE, A-L
VAESKEYGENASSIST
X3[31:0] := SRC [127: 96];
X2[31:0] := SRC [95: 64];
X1[31:0] := SRC [63: 32];
X0[31:0] := SRC [31: 0];
RCON[31:0] := ZeroExtend(imm8[7:0]);
DEST[31:0] := SubWord(X1);
DEST[63:32 ] := RotWord( SubWord(X1) ) XOR RCON;
DEST[95:64] := SubWord(X3);
DEST[127:96] := RotWord( SubWord(X3) ) XOR RCON;
DEST[MAXVL-1:128] := 0;
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESKEYGENASSIST:
__m128i _mm_aeskeygenassist (__m128i, const int)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-21, “Type 4 Class Exception Conditions”; additionally:
#UD
If VEX.vvvv ≠ 1111B.
AESKEYGENASSIST—AES Round Key Generation Assist
Vol. 2A
3-77
INSTRUCTION SET REFERENCE, A-L
AND—Logical AND
Opcode
Instruction
Op/
64-bit
Compat/
Description
En
Mode
Leg Mode
24 ib
AND AL, imm8
I
Valid
Valid
AL AND imm8.
25 iw
AND AX, imm16
I
Valid
Valid
AX AND imm16.
25 id
AND EAX, imm32
I
Valid
Valid
EAX AND imm32.
REX.W + 25 id
AND RAX, imm32
I
Valid
N.E.
RAX AND imm32 sign-extended to 64-bits.
80 /4 ib
AND r/m8, imm8
MI
Valid
Valid
r/m8 AND imm8.
REX + 80 /4 ib
AND r/m8*, imm8
MI
Valid
N.E.
r/m8 AND imm8.
81 /4 iw
AND r/m16, imm16
MI
Valid
Valid
r/m16 AND imm16.
81 /4 id
AND r/m32, imm32
MI
Valid
Valid
r/m32 AND imm32.
REX.W + 81 /4 id
AND r/m64, imm32
MI
Valid
N.E.
r/m64 AND imm32 sign extended to 64-bits.
83 /4 ib
AND r/m16, imm8
MI
Valid
Valid
r/m16 AND imm8 (sign-extended).
83 /4 ib
AND r/m32, imm8
MI
Valid
Valid
r/m32 AND imm8 (sign-extended).
REX.W + 83 /4 ib
AND r/m64, imm8
MI
Valid
N.E.
r/m64 AND imm8 (sign-extended).
20 /r
AND r/m8, r8
MR
Valid
Valid
r/m8 AND r8.
REX + 20 /r
AND r/m8*, r8*
MR
Valid
N.E.
r/m64 AND r8 (sign-extended).
21 /r
AND r/m16, r16
MR
Valid
Valid
r/m16 AND r16.
21 /r
AND r/m32, r32
MR
Valid
Valid
r/m32 AND r32.
REX.W + 21 /r
AND r/m64, r64
MR
Valid
N.E.
r/m64 AND r32.
22 /r
AND r8, r/m8
RM
Valid
Valid
r8 AND r/m8.
REX + 22 /r
AND r8*, r/m8*
RM
Valid
N.E.
r/m64 AND r8 (sign-extended).
23 /r
AND r16, r/m16
RM
Valid
Valid
r16 AND r/m16.
23 /r
AND r32, r/m32
RM
Valid
Valid
r32 AND r/m32.
REX.W + 23 /r
AND r64, r/m64
RM
Valid
N.E.
r64 AND r/m64.
NOTES:
*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
MR
ModRM:r/m (r, w)
ModRM:reg (r)
N/A
N/A
MI
ModRM:r/m (r, w)
imm8/16/32
N/A
N/A
I
AL/AX/EAX/RAX
imm8/16/32
N/A
N/A
Description
Performs a bitwise AND operation on the destination (first) and source (second) operands and stores the result in
the destination operand location. The source operand can be an immediate, a register, or a memory location; the
destination operand can be a register or a memory location. (However, two memory operands cannot be used in
one instruction.) Each bit of the result is set to 1 if both corresponding bits of the first and second operands are 1;
otherwise, it is set to 0.
This instruction can be used with a LOCK prefix to allow the it to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
3-78
Vol. 2A
AND—Logical AND
INSTRUCTION SET REFERENCE, A-L
Operation
DEST := DEST AND SRC;
Flags Affected
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is
undefined.
Protected Mode Exceptions
#GP(0)
If the destination operand points to a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
AND—Logical AND
Vol. 2A
3-79
INSTRUCTION SET REFERENCE, A-L
ANDN—Logical AND NOT
Opcode/Instruction
Op/
64/32
CPUID
Description
En
-bit
Feature
Mode
Flag
VEX.LZ.0F38.W0 F2 /r
RVM
V/V
BMI1
Bitwise AND of inverted r32b with r/m32, store result in r32a.
ANDN r32a, r32b, r/m32
VEX.LZ. 0F38.W1 F2 /r
RVM
V/NE
BMI1
Bitwise AND of inverted r64b with r/m64, store result in r64a.
ANDN r64a, r64b, r/m64
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Performs a bitwise logical AND of inverted second operand (the first source operand) with the third operand (the
second source operand). The result is stored in the first operand (destination operand).
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt
to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
DEST := (NOT SRC1) bitwiseAND SRC2;
SF := DEST[OperandSize -1];
ZF := (DEST = 0);
Flags Affected
SF and ZF are updated based on result. OF and CF flags are cleared. AF and PF flags are undefined.
Intel C/C++ Compiler Intrinsic Equivalent
Auto-generated from high-level language.
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 2-29, “Type 13 Class Exception Conditions”.
3-80
Vol. 2A
ANDN—Logical AND NOT
INSTRUCTION SET REFERENCE, A-L
ANDPD—Bitwise Logical AND of Packed Double Precision Floating-Point Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
66 0F 54 /r
A
V/V
SSE2
Return the bitwise logical AND of packed double
ANDPD xmm1, xmm2/m128
precision floating-point values in xmm1 and xmm2/mem.
VEX.128.66.0F 54 /r
B
V/V
AVX
Return the bitwise logical AND of packed double
VANDPD xmm1, xmm2,
precision floating-point values in xmm2 and xmm3/mem.
xmm3/m128
VEX.256.66.0F 54 /r
B
V/V
AVX
Return the bitwise logical AND of packed double
VANDPD ymm1, ymm2,
precision floating-point values in ymm2 and ymm3/mem.
ymm3/m256
EVEX.128.66.0F.W1 54 /r
C
V/V
AVX512VL
Return the bitwise logical AND of packed double
VANDPD xmm1 {k1}{z}, xmm2,
AVX512DQ
precision floating-point values in xmm2 and
xmm3/m128/m64bcst
xmm3/m128/m64bcst subject to writemask k1.
EVEX.256.66.0F.W1 54 /r
C
V/V
AVX512VL
Return the bitwise logical AND of packed double
VANDPD ymm1 {k1}{z}, ymm2,
AVX512DQ
precision floating-point values in ymm2 and
ymm3/m256/m64bcst
ymm3/m256/m64bcst subject to writemask k1.
EVEX.512.66.0F.W1 54 /r
C
V/V
AVX512DQ
Return the bitwise logical AND of packed double
VANDPD zmm1 {k1}{z}, zmm2,
precision floating-point values in zmm2 and
zmm3/m512/m64bcst
zmm3/m512/m64bcst subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Performs a bitwise logical AND of the two, four or eight packed double precision floating-point values from the first
source operand and the second source operand, and stores the result in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a
64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of
the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding
register destination are unmodified.
ANDPD—Bitwise Logical AND of Packed Double Precision Floating-Point Values
Vol. 2A
3-81
INSTRUCTION SET REFERENCE, A-L
Operation
VANDPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i] := SRC1[i+63:i] BITWISE AND SRC2[63:0]
ELSE
DEST[i+63:i] := SRC1[i+63:i] BITWISE AND SRC2[i+63:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] = 0
FI;
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VANDPD (VEX.256 encoded version)
DEST[63:0] := SRC1[63:0] BITWISE AND SRC2[63:0]
DEST[127:64] := SRC1[127:64] BITWISE AND SRC2[127:64]
DEST[191:128] := SRC1[191:128] BITWISE AND SRC2[191:128]
DEST[255:192] := SRC1[255:192] BITWISE AND SRC2[255:192]
DEST[MAXVL-1:256] := 0
VANDPD (VEX.128 encoded version)
DEST[63:0] := SRC1[63:0] BITWISE AND SRC2[63:0]
DEST[127:64] := SRC1[127:64] BITWISE AND SRC2[127:64]
DEST[MAXVL-1:128] := 0
ANDPD (128-bit Legacy SSE version)
DEST[63:0] := DEST[63:0] BITWISE AND SRC[63:0]
DEST[127:64] := DEST[127:64] BITWISE AND SRC[127:64]
DEST[MAXVL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VANDPD __m512d _mm512_and_pd (__m512d a, __m512d b);
VANDPD __m512d _mm512_mask_and_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);
VANDPD __m512d _mm512_maskz_and_pd (__mmask8 k, __m512d a, __m512d b);
VANDPD __m256d _mm256_mask_and_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);
VANDPD __m256d _mm256_maskz_and_pd (__mmask8 k, __m256d a, __m256d b);
VANDPD __m128d _mm_mask_and_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);
VANDPD __m128d _mm_maskz_and_pd (__mmask8 k, __m128d a, __m128d b);
VANDPD __m256d _mm256_and_pd (__m256d a, __m256d b);
ANDPD __m128d _mm_and_pd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
None
3-82
Vol. 2A
ANDPD—Bitwise Logical AND of Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Other Exceptions
VEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions”.
ANDPD—Bitwise Logical AND of Packed Double Precision Floating-Point Values
Vol. 2A
3-83
INSTRUCTION SET REFERENCE, A-L
ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
NP 0F 54 /r
A
V/V
SSE
Return the bitwise logical AND of packed single precision
ANDPS xmm1, xmm2/m128
floating-point values in xmm1 and xmm2/mem.
VEX.128.0F 54 /r
B
V/V
AVX
Return the bitwise logical AND of packed single precision
VANDPS xmm1,xmm2,
floating-point values in xmm2 and xmm3/mem.
xmm3/m128
VEX.256.0F 54 /r
B
V/V
AVX
Return the bitwise logical AND of packed single precision
VANDPS ymm1, ymm2,
floating-point values in ymm2 and ymm3/mem.
ymm3/m256
EVEX.128.0F.W0 54 /r
C
V/V
AVX512VL
Return the bitwise logical AND of packed single precision
VANDPS xmm1 {k1}{z}, xmm2,
AVX512DQ
floating-point values in xmm2 and xmm3/m128/m32bcst
xmm3/m128/m32bcst
subject to writemask k1.
EVEX.256.0F.W0 54 /r
C
V/V
AVX512VL
Return the bitwise logical AND of packed single precision
VANDPS ymm1 {k1}{z}, ymm2,
AVX512DQ
floating-point values in ymm2 and ymm3/m256/m32bcst
ymm3/m256/m32bcst
subject to writemask k1.
EVEX.512.0F.W0 54 /r
C
V/V
AVX512DQ
Return the bitwise logical AND of packed single precision
VANDPS zmm1 {k1}{z}, zmm2,
floating-point values in zmm2 and zmm3/m512/m32bcst
zmm3/m512/m32bcst
subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Performs a bitwise logical AND of the four, eight or sixteen packed single precision floating-point values from the
first source operand and the second source operand, and stores the result in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a
32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of
the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding
ZMM register destination are unmodified.
3-84
Vol. 2A
ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Operation
VANDPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j := 0 TO KL-1
i := j * 32
IF k1[j] OR *no writemask*
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i] := SRC1[i+31:i] BITWISE AND SRC2[31:0]
ELSE
DEST[i+31:i] := SRC1[i+31:i] BITWISE AND SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] := 0
FI;
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0;
VANDPS (VEX.256 encoded version)
DEST[31:0] := SRC1[31:0] BITWISE AND SRC2[31:0]
DEST[63:32] := SRC1[63:32] BITWISE AND SRC2[63:32]
DEST[95:64] := SRC1[95:64] BITWISE AND SRC2[95:64]
DEST[127:96] := SRC1[127:96] BITWISE AND SRC2[127:96]
DEST[159:128] := SRC1[159:128] BITWISE AND SRC2[159:128]
DEST[191:160] := SRC1[191:160] BITWISE AND SRC2[191:160]
DEST[223:192] := SRC1[223:192] BITWISE AND SRC2[223:192]
DEST[255:224] := SRC1[255:224] BITWISE AND SRC2[255:224].
DEST[MAXVL-1:256] := 0;
VANDPS (VEX.128 encoded version)
DEST[31:0] := SRC1[31:0] BITWISE AND SRC2[31:0]
DEST[63:32] := SRC1[63:32] BITWISE AND SRC2[63:32]
DEST[95:64] := SRC1[95:64] BITWISE AND SRC2[95:64]
DEST[127:96] := SRC1[127:96] BITWISE AND SRC2[127:96]
DEST[MAXVL-1:128] := 0;
ANDPS (128-bit Legacy SSE version)
DEST[31:0] := DEST[31:0] BITWISE AND SRC[31:0]
DEST[63:32] := DEST[63:32] BITWISE AND SRC[63:32]
DEST[95:64] := DEST[95:64] BITWISE AND SRC[95:64]
DEST[127:96] := DEST[127:96] BITWISE AND SRC[127:96]
DEST[MAXVL-1:128] (Unmodified)
ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point Values
Vol. 2A
3-85
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
VANDPS __m512 _mm512_and_ps (__m512 a, __m512 b);
VANDPS __m512 _mm512_mask_and_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);
VANDPS __m512 _mm512_maskz_and_ps (__mmask16 k, __m512 a, __m512 b);
VANDPS __m256 _mm256_mask_and_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);
VANDPS __m256 _mm256_maskz_and_ps (__mmask8 k, __m256 a, __m256 b);
VANDPS __m128 _mm_mask_and_ps (__m128 s, __mmask8 k, __m128 a, __m128 b);
VANDPS __m128 _mm_maskz_and_ps (__mmask8 k, __m128 a, __m128 b);
VANDPS __m256 _mm256_and_ps (__m256 a, __m256 b);
ANDPS __m128 _mm_and_ps (__m128 a, __m128 b);
SIMD Floating-Point Exceptions
None
Other Exceptions
VEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions”.
3-86
Vol. 2A
ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
66 0F 55 /r
A
V/V
SSE2
Return the bitwise logical AND NOT of packed double
ANDNPD xmm1, xmm2/m128
precision floating-point values in xmm1 and xmm2/mem.
VEX.128.66.0F 55 /r
B
V/V
AVX
Return the bitwise logical AND NOT of packed double
VANDNPD xmm1, xmm2,
precision floating-point values in xmm2 and xmm3/mem.
xmm3/m128
VEX.256.66.0F 55/r
B
V/V
AVX
Return the bitwise logical AND NOT of packed double
VANDNPD ymm1, ymm2,
precision floating-point values in ymm2 and ymm3/mem.
ymm3/m256
EVEX.128.66.0F.W1 55 /r
C
V/V
AVX512VL
Return the bitwise logical AND NOT of packed double
VANDNPD xmm1 {k1}{z}, xmm2,
AVX512DQ
precision floating-point values in xmm2 and
xmm3/m128/m64bcst
xmm3/m128/m64bcst subject to writemask k1.
EVEX.256.66.0F.W1 55 /r
C
V/V
AVX512VL
Return the bitwise logical AND NOT of packed double
VANDNPD ymm1 {k1}{z}, ymm2,
AVX512DQ
precision floating-point values in ymm2 and
ymm3/m256/m64bcst
ymm3/m256/m64bcst subject to writemask k1.
EVEX.512.66.0F.W1 55 /r
C
V/V
AVX512DQ
Return the bitwise logical AND NOT of packed double
VANDNPD zmm1 {k1}{z}, zmm2,
precision floating-point values in zmm2 and
zmm3/m512/m64bcst
zmm3/m512/m64bcst subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Performs a bitwise logical AND NOT of the two, four or eight packed double precision floating-point values from the
first source operand and the second source operand, and stores the result in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a
64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of
the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding
register destination are unmodified.
ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values
Vol. 2A
3-87
INSTRUCTION SET REFERENCE, A-L
Operation
VANDNPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
i := j * 64
IF k1[j] OR *no writemask*
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i] := (NOT(SRC1[i+63:i])) BITWISE AND SRC2[63:0]
ELSE
DEST[i+63:i] := (NOT(SRC1[i+63:i])) BITWISE AND SRC2[i+63:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] = 0
FI;
FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
VANDNPD (VEX.256 encoded version)
DEST[63:0] := (NOT(SRC1[63:0])) BITWISE AND SRC2[63:0]
DEST[127:64] := (NOT(SRC1[127:64])) BITWISE AND SRC2[127:64]
DEST[191:128] := (NOT(SRC1[191:128])) BITWISE AND SRC2[191:128]
DEST[255:192] := (NOT(SRC1[255:192])) BITWISE AND SRC2[255:192]
DEST[MAXVL-1:256] := 0
VANDNPD (VEX.128 encoded version)
DEST[63:0] := (NOT(SRC1[63:0])) BITWISE AND SRC2[63:0]
DEST[127:64] := (NOT(SRC1[127:64])) BITWISE AND SRC2[127:64]
DEST[MAXVL-1:128] := 0
ANDNPD (128-bit Legacy SSE version)
DEST[63:0] := (NOT(DEST[63:0])) BITWISE AND SRC[63:0]
DEST[127:64] := (NOT(DEST[127:64])) BITWISE AND SRC[127:64]
DEST[MAXVL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VANDNPD __m512d _mm512_andnot_pd (__m512d a, __m512d b);
VANDNPD __m512d _mm512_mask_andnot_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);
VANDNPD __m512d _mm512_maskz_andnot_pd (__mmask8 k, __m512d a, __m512d b);
VANDNPD __m256d _mm256_mask_andnot_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);
VANDNPD __m256d _mm256_maskz_andnot_pd (__mmask8 k, __m256d a, __m256d b);
VANDNPD __m128d _mm_mask_andnot_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);
VANDNPD __m128d _mm_maskz_andnot_pd (__mmask8 k, __m128d a, __m128d b);
VANDNPD __m256d _mm256_andnot_pd (__m256d a, __m256d b);
ANDNPD __m128d _mm_andnot_pd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
None
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ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Other Exceptions
VEX-encoded instruction, see Table 2-21, “Type 4 Class Exception Conditions”.
EVEX-encoded instruction, see Table 2-49, “Type E4 Class Exception Conditions”.
ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values
Vol. 2A
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INSTRUCTION SET REFERENCE, A-L
ANDNPS—Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values
Opcode/
Op /
64/32
CPUID
Description
Instruction
En
bit Mode
Feature
Support
Flag
NP 0F 55 /r
A
V/V
SSE
Return the bitwise logical AND NOT of packed single precision
ANDNPS xmm1, xmm2/m128
floating-point values in xmm1 and xmm2/mem.
VEX.128.0F 55 /r
B
V/V
AVX
Return the bitwise logical AND NOT of packed single precision
VANDNPS xmm1, xmm2,
floating-point values in xmm2 and xmm3/mem.
xmm3/m128
VEX.256.0F 55 /r
B
V/V
AVX
Return the bitwise logical AND NOT of packed single precision
VANDNPS ymm1, ymm2,
floating-point values in ymm2 and ymm3/mem.
ymm3/m256
EVEX.128.0F.W0 55 /r
C
V/V
AVX512VL
Return the bitwise logical AND of packed single precision
VANDNPS xmm1 {k1}{z},
AVX512DQ
floating-point values in xmm2 and xmm3/m128/m32bcst
xmm2, xmm3/m128/m32bcst
subject to writemask k1.
EVEX.256.0F.W0 55 /r
C
V/V
AVX512VL
Return the bitwise logical AND of packed single precision
VANDNPS ymm1 {k1}{z},
AVX512DQ
floating-point values in ymm2 and ymm3/m256/m32bcst
ymm2, ymm3/m256/m32bcst
subject to writemask k1.
EVEX.512.0F.W0 55 /r
C
V/V
AVX512DQ
Return the bitwise logical AND of packed single precision
VANDNPS zmm1 {k1}{z},
floating-point values in zmm2 and zmm3/m512/m32bcst
zmm2, zmm3/m512/m32bcst
subject to writemask k1.
Instruction Operand Encoding
Op/En
Tuple Type
Operand 1
Operand 2
Operand 3
Operand 4
A
N/A
ModRM:reg (r, w)
ModRM:r/m (r)
N/A
N/A
B
N/A
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
N/A
C
Full
ModRM:reg (w)
EVEX.vvvv (r)
ModRM:r/m (r)
N/A
Description
Performs a bitwise logical AND NOT of the four, eight or sixteen packed single precision floating-point values from
the first source operand and the second source operand, and stores the result in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a
32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAXVL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAXVL-1:128) of
the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding
ZMM register destination are unmodified.
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