Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023)

INSTRUCTION SET REFERENCE, A-L

CVTTSD2SI-Convert With Truncation Scalar Double Precision Floating-Point Value to Signed

Integer

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F2 0F 2C /r

V/V

SSE2

Convert one double precision floating-point value from

CVTTSD2SI r32, xmm1/m64

xmm1/m64 to one signed doubleword integer in r32

using truncation.

F2 REX.W 0F 2C /r

V/N.E.

SSE2

Convert one double precision floating-point value from

CVTTSD2SI r64, xmm1/m64

xmm1/m64 to one signed quadword integer in r64

using truncation.

VEX.LIG.F2.0F.W0 2C /r ¹

V/V

AVX

Convert one double precision floating-point value from

VCVTTSD2SI r32, xmm1/m64

xmm1/m64 to one signed doubleword integer in r32

using truncation.

VEX.LIG.F2.0F.W1 2C /r ¹

V/N.E.²

AVX

Convert one double precision floating-point value from

VCVTTSD2SI r64, xmm1/m64

xmm1/m64 to one signed quadword integer in r64

using truncation.

EVEX.LLIG.F2.0F.W0 2C /r

V/V

AVX512F

Convert one double precision floating-point value from

VCVTTSD2SI r32, xmm1/m64{sae}

xmm1/m64 to one signed doubleword integer in r32

using truncation.

EVEX.LLIG.F2.0F.W1 2C /r

V/N.E.²

AVX512F

Convert one double precision floating-point value from

VCVTTSD2SI r64, xmm1/m64{sae}

xmm1/m64 to one signed quadword integer in r64

using truncation.

NOTES:

1. Software should ensure VCVTTSD2SI is encoded with VEX.L=0. Encoding VCVTTSD2SI with VEX.L=1 may encounter unpredictable

behavior across different processor generations.

2. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Tuple1 Fixed

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts a double precision floating-point value in the source operand (the second operand) to a signed double-

word integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand).

The source operand can be an XMM register or a 64-bit memory location. The destination operand is a general

purpose register. When the source operand is an XMM register, the double precision floating-point value is

contained in the low quadword of the register.

When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR

If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode

with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the

indefinite integer value (80000000H) is returned.

If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and

REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the

indefinite integer value (80000000_00000000H) is returned.

Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See

the summary chart at the beginning of this section for encoding data and limits.

VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.

CVTTSD2SI-Convert With Truncation Scalar Double Precision Floating-Point Value to Signed Integer

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INSTRUCTION SET REFERENCE, A-L

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

Software should ensure VCVTTSD2SI is encoded with VEX.L=0. Encoding VCVTTSD2SI with VEX.L=1 may

encounter unpredictable behavior across different processor generations.

Operation

(V)CVTTSD2SI (All Versions)

IF 64-Bit Mode and OperandSize = 64

THEN

DEST[63:0] := Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]);

ELSE

DEST[31:0] := Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]);

FI;

Intel C/C++ Compiler Intrinsic Equivalent

VCVTTSD2SI int _mm_cvttsd_i32( __m128d a);

VCVTTSD2SI int _mm_cvtt_roundsd_i32( __m128d a, int sae);

VCVTTSD2SI __int64 _mm_cvttsd_i64( __m128d a);

VCVTTSD2SI __int64 _mm_cvtt_roundsd_i64( __m128d a, int sae);

CVTTSD2SI int _mm_cvttsd_si32( __m128d a);

CVTTSD2SI __int64 _mm_cvttsd_si64( __m128d a);

SIMD Floating-Point Exceptions

Invalid, Precision.

Other Exceptions

VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions,” additionally:

#UD

If VEX.vvvv != 1111B.

EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”

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CVTTSD2SI-Convert With Truncation Scalar Double Precision Floating-Point Value to Signed Integer

INSTRUCTION SET REFERENCE, A-L

CVTTSS2SI-Convert With Truncation Scalar Single Precision Floating-Point Value to Integer

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F3 0F 2C /r

V/V

SSE

Convert one single precision floating-point value from

CVTTSS2SI r32, xmm1/m32

xmm1/m32 to one signed doubleword integer in r32

using truncation.

F3 REX.W 0F 2C /r

V/N.E.

SSE

Convert one single precision floating-point value from

CVTTSS2SI r64, xmm1/m32

xmm1/m32 to one signed quadword integer in r64

using truncation.

VEX.LIG.F3.0F.W0 2C /r ¹

V/V

AVX

Convert one single precision floating-point value from

VCVTTSS2SI r32, xmm1/m32

xmm1/m32 to one signed doubleword integer in r32

using truncation.

VEX.LIG.F3.0F.W1 2C /r ¹

V/N.E.²

AVX

Convert one single precision floating-point value from

VCVTTSS2SI r64, xmm1/m32

xmm1/m32 to one signed quadword integer in r64

using truncation.

EVEX.LLIG.F3.0F.W0 2C /r

V/V

AVX512F

Convert one single precision floating-point value from

VCVTTSS2SI r32, xmm1/m32{sae}

xmm1/m32 to one signed doubleword integer in r32

using truncation.

EVEX.LLIG.F3.0F.W1 2C /r

V/N.E.²

AVX512F

Convert one single precision floating-point value from

VCVTTSS2SI r64, xmm1/m32{sae}

xmm1/m32 to one signed quadword integer in r64

using truncation.

NOTES:

1. Software should ensure VCVTTSS2SI is encoded with VEX.L=0. Encoding VCVTTSS2SI with VEX.L=1 may encounter unpredictable

behavior across different processor generations.

2. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Tuple1 Fixed

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

Converts a single precision floating-point value in the source operand (the second operand) to a signed doubleword

integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The

source operand can be an XMM register or a 32-bit memory location. The destination operand is a general purpose

low doubleword of the register.

When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger

than the maximum signed doubleword integer, the floating-point invalid exception is raised. If this exception is

masked, the indefinite integer value (80000000H or 80000000_00000000H if operand size is 64 bits) is returned.

Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See

the summary chart at the beginning of this section for encoding data and limits.

VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.

Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.

Software should ensure VCVTTSS2SI is encoded with VEX.L=0. Encoding VCVTTSS2SI with VEX.L=1 may

encounter unpredictable behavior across different processor generations.

CVTTSS2SI-Convert With Truncation Scalar Single Precision Floating-Point Value to Integer

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INSTRUCTION SET REFERENCE, A-L

Operation

(V)CVTTSS2SI (All Versions)

IF 64-Bit Mode and OperandSize = 64

THEN

DEST[63:0] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);

ELSE

DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);

FI;

Intel C/C++ Compiler Intrinsic Equivalent

VCVTTSS2SI int _mm_cvttss_i32( __m128 a);

VCVTTSS2SI int _mm_cvtt_roundss_i32( __m128 a, int sae);

VCVTTSS2SI __int64 _mm_cvttss_i64( __m128 a);

VCVTTSS2SI __int64 _mm_cvtt_roundss_i64( __m128 a, int sae);

CVTTSS2SI int _mm_cvttss_si32( __m128 a);

CVTTSS2SI __int64 _mm_cvttss_si64( __m128 a);

SIMD Floating-Point Exceptions

Invalid, Precision.

Other Exceptions

See Table 2-20, “Type 3 Class Exception Conditions,” additionally:

#UD

If VEX.vvvv != 1111B.

EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”

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CVTTSS2SI-Convert With Truncation Scalar Single Precision Floating-Point Value to Integer

INSTRUCTION SET REFERENCE, A-L

CWD/CDQ/CQO-Convert Word to Doubleword/Convert Doubleword to Quadword

Opcode

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

CWD

Valid

DX:AX := sign-extend of AX.

CDQ

Valid

EDX:EAX := sign-extend of EAX.

REX.W + 99

CQO

Valid

N.E.

RDX:RAX:= sign-extend of RAX.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

N/A

Description

Doubles the size of the operand in register AX, EAX, or RAX (depending on the operand size) by means of sign

extension and stores the result in registers DX:AX, EDX:EAX, or RDX:RAX, respectively. The CWD instruction

copies the sign (bit 15) of the value in the AX register into every bit position in the DX register. The CDQ instruction

copies the sign (bit 31) of the value in the EAX register into every bit position in the EDX register. The CQO instruc-

tion (available in 64-bit mode only) copies the sign (bit 63) of the value in the RAX register into every bit position

in the RDX register.

The CWD instruction can be used to produce a doubleword dividend from a word before word division. The CDQ

instruction can be used to produce a quadword dividend from a doubleword before doubleword division. The CQO

instruction can be used to produce a double quadword dividend from a quadword before a quadword division.

The CWD and CDQ mnemonics reference the same opcode. The CWD instruction is intended for use when the

operand-size attribute is 16 and the CDQ instruction for when the operand-size attribute is 32. Some assemblers

may force the operand size to 16 when CWD is used and to 32 when CDQ is used. Others may treat these

mnemonics as synonyms (CWD/CDQ) and use the current setting of the operand-size attribute to determine the

size of values to be converted, regardless of the mnemonic used.

In 64-bit mode, use of the REX.W prefix promotes operation to 64 bits. The CQO mnemonics reference the same

opcode as CWD/CDQ. See the summary chart at the beginning of this section for encoding data and limits.

Operation

IF OperandSize = 16 (* CWD instruction *)

THEN

DX := SignExtend(AX);

ELSE IF OperandSize = 32 (* CDQ instruction *)

EDX := SignExtend(EAX); FI;

ELSE IF 64-Bit Mode and OperandSize = 64 (* CQO instruction*)

RDX := SignExtend(RAX); FI;

FI;

Flags Affected

None.

Exceptions (All Operating Modes)

#UD

If the LOCK prefix is used.

CWD/CDQ/CQO-Convert Word to Doubleword/Convert Doubleword to Quadword

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INSTRUCTION SET REFERENCE, A-L

DAA-Decimal Adjust AL After Addition

Opcode

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

DAA

Invalid

Valid

Decimal adjust AL after addition.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

N/A

Description

Adjusts the sum of two packed BCD values to create a packed BCD result. The AL register is the implied source and

destination operand. The DAA instruction is only useful when it follows an ADD instruction that adds (binary addi-

tion) two 2-digit, packed BCD values and stores a byte result in the AL register. The DAA instruction then adjusts

the contents of the AL register to contain the correct 2-digit, packed BCD result. If a decimal carry is detected, the

CF and AF flags are set accordingly.

This instruction executes as described above in compatibility mode and legacy mode. It is not valid in 64-bit mode.

Operation

IF 64-Bit Mode

THEN

#UD;

ELSE

old_AL := AL;

old_CF := CF;

CF := 0;

IF (((AL AND 0FH) > 9) or AF = 1)

THEN

AL := AL + 6;

CF := old_CF or (Carry from AL := AL + 6);

AF := 1;

ELSE

AF := 0;

FI;

IF ((old_AL > 99H) or (old_CF = 1))

THEN

AL := AL + 60H;

CF := 1;

ELSE

CF := 0;

FI;

Example

ADD AL, BL Before: AL=79H BL=35H EFLAGS(OSZAPC)=XXXXXX

After: AL=AEH BL=35H EFLAGS(0SZAPC)=110000

DAA

Before: AL=AEH BL=35H EFLAGS(OSZAPC)=110000

After: AL=14H BL=35H EFLAGS(0SZAPC)=X00111

DAA

Before: AL=2EH BL=35H EFLAGS(OSZAPC)=110000

After: AL=34H BL=35H EFLAGS(0SZAPC)=X00101

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DAA-Decimal Adjust AL After Addition

INSTRUCTION SET REFERENCE, A-L

DAS-Decimal Adjust AL After Subtraction

Opcode

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

DAS

Invalid

Valid

Decimal adjust AL after subtraction.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

N/A

Description

Adjusts the result of the subtraction of two packed BCD values to create a packed BCD result. The AL register is the

implied source and destination operand. The DAS instruction is only useful when it follows a SUB instruction that

subtracts (binary subtraction) one 2-digit, packed BCD value from another and stores a byte result in the AL

result. If a decimal borrow is detected, the CF and AF flags are set accordingly.

This instruction executes as described above in compatibility mode and legacy mode. It is not valid in 64-bit mode.

Operation

IF 64-Bit Mode

THEN

#UD;

ELSE

old_AL := AL;

old_CF := CF;

CF := 0;

IF (((AL AND 0FH) > 9) or AF = 1)

THEN

AL := AL - 6;

CF := old_CF or (Borrow from AL := AL - 6);

AF := 1;

ELSE

AF := 0;

FI;

IF ((old_AL > 99H) or (old_CF = 1))

THEN

AL := AL - 60H;

CF := 1;

FI;

Example

SUB

AL, BL Before: AL = 35H, BL = 47H, EFLAGS(OSZAPC) = XXXXXX

After: AL = EEH, BL = 47H, EFLAGS(0SZAPC) = 010111

DAA

Before: AL = EEH, BL = 47H, EFLAGS(OSZAPC) = 010111

After: AL = 88H, BL = 47H, EFLAGS(0SZAPC) = X10111

Flags Affected

The CF and AF flags are set if the adjustment of the value results in a decimal borrow in either digit of the result

(see the “Operation” section above). The SF, ZF, and PF flags are set according to the result. The OF flag is unde-

fined.

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DAS-Decimal Adjust AL After Subtraction

INSTRUCTION SET REFERENCE, A-L

DEC-Decrement by 1

Opcode

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

FE /1

DEC r/m8

Valid

Decrement r/m8 by 1.

REX + FE /1

DEC r/m8^*

Valid

N.E.

Decrement r/m8 by 1.

FF /1

DEC r/m16

Valid

Decrement r/m16 by 1.

FF /1

DEC r/m32

Valid

Decrement r/m32 by 1.

REX.W + FF /1

DEC r/m64

Valid

N.E.

Decrement r/m64 by 1.

48+rw

DEC r16

N.E.

Valid

Decrement r16 by 1.

48+rd

DEC r32

N.E.

Valid

Decrement r32 by 1.

NOTES:

* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:r/m (r, w)

N/A

opcode + rd (r, w)

N/A

Description

Subtracts 1 from the destination operand, while preserving the state of the CF flag. The destination operand can be

a register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag.

(To perform a decrement operation that updates the CF flag, use a SUB instruction with an immediate operand of

1.)

This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.

In 64-bit mode, DEC r16 and DEC r32 are not encodable (because opcodes 48H through 4FH are REX prefixes).

Otherwise, the instruction’s 64-bit mode default operation size is 32 bits. Use of the REX.R prefix permits access to

additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.

See the summary chart at the beginning of this section for encoding data and limits.

Operation

DEST := DEST - 1;

Flags Affected

The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.

Protected Mode Exceptions

#GP(0)

If the destination operand is located in a non-writable segment.

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register contains a NULL segment selector.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

Real-Address Mode Exceptions

#GP

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

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DEC-Decrement by 1

INSTRUCTION SET REFERENCE, A-L

#SS

If a memory operand effective address is outside the SS segment limit.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

Virtual-8086 Mode Exceptions

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0)

If a memory address referencing the SS segment is in a non-canonical form.

#GP(0)

If the memory address is in a non-canonical form.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used but the destination is not a memory operand.

DEC-Decrement by 1

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INSTRUCTION SET REFERENCE, A-L

DIV-Unsigned Divide

Opcode

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

F6 /6

DIV r/m8

Valid

Unsigned divide AX by r/m8, with result

stored in AL := Quotient, AH := Remainder.

REX + F6 /6

DIV r/m8¹

Valid

N.E.

Unsigned divide AX by r/m8, with result

stored in AL := Quotient, AH := Remainder.

F7 /6

DIV r/m16

Valid

Unsigned divide DX:AX by r/m16, with result

stored in AX := Quotient, DX := Remainder.

F7 /6

DIV r/m32

Valid

Unsigned divide EDX:EAX by r/m32, with

result stored in EAX := Quotient, EDX :=

Remainder.

REX.W + F7 /6

DIV r/m64

Valid

N.E.

Unsigned divide RDX:RAX by r/m64, with

result stored in RAX := Quotient, RDX :=

Remainder.

NOTES:

1. In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

ModRM:r/m (w)

N/A

Description

Divides unsigned the value in the AX, DX:AX, EDX:EAX, or RDX:RAX registers (dividend) by the source operand

(divisor) and stores the result in the AX (AH:AL), DX:AX, EDX:EAX, or RDX:RAX registers. The source operand can

be a general-purpose register or a memory location. The action of this instruction depends on the operand size

(dividend/divisor). Division using 64-bit operand is available only in 64-bit mode.

Non-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magni-

tude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag.

In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to addi-

tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is

applied, the instruction divides the unsigned value in RDX:RAX by the source operand and stores the quotient in

RAX, the remainder in RDX.

See the summary chart at the beginning of this section for encoding data and limits. See Table 3-15.

Table 3-15. DIV Action

Maximum

Operand Size

Dividend

Divisor

Quotient

Remainder

Quotient

Word/byte

r/m8

255

Doubleword/word

DX:AX

r/m16

65,535

Quadword/doubleword

EDX:EAX

r/m32

EAX

EDX

2³² - 1

Doublequadword/

RDX:RAX

r/m64

RAX

RDX

2⁶⁴ - 1

quadword

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DIV-Unsigned Divide

INSTRUCTION SET REFERENCE, A-L

Operation

IF SRC = 0

THEN #DE; FI; (* Divide Error *)

IF OperandSize = 8 (* Word/Byte Operation *)

THEN

temp := AX / SRC;

IF temp > FFH

THEN #DE; (* Divide error *)

ELSE

AL := temp;

AH := AX MOD SRC;

FI;

ELSE IF OperandSize = 16 (* Doubleword/word operation *)

THEN

temp := DX:AX / SRC;

IF temp > FFFFH

THEN #DE; (* Divide error *)

ELSE

AX := temp;

DX := DX:AX MOD SRC;

FI;

ELSE IF Operandsize = 32 (* Quadword/doubleword operation *)

THEN

temp := EDX:EAX / SRC;

IF temp > FFFFFFFFH

THEN #DE; (* Divide error *)

ELSE

EAX := temp;

EDX := EDX:EAX MOD SRC;

FI;

ELSE IF 64-Bit Mode and Operandsize = 64 (* Doublequadword/quadword operation *)

THEN

temp := RDX:RAX / SRC;

IF temp > FFFFFFFFFFFFFFFFH

THEN #DE; (* Divide error *)

ELSE

RAX := temp;

RDX := RDX:RAX MOD SRC;

FI;

Flags Affected

The CF, OF, SF, ZF, AF, and PF flags are undefined.

DIV-Unsigned Divide

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INSTRUCTION SET REFERENCE, A-L

Protected Mode Exceptions

#DE

If the source operand (divisor) is 0

If the quotient is too large for the designated register.

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register contains a NULL segment selector.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

#DE

If the source operand (divisor) is 0.

If the quotient is too large for the designated register.

#GP

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register contains a NULL segment selector.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#UD

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#DE

If the source operand (divisor) is 0.

If the quotient is too large for the designated register.

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS

If a memory operand effective address is outside the SS segment limit.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made.

#UD

If the LOCK prefix is used.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0)

If a memory address referencing the SS segment is in a non-canonical form.

#GP(0)

If the memory address is in a non-canonical form.

#DE

If the source operand (divisor) is 0

If the quotient is too large for the designated register.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used.

3-324

Vol. 2A

DIV-Unsigned Divide

INSTRUCTION SET REFERENCE, A-L

DIVPD-Divide Packed Double Precision Floating-Point Values

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

66 0F 5E /r

V/V

SSE2

Divide packed double precision floating-point values in

DIVPD xmm1, xmm2/m128

xmm1 by packed double precision floating-point

values in xmm2/mem.

VEX.128.66.0F.WIG 5E /r

V/V

AVX

Divide packed double precision floating-point values in

VDIVPD xmm1, xmm2, xmm3/m128

xmm2 by packed double precision floating-point

values in xmm3/mem.

VEX.256.66.0F.WIG 5E /r

V/V

AVX

Divide packed double precision floating-point values in

VDIVPD ymm1, ymm2, ymm3/m256

ymm2 by packed double precision floating-point

values in ymm3/mem.

EVEX.128.66.0F.W1 5E /r

V/V

AVX512VL

Divide packed double precision floating-point values in

VDIVPD xmm1 {k1}{z}, xmm2,

AVX512F

xmm2 by packed double precision floating-point

xmm3/m128/m64bcst

values in xmm3/m128/m64bcst and write results to

xmm1 subject to writemask k1.

EVEX.256.66.0F.W1 5E /r

V/V

AVX512VL

Divide packed double precision floating-point values in

VDIVPD ymm1 {k1}{z}, ymm2,

AVX512F

ymm2 by packed double precision floating-point

ymm3/m256/m64bcst

values in ymm3/m256/m64bcst and write results to

ymm1 subject to writemask k1.

EVEX.512.66.0F.W1 5E /r

V/V

AVX512F

Divide packed double precision floating-point values in

VDIVPD zmm1 {k1}{z}, zmm2,

zmm2 by packed double precision floating-point values

zmm3/m512/m64bcst{er}

in zmm3/m512/m64bcst and write results to zmm1

subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a SIMD divide of the double precision floating-point values in the first source operand by the floating-

point values in the second source operand (the third operand). Results are written to the destination operand (the

first operand).

EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second

source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector

broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally

updated with writemask k1.

VEX.256 encoded version: The first source operand (the second operand) is a YMM register. The second source

operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper

bits (MAXVL-1:256) of the corresponding destination are zeroed.

VEX.128 encoded version: The first source operand (the second operand) is a XMM register. The second source

operand can be a XMM register or a 128-bit memory location. The destination operand is a XMM register. The upper

bits (MAXVL-1:128) of the corresponding destination are zeroed.

128-bit Legacy SSE version: The second source operand (the second operand) can be an XMM register or an 128-

bit memory location. The destination is the same as the first source operand. The upper bits (MAXVL-1:128) of the

corresponding destination are unmodified.

DIVPD-Divide Packed Double Precision Floating-Point Values

Vol. 2A

3-325

INSTRUCTION SET REFERENCE, A-L

Operation

VDIVPD (EVEX Encoded Versions)

(KL, VL) = (2, 128), (4, 256), (8, 512)

IF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC); ; refer to Table 15-4 in the Intel^® 64 and IA-32 Architectures

Software Developer’s Manual, Volume 1

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

FOR j := 0 TO KL-1

i := j * 64

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN

DEST[i+63:i] := SRC1[i+63:i] / SRC2[63:0]

ELSE

DEST[i+63:i] := SRC1[i+63:i] / SRC2[i+63:i]

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+63:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+63:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VDIVPD (VEX.256 Encoded Version)

DEST[63:0] := SRC1[63:0] / SRC2[63:0]

DEST[127:64] := SRC1[127:64] / SRC2[127:64]

DEST[191:128] := SRC1[191:128] / SRC2[191:128]

DEST[255:192] := SRC1[255:192] / SRC2[255:192]

DEST[MAXVL-1:256] := 0;

VDIVPD (VEX.128 Encoded Version)

DEST[63:0] := SRC1[63:0] / SRC2[63:0]

DEST[127:64] := SRC1[127:64] / SRC2[127:64]

DEST[MAXVL-1:128] := 0;

DIVPD (128-bit Legacy SSE Version)

DEST[63:0] := SRC1[63:0] / SRC2[63:0]

DEST[127:64] := SRC1[127:64] / SRC2[127:64]

DEST[MAXVL-1:128] (Unmodified)

3-326

Vol. 2A

DIVPD-Divide Packed Double Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-L

Intel C/C++ Compiler Intrinsic Equivalent

VDIVPD __m512d _mm512_div_pd( __m512d a, __m512d b);

VDIVPD __m512d _mm512_mask_div_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);

VDIVPD __m512d _mm512_maskz_div_pd( __mmask8 k, __m512d a, __m512d b);

VDIVPD __m256d _mm256_mask_div_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);

VDIVPD __m256d _mm256_maskz_div_pd( __mmask8 k, __m256d a, __m256d b);

VDIVPD __m128d _mm_mask_div_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);

VDIVPD __m128d _mm_maskz_div_pd( __mmask8 k, __m128d a, __m128d b);

VDIVPD __m512d _mm512_div_round_pd( __m512d a, __m512d b, int);

VDIVPD __m512d _mm512_mask_div_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);

VDIVPD __m512d _mm512_maskz_div_round_pd( __mmask8 k, __m512d a, __m512d b, int);

VDIVPD __m256d _mm256_div_pd (__m256d a, __m256d b);

DIVPD __m128d _mm_div_pd (__m128d a, __m128d b);

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.

Other Exceptions

VEX-encoded instructions, see Table 2-19, “Type 2 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”

DIVPD-Divide Packed Double Precision Floating-Point Values

Vol. 2A

3-327

INSTRUCTION SET REFERENCE, A-L

DIVPS-Divide Packed Single Precision Floating-Point Values

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

NP 0F 5E /r

V/V

SSE

Divide packed single precision floating-point values in

DIVPS xmm1, xmm2/m128

xmm1 by packed single precision floating-point values

in xmm2/mem.

VEX.128.0F.WIG 5E /r

V/V

AVX

Divide packed single precision floating-point values in

VDIVPS xmm1, xmm2, xmm3/m128

xmm2 by packed single precision floating-point values

in xmm3/mem.

VEX.256.0F.WIG 5E /r

V/V

AVX

Divide packed single precision floating-point values in

VDIVPS ymm1, ymm2, ymm3/m256

ymm2 by packed single precision floating-point values

in ymm3/mem.

EVEX.128.0F.W0 5E /r

V/V

AVX512VL

Divide packed single precision floating-point values in

VDIVPS xmm1 {k1}{z}, xmm2,

AVX512F

xmm2 by packed single precision floating-point values

xmm3/m128/m32bcst

in xmm3/m128/m32bcst and write results to xmm1

subject to writemask k1.

EVEX.256.0F.W0 5E /r

V/V

AVX512VL

Divide packed single precision floating-point values in

VDIVPS ymm1 {k1}{z}, ymm2,

AVX512F

ymm2 by packed single precision floating-point values

ymm3/m256/m32bcst

in ymm3/m256/m32bcst and write results to ymm1

subject to writemask k1.

EVEX.512.0F.W0 5E /r

V/V

AVX512F

Divide packed single precision floating-point values in

VDIVPS zmm1 {k1}{z}, zmm2,

zmm2 by packed single precision floating-point values

zmm3/m512/m32bcst{er}

in zmm3/m512/m32bcst and write results to zmm1

subject to writemask k1.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Full

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Performs a SIMD divide of the four, eight or sixteen packed single precision floating-point values in the first source

operand (the second operand) by the four, eight or sixteen packed single precision floating-point values in the

second source operand (the third operand). Results are written to the destination operand (the first operand).

EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second

source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector

broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally

updated with writemask k1.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM

VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM

the corresponding ZMM register destination are zeroed.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

ZMM register destination are unmodified.

3-328

Vol. 2A

DIVPS-Divide Packed Single Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-L

Operation

VDIVPS (EVEX Encoded Versions)

(KL, VL) = (4, 128), (8, 256), (16, 512)

IF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

FOR j := 0 TO KL-1

i := j * 32

IF k1[j] OR *no writemask*

THEN

IF (EVEX.b = 1) AND (SRC2 *is memory*)

THEN

DEST[i+31:i] := SRC1[i+31:i] / SRC2[31:0]

ELSE

DEST[i+31:i] := SRC1[i+31:i] / SRC2[i+31:i]

FI;

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[i+31:i] remains unchanged*

ELSE

; zeroing-masking

DEST[i+31:i] := 0

FI;

ENDFOR

DEST[MAXVL-1:VL] := 0

VDIVPS (VEX.256 Encoded Version)

DEST[31:0] := SRC1[31:0] / SRC2[31:0]

DEST[63:32] := SRC1[63:32] / SRC2[63:32]

DEST[95:64] := SRC1[95:64] / SRC2[95:64]

DEST[127:96] := SRC1[127:96] / SRC2[127:96]

DEST[159:128] := SRC1[159:128] / SRC2[159:128]

DEST[191:160] := SRC1[191:160] / SRC2[191:160]

DEST[223:192] := SRC1[223:192] / SRC2[223:192]

DEST[255:224] := SRC1[255:224] / SRC2[255:224].

DEST[MAXVL-1:256] := 0;

VDIVPS (VEX.128 Encoded Version)

DEST[31:0] := SRC1[31:0] / SRC2[31:0]

DEST[63:32] := SRC1[63:32] / SRC2[63:32]

DEST[95:64] := SRC1[95:64] / SRC2[95:64]

DEST[127:96] := SRC1[127:96] / SRC2[127:96]

DEST[MAXVL-1:128] := 0

DIVPS-Divide Packed Single Precision Floating-Point Values

Vol. 2A

3-329

INSTRUCTION SET REFERENCE, A-L

DIVPS (128-bit Legacy SSE Version)

DEST[31:0] := SRC1[31:0] / SRC2[31:0]

DEST[63:32] := SRC1[63:32] / SRC2[63:32]

DEST[95:64] := SRC1[95:64] / SRC2[95:64]

DEST[127:96] := SRC1[127:96] / SRC2[127:96]

DEST[MAXVL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VDIVPS __m512 _mm512_div_ps( __m512 a, __m512 b);

VDIVPS __m512 _mm512_mask_div_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);

VDIVPS __m512 _mm512_maskz_div_ps(__mmask16 k, __m512 a, __m512 b);

VDIVPD __m256d _mm256_mask_div_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);

VDIVPD __m256d _mm256_maskz_div_pd( __mmask8 k, __m256d a, __m256d b);

VDIVPD __m128d _mm_mask_div_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);

VDIVPD __m128d _mm_maskz_div_pd( __mmask8 k, __m128d a, __m128d b);

VDIVPS __m512 _mm512_div_round_ps( __m512 a, __m512 b, int);

VDIVPS __m512 _mm512_mask_div_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);

VDIVPS __m512 _mm512_maskz_div_round_ps(__mmask16 k, __m512 a, __m512 b, int);

VDIVPS __m256 _mm256_div_ps (__m256 a, __m256 b);

DIVPS __m128 _mm_div_ps (__m128 a, __m128 b);

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.

Other Exceptions

VEX-encoded instructions, see Table 2-19, “Type 2 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-46, “Type E2 Class Exception Conditions.”

3-330

Vol. 2A

DIVPS-Divide Packed Single Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-L

DIVSD-Divide Scalar Double Precision Floating-Point Value

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F2 0F 5E /r

V/V

SSE2

Divide low double precision floating-point value in

DIVSD xmm1, xmm2/m64

xmm1 by low double precision floating-point value in

xmm2/m64.

VEX.LIG.F2.0F.WIG 5E /r

V/V

AVX

Divide low double precision floating-point value in

VDIVSD xmm1, xmm2, xmm3/m64

xmm2 by low double precision floating-point value in

xmm3/m64.

EVEX.LLIG.F2.0F.W1 5E /r

V/V

AVX512F

Divide low double precision floating-point value in

VDIVSD xmm1 {k1}{z}, xmm2,

xmm2 by low double precision floating-point value in

xmm3/m64{er}

xmm3/m64.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Divides the low double precision floating-point value in the first source operand by the low double precision

floating-point value in the second source operand, and stores the double precision floating-point result in the desti-

nation operand. The second source operand can be an XMM register or a 64-bit memory location. The first source

and destination are XMM registers.

128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL-

1:64) of the corresponding ZMM destination register remain unchanged.

VEX.128 encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The quadword at bits

127:64 of the destination operand is copied from the corresponding quadword of the first source operand. Bits

(MAXVL-1:128) of the destination register are zeroed.

EVEX.128 encoded version: The first source operand is an xmm register encoded by EVEX.vvvv. The quadword

element of the destination operand at bits 127:64 are copied from the first source operand. Bits (MAXVL-1:128) of

the destination register are zeroed.

EVEX version: The low quadword element of the destination is updated according to the writemask.

Software should ensure VDIVSD is encoded with VEX.L=0. Encoding VDIVSD with VEX.L=1 may encounter unpre-

dictable behavior across different processor generations.

DIVSD-Divide Scalar Double Precision Floating-Point Value

Vol. 2A

3-331

INSTRUCTION SET REFERENCE, A-L

Operation

VDIVSD (EVEX Encoded Version)

IF (EVEX.b = 1) AND SRC2 *is a register*

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

IF k1[0] or *no writemask*

THEN

DEST[63:0] := SRC1[63:0] / SRC2[63:0]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[63:0] remains unchanged*

ELSE

; zeroing-masking

THEN DEST[63:0] := 0

FI;

DEST[127:64] := SRC1[127:64]

DEST[MAXVL-1:128] := 0

VDIVSD (VEX.128 Encoded Version)

DEST[63:0] := SRC1[63:0] / SRC2[63:0]

DEST[127:64] := SRC1[127:64]

DEST[MAXVL-1:128] := 0

DIVSD (128-bit Legacy SSE Version)

DEST[63:0] := DEST[63:0] / SRC[63:0]

DEST[MAXVL-1:64] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VDIVSD __m128d _mm_mask_div_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);

VDIVSD __m128d _mm_maskz_div_sd( __mmask8 k, __m128d a, __m128d b);

VDIVSD __m128d _mm_div_round_sd( __m128d a, __m128d b, int);

VDIVSD __m128d _mm_mask_div_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);

VDIVSD __m128d _mm_maskz_div_round_sd( __mmask8 k, __m128d a, __m128d b, int);

DIVSD __m128d _mm_div_sd (__m128d a, __m128d b);

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.

Other Exceptions

VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”

3-332

Vol. 2A

DIVSD-Divide Scalar Double Precision Floating-Point Value

INSTRUCTION SET REFERENCE, A-L

DIVSS-Divide Scalar Single Precision Floating-Point Values

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F3 0F 5E /r

V/V

SSE

Divide low single precision floating-point value in

DIVSS xmm1, xmm2/m32

xmm1 by low single precision floating-point value in

xmm2/m32.

VEX.LIG.F3.0F.WIG 5E /r

V/V

AVX

Divide low single precision floating-point value in

VDIVSS xmm1, xmm2, xmm3/m32

xmm2 by low single precision floating-point value in

xmm3/m32.

EVEX.LLIG.F3.0F.W0 5E /r

V/V

AVX512F

Divide low single precision floating-point value in

VDIVSS xmm1 {k1}{z}, xmm2,

xmm2 by low single precision floating-point value in

xmm3/m32{er}

xmm3/m32.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (r, w)

ModRM:r/m (r)

N/A

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

N/A

Tuple1 Scalar

ModRM:reg (w)

EVEX.vvvv (r)

ModRM:r/m (r)

N/A

Description

Divides the low single precision floating-point value in the first source operand by the low single precision floating-

point value in the second source operand, and stores the single precision floating-point result in the destination

operand. The second source operand can be an XMM register or a 32-bit memory location.

128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAXVL-

1:32) of the corresponding YMM destination register remain unchanged.

VEX.128 encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The three high-order

doublewords of the destination operand are copied from the first source operand. Bits (MAXVL-1:128) of the desti-

nation register are zeroed.

EVEX.128 encoded version: The first source operand is an xmm register encoded by EVEX.vvvv. The doubleword

elements of the destination operand at bits 127:32 are copied from the first source operand. Bits (MAXVL-1:128)

of the destination register are zeroed.

EVEX version: The low doubleword element of the destination is updated according to the writemask.

Software should ensure VDIVSS is encoded with VEX.L=0. Encoding VDIVSS with VEX.L=1 may encounter unpre-

dictable behavior across different processor generations.

DIVSS-Divide Scalar Single Precision Floating-Point Values

Vol. 2A

3-333

INSTRUCTION SET REFERENCE, A-L

Operation

VDIVSS (EVEX Encoded Version)

IF (EVEX.b = 1) AND SRC2 *is a register*

THEN

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(EVEX.RC);

ELSE

SET_ROUNDING_MODE_FOR_THIS_INSTRUCTION(MXCSR.RC);

FI;

IF k1[0] or *no writemask*

THEN

DEST[31:0] := SRC1[31:0] / SRC2[31:0]

ELSE

IF *merging-masking*

; merging-masking

THEN *DEST[31:0] remains unchanged*

ELSE

; zeroing-masking

THEN DEST[31:0] := 0

FI;

DEST[127:32] := SRC1[127:32]

DEST[MAXVL-1:128] := 0

VDIVSS (VEX.128 Encoded Version)

DEST[31:0] := SRC1[31:0] / SRC2[31:0]

DEST[127:32] := SRC1[127:32]

DEST[MAXVL-1:128] := 0

DIVSS (128-bit Legacy SSE Version)

DEST[31:0] := DEST[31:0] / SRC[31:0]

DEST[MAXVL-1:32] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VDIVSS __m128 _mm_mask_div_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);

VDIVSS __m128 _mm_maskz_div_ss( __mmask8 k, __m128 a, __m128 b);

VDIVSS __m128 _mm_div_round_ss( __m128 a, __m128 b, int);

VDIVSS __m128 _mm_mask_div_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);

VDIVSS __m128 _mm_maskz_div_round_ss( __mmask8 k, __m128 a, __m128 b, int);

DIVSS __m128 _mm_div_ss(__m128 a, __m128 b);

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.

Other Exceptions

VEX-encoded instructions, see Table 2-20, “Type 3 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-47, “Type E3 Class Exception Conditions.”

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INSTRUCTION SET REFERENCE, A-L

DPPD-Dot Product of Packed Double Precision Floating-Point Values

Opcode/

Op/

64/32-bit

CPUID

Description

Instruction

Mode

Feature

Flag

66 0F 3A 41 /r ib

RMI

V/V

SSE4_1

Selectively multiply packed double precision

floating-point values from xmm1 with packed

DPPD xmm1, xmm2/m128, imm8

double precision floating-point values from

xmm2, add and selectively store the packed

double precision floating-point values to

xmm1.

VEX.128.66.0F3A.WIG 41 /r ib

RVMI

V/V

AVX

Selectively multiply packed double precision

floating-point values from xmm2 with packed

VDPPD xmm1,xmm2, xmm3/m128, imm8

double precision floating-point values from

xmm3, add and selectively store the packed

double precision floating-point values to

xmm1.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RMI

ModRM:reg (r, w)

ModRM:r/m (r)

imm8

N/A

RVMI

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

Conditionally multiplies the packed double precision floating-point values in the destination operand (first operand)

with the packed double precision floating-point values in the source (second operand) depending on a mask

extracted from bits [5:4] of the immediate operand (third operand). If a condition mask bit is zero, the corre-

sponding multiplication is replaced by a value of 0.0 in the manner described by Section 12.8.4 of Intel^® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 1.

The two resulting double precision values are summed into an intermediate result. The intermediate result is condi-

tionally broadcasted to the destination using a broadcast mask specified by bits [1:0] of the immediate byte.

If a broadcast mask bit is “1”, the intermediate result is copied to the corresponding qword element in the destina-

tion operand. If a broadcast mask bit is zero, the corresponding element in the destination is set to zero.

DPPD follows the NaN forwarding rules stated in the Software Developer’s Manual, vol. 1, table 4.7. These rules do

not cover horizontal prioritization of NaNs. Horizontal propagation of NaNs to the destination and the positioning of

those NaNs in the destination is implementation dependent. NaNs on the input sources or computationally gener-

ated NaNs will have at least one NaN propagated to the destination.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

YMM register destination are unmodified.

VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are

zeroed.

If VDPPD is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an

#UD exception.

DPPD-Dot Product of Packed Double Precision Floating-Point Values

Vol. 2A

3-335

INSTRUCTION SET REFERENCE, A-L

Operation

DP_primitive (SRC1, SRC2)

IF (imm8[4] = 1)

THEN Temp1[63:0] := DEST[63:0] * SRC[63:0]; // update SIMD exception flags

ELSE Temp1[63:0] := +0.0; FI;

IF (imm8[5] = 1)

THEN Temp1[127:64] := DEST[127:64] * SRC[127:64]; // update SIMD exception flags

ELSE Temp1[127:64] := +0.0; FI;

/* if unmasked exception reported, execute exception handler*/

Temp2[63:0] := Temp1[63:0] + Temp1[127:64]; // update SIMD exception flags

/* if unmasked exception reported, execute exception handler*/

IF (imm8[0] = 1)

THEN DEST[63:0] := Temp2[63:0];

ELSE DEST[63:0] := +0.0; FI;

IF (imm8[1] = 1)

THEN DEST[127:64] := Temp2[63:0];

ELSE DEST[127:64] := +0.0; FI;

DPPD (128-bit Legacy SSE Version)

DEST[127:0] := DP_Primitive(SRC1[127:0], SRC2[127:0]);

DEST[MAXVL-1:128] (Unmodified)

VDPPD (VEX.128 Encoded Version)

DEST[127:0] := DP_Primitive(SRC1[127:0], SRC2[127:0]);

DEST[MAXVL-1:128] := 0

Flags Affected

None.

Intel C/C++ Compiler Intrinsic Equivalent

DPPD __m128d _mm_dp_pd ( __m128d a, __m128d b, const int mask);

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Precision, Denormal.

Exceptions are determined separately for each add and multiply operation. Unmasked exceptions will leave the

destination untouched.

Other Exceptions

See Table 2-19, “Type 2 Class Exception Conditions,” additionally:

#UD

If VEX.L= 1.

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DPPD-Dot Product of Packed Double Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-L

DPPS-Dot Product of Packed Single Precision Floating-Point Values

Opcode/

Op/

64/32-bit

CPUID

Description

Instruction

Mode

Feature

Flag

66 0F 3A 40 /r ib

RMI

V/V

SSE4_1

Selectively multiply packed single precision floating-

point values from xmm1 with packed single precision

DPPS xmm1, xmm2/m128, imm8

floating-point values from xmm2, add and selectively

store the packed single precision floating-point values

or zero values to xmm1.

VEX.128.66.0F3A.WIG 40 /r ib

RVMI

V/V

AVX

Multiply packed single precision floating-point values

from xmm1 with packed single precision floating-point

VDPPS xmm1,xmm2, xmm3/m128, imm8

values from xmm2/mem selectively add and store to

xmm1.

VEX.256.66.0F3A.WIG 40 /r ib

RVMI

V/V

AVX

Multiply packed single precision floating-point values

from ymm2 with packed single precision floating-point

VDPPS ymm1, ymm2, ymm3/m256, imm8

values from ymm3/mem, selectively add pairs of

elements and store to ymm1.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

RMI

ModRM:reg (r, w)

ModRM:r/m (r)

imm8

N/A

RVMI

ModRM:reg (w)

VEX.vvvv (r)

ModRM:r/m (r)

imm8

Description

Conditionally multiplies the packed single precision floating-point values in the destination operand (first operand)

with the packed single precision floats in the source (second operand) depending on a mask extracted from the

high 4 bits of the immediate byte (third operand). If a condition mask bit in imm8[7:4] is zero, the corresponding

multiplication is replaced by a value of 0.0 in the manner described by Section 12.8.4 of Intel^® 64 and IA-32 Archi-

tectures Software Developer’s Manual, Volume 1.

The four resulting single precision values are summed into an intermediate result. The intermediate result is condi-

tionally broadcasted to the destination using a broadcast mask specified by bits [3:0] of the immediate byte.

If a broadcast mask bit is “1”, the intermediate result is copied to the corresponding dword element in the destina-

tion operand. If a broadcast mask bit is zero, the corresponding element in the destination is set to zero.

DPPS follows the NaN forwarding rules stated in the Software Developer’s Manual, vol. 1, table 4.7. These rules do

not cover horizontal prioritization of NaNs. Horizontal propagation of NaNs to the destination and the positioning of

those NaNs in the destination is implementation dependent. NaNs on the input sources or computationally gener-

ated NaNs will have at least one NaN propagated to the destination.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAXVL-1:128) of the corresponding

YMM register destination are unmodified.

VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination

operand is an XMM register. The upper bits (MAXVL-1:128) of the corresponding YMM register destination are

zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM

DPPS-Dot Product of Packed Single Precision Floating-Point Values

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3-337

INSTRUCTION SET REFERENCE, A-L

Operation

DP_primitive (SRC1, SRC2)

IF (imm8[4] = 1)

THEN Temp1[31:0] := DEST[31:0] * SRC[31:0]; // update SIMD exception flags

ELSE Temp1[31:0] := +0.0; FI;

IF (imm8[5] = 1)

THEN Temp1[63:32] := DEST[63:32] * SRC[63:32]; // update SIMD exception flags

ELSE Temp1[63:32] := +0.0; FI;

IF (imm8[6] = 1)

THEN Temp1[95:64] := DEST[95:64] * SRC[95:64]; // update SIMD exception flags

ELSE Temp1[95:64] := +0.0; FI;

IF (imm8[7] = 1)

THEN Temp1[127:96] := DEST[127:96] * SRC[127:96]; // update SIMD exception flags

ELSE Temp1[127:96] := +0.0; FI;

Temp2[31:0] := Temp1[31:0] + Temp1[63:32]; // update SIMD exception flags

/* if unmasked exception reported, execute exception handler*/

Temp3[31:0] := Temp1[95:64] + Temp1[127:96]; // update SIMD exception flags

/* if unmasked exception reported, execute exception handler*/

Temp4[31:0] := Temp2[31:0] + Temp3[31:0]; // update SIMD exception flags

/* if unmasked exception reported, execute exception handler*/

IF (imm8[0] = 1)

THEN DEST[31:0] := Temp4[31:0];

ELSE DEST[31:0] := +0.0; FI;

IF (imm8[1] = 1)

THEN DEST[63:32] := Temp4[31:0];

ELSE DEST[63:32] := +0.0; FI;

IF (imm8[2] = 1)

THEN DEST[95:64] := Temp4[31:0];

ELSE DEST[95:64] := +0.0; FI;

IF (imm8[3] = 1)

THEN DEST[127:96] := Temp4[31:0];

ELSE DEST[127:96] := +0.0; FI;

DPPS (128-bit Legacy SSE Version)

DEST[127:0] := DP_Primitive(SRC1[127:0], SRC2[127:0]);

DEST[MAXVL-1:128] (Unmodified)

VDPPS (VEX.128 Encoded Version)

DEST[127:0] := DP_Primitive(SRC1[127:0], SRC2[127:0]);

DEST[MAXVL-1:128] := 0

VDPPS (VEX.256 Encoded Version)

DEST[127:0] := DP_Primitive(SRC1[127:0], SRC2[127:0]);

DEST[255:128] := DP_Primitive(SRC1[255:128], SRC2[255:128]);

Flags Affected

None.

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DPPS-Dot Product of Packed Single Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-L

EMMS-Empty MMX Technology State

Opcode

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

NP 0F 77

EMMS

Valid

Set the x87 FPU tag word to empty.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

N/A

Description

Sets the values of all the tags in the x87 FPU tag word to empty (all 1s). This operation marks the x87 FPU data

registers (which are aliased to the MMX technology registers) as available for use by x87 FPU floating-point instruc-

tions. (See Figure 8-7 in the Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for the

format of the x87 FPU tag word.) All other MMX instructions (other than the EMMS instruction) set all the tags in

x87 FPU tag word to valid (all 0s).

The EMMS instruction must be used to clear the MMX technology state at the end of all MMX technology procedures

or subroutines and before calling other procedures or subroutines that may execute x87 floating-point instructions.

If a floating-point instruction loads one of the registers in the x87 FPU data register stack before the x87 FPU tag

word has been reset by the EMMS instruction, an x87 floating-point register stack overflow can occur that will result

in an x87 floating-point exception or incorrect result.

EMMS operation is the same in non-64-bit modes and 64-bit mode.

Operation

x87FPUTagWord := FFFFH;

Intel C/C++ Compiler Intrinsic Equivalent

void _mm_empty()

Flags Affected

None

Protected Mode Exceptions

#UD

If CR0.EM[bit 2] = 1.

#NM

If CR0.TS[bit 3] = 1.

#MF

If there is a pending FPU exception.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as in protected mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

Same exceptions as in protected mode.

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EMMS-Empty MMX Technology State

INSTRUCTION SET REFERENCE, A-L

ENCODEKEY128-Encode 128-Bit Key With Key Locker

Opcode/

Op/

64/32-bit

CPUID

Description

Instruction

Mode

Feature

Flag

F3 0F 38 FA 11:rrr:bbb

V/V

AESKLE

Wrap a 128-bit AES key from XMM0 into a key handle

ENCODEKEY128 r32, r32, <XMM0-2>,

and output handle in XMM0-2.

<XMM4-6>

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operands 4-5

Operands 6-7

N/A

ModRM:reg (w)

ModRM:r/m (r)

Implicit XMM0 (r, w)

Implicit XMM1-2 (w)

Implicit XMM4-6 (w)

Description

The ENCODEKEY128¹ instruction wraps a 128-bit AES key from the implicit operand XMM0 into a key handle that

is then stored in the implicit destination operands XMM0-2.

The explicit source operand specifies handle restrictions, if any.

The explicit destination operand is populated with information on the source of the key and its attributes. XMM4

through XMM6 are reserved for future usages and software should not rely upon them being zeroed.

Operation

ENCODEKEY128

#GP (0) if a reserved bit² in SRC[31:0] is set

InputKey[127:0] := XMM0;

KeyMetadata[2:0] = SRC[2:0];

KeyMetadata[23:3] = 0;

// Reserved for future usage

KeyMetadata[27:24] = 0;

// KeyType is AES-128 (value of 0)

KeyMetadata[127:28] = 0;

// Reserved for future usage

// KeyMetadata is the AAD input and InputKey is the Plaintext input for WrapKey128

Handle[383:0] := WrapKey128(InputKey[127:0], KeyMetadata[127:0], IWKey.Integrity Key[127:0], IWKey.Encryption Key[255:0]);

DEST[0] := IWKey.NoBackup;

DEST[4:1] := IWKey.KeySource[3:0];

DEST[31:5] = 0;

XMM0 := Handle[127:0];

// AAD

XMM1 := Handle[255:128]; // Integrity Tag

XMM2 := Handle[383:256]; // CipherText

XMM4 := 0;

// Reserved for future usage

XMM5 := 0;

// Reserved for future usage

XMM6 := 0;

// Reserved for future usage

RFLAGS.OF, SF, ZF, AF, PF, CF := 0;

Flags Affected

All arithmetic flags (OF, SF, ZF, AF, PF, CF) are cleared to 0. Although they are cleared for the currently defined oper-

ations, future extensions may report information in the flags.

1. Further details on Key Locker and usage of this instruction can be found here:

https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.

2. SRC[31:3] are currently reserved for future usages. SRC[2], which indicates a no-decrypt restriction, is reserved if

CPUID.19H:EAX[2] is 0. SRC[1], which indicates a no-encrypt restriction, is reserved if CPUID.19H:EAX[1] is 0. SRC[0], which indicates

a CPL0-only restriction, is reserved if CPUID.19H:EAX[0] is 0.

ENCODEKEY128-Encode 128-Bit Key With Key Locker

Vol. 2A

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INSTRUCTION SET REFERENCE, A-L

ENCODEKEY256-Encode 256-Bit Key With Key Locker

Opcode/

Op/

64/32-bit

CPUID

Description

Instruction

Mode

Feature

Flag

F3 0F 38 FB 11:rrr:bbb

V/V

AESKLE

Wrap a 256-bit AES key from XMM1:XMM0 into a key

ENCODEKEY256 r32, r32 <XMM0-6>

handle and store it in XMM0-3.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operands 3-4

Operands 5-9

N/A

ModRM:reg (w)

ModRM:r/m (r)

Implicit XMM0-1 (r, w)

Implicit XMM2-6 (w)

Description

The ENCODEKEY256¹ instruction wraps a 256-bit AES key from the implicit operand XMM1:XMM0 into a key handle

that is then stored in the implicit destination operands XMM0-3.

The explicit source operand is a general-purpose register and specifies what handle restrictions should be built into

the handle.

The explicit destination operand is populated with information on the source of the key and its attributes. XMM4

through XMM6 are reserved for future usages and software should not rely upon them being zeroed.

Operation

ENCODEKEY256

#GP (0) if a reserved bit² in SRC[31:0] is set

InputKey[255:0] := XMM1:XMM0;

KeyMetadata[2:0] = SRC[2:0];

KeyMetadata[23:3] = 0;

// Reserved for future usage

KeyMetadata[27:24] = 1;

// KeyType is AES-256 (value of 1)

KeyMetadata[127:28] = 0; // Reserved for future usage

// KeyMetadata is the AAD input and InputKey is the Plaintext input for WrapKey256

Handle[511:0] := WrapKey256(InputKey[255:0], KeyMetadata[127:0], IWKey.Integrity Key[127:0], IWKey.Encryption Key[255:0]);

DEST[0] := IWKey.NoBackup;

DEST[4:1] := IWKey.KeySource[3:0];

DEST[31:5] = 0;

XMM0 := Handle[127:0];

// AAD

XMM1 := Handle[255:128]; // Integrity Tag

XMM2 := Handle[383:256]; // CipherText[127:0]

XMM3 := Handle[511:384]; // CipherText[255:128]

XMM4 := 0;

// Reserved for future usage

XMM5 := 0;

// Reserved for future usage

XMM6 := 0;

// Reserved for future usage

RFLAGS.OF, SF, ZF, AF, PF, CF := 0;

1. Further details on Key Locker and usage of this instruction can be found here:

https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.

2. SRC[31:3] are currently reserved for future usages. SRC[2], which indicates a no-decrypt restriction, is reserved if

CPUID.19H:EAX[2] is 0. SRC[1], which indicates a no-encrypt restriction, is reserved if CPUID.19H:EAX[1] is 0. SRC[0], which indicates

a CPL0-only restriction, is reserved if CPUID.19H:EAX[0] is 0.

ENCODEKEY256-Encode 256-Bit Key With Key Locker

Vol. 2A

3-343

INSTRUCTION SET REFERENCE, A-L

ENDBR32-Terminate an Indirect Branch in 32-bit and Compatibility Mode

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F3 0F 1E FB

V/V

CET_IBT

Terminate indirect branch in 32-bit and compatibility

ENDBR32

mode.

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

Description

Terminate an indirect branch in 32 bit and compatibility mode.

Operation

IF EndbranchEnabled(CPL) & (IA32_EFER.LMA = 0 | (IA32_EFER.LMA=1 & CS.L = 0)

IF CPL = 3

THEN

IA32_U_CET.TRACKER = IDLE

IA32_U_CET.SUPPRESS = 0

ELSE

IA32_S_CET.TRACKER = IDLE

IA32_S_CET.SUPPRESS = 0

FI;

Flags Affected

None.

Exceptions

None.

ENDBR32-Terminate an Indirect Branch in 32-bit and Compatibility Mode

Vol. 2A

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INSTRUCTION SET REFERENCE, A-L

ENDBR64-Terminate an Indirect Branch in 64-bit Mode

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature

Support

Flag

F3 0F 1E FA

V/V

CET_IBT

Terminate indirect branch in 64-bit mode.

ENDBR64

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

Description

Terminate an indirect branch in 64 bit mode.

Operation

IF EndbranchEnabled(CPL) & IA32_EFER.LMA = 1 & CS.L = 1

IF CPL = 3

THEN

IA32_U_CET.TRACKER = IDLE

IA32_U_CET.SUPPRESS = 0

ELSE

IA32_S_CET.TRACKER = IDLE

IA32_S_CET.SUPPRESS = 0

FI;

Flags Affected

None.

Exceptions

None.

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ENDBR64-Terminate an Indirect Branch in 64-bit Mode

INSTRUCTION SET REFERENCE, A-L

ENTER-Make Stack Frame for Procedure Parameters

Opcode

Instruction

Op/

64-Bit

Compat/

Description

Mode

Leg Mode

C8 iw 00

ENTER imm16, 0

Valid

Create a stack frame for a procedure.

C8 iw 01

ENTER imm16,1

Valid

Create a stack frame with a nested pointer for

a procedure.

C8 iw ib

ENTER imm16, imm8

Valid

Create a stack frame with nested pointers for

a procedure.

Instruction Operand Encoding

Op/En

Operand 1

Operand 2

Operand 3

Operand 4

imm8

N/A

Description

Creates a stack frame (comprising of space for dynamic storage and 1-32 frame pointer storage) for a procedure.

The first operand (imm16) specifies the size of the dynamic storage in the stack frame (that is, the number of bytes

of dynamically allocated on the stack for the procedure). The second operand (imm8) gives the lexical nesting level

(0 to 31) of the procedure. The nesting level (imm8 mod 32) and the OperandSize attribute determine the size in

bytes of the storage space for frame pointers.

The nesting level determines the number of frame pointers that are copied into the “display area” of the new stack

frame from the preceding frame. The default size of the frame pointer is the StackAddrSize attribute, but can be

overridden using the 66H prefix. Thus, the OperandSize attribute determines the size of each frame pointer that

will be copied into the stack frame and the data being transferred from SP/ESP/RSP register into the BP/EBP/RBP

The ENTER and companion LEAVE instructions are provided to support block structured languages. The ENTER

instruction (when used) is typically the first instruction in a procedure and is used to set up a new stack frame for

a procedure. The LEAVE instruction is then used at the end of the procedure (just before the RET instruction) to

release the stack frame.

If the nesting level is 0, the processor pushes the frame pointer from the BP/EBP/RBP register onto the stack,

copies the current stack pointer from the SP/ESP/RSP register into the BP/EBP/RBP register, and loads the

SP/ESP/RSP register with the current stack-pointer value minus the value in the size operand. For nesting levels of

1 or greater, the processor pushes additional frame pointers on the stack before adjusting the stack pointer. These

additional frame pointers provide the called procedure with access points to other nested frames on the stack. See

“Procedure Calls for Block-Structured Languages” in Chapter 6 of the Intel^® 64 and IA-32 Architectures Software

Developer’s Manual, Volume 1, for more information about the actions of the ENTER instruction.

The ENTER instruction causes a page fault whenever a write using the final value of the stack pointer (within the

current stack segment) would do so.

In 64-bit mode, default operation size is 64 bits; 32-bit operation size cannot be encoded. Use of 66H prefix

changes frame pointer operand size to 16 bits.

When the 66H prefix is used and causing the OperandSize attribute to be less than the StackAddrSize, software is

responsible for the following:

• The companion LEAVE instruction must also use the 66H prefix,

• The value in the RBP/EBP register prior to executing “66H ENTER” must be within the same 16KByte region of

the current stack pointer (RSP/ESP), such that the value of RBP/EBP after “66H ENTER” remains a valid address

in the stack. This ensures “66H LEAVE” can restore 16-bits of data from the stack.

ENTER-Make Stack Frame for Procedure Parameters

Vol. 2A

3-347

INSTRUCTION SET REFERENCE, A-L

Operation

AllocSize := imm16;

NestingLevel := imm8 MOD 32;

IF (OperandSize = 64)

THEN

Push(RBP); (* RSP decrements by 8 *)

FrameTemp := RSP;

ELSE IF OperandSize = 32

THEN

Push(EBP); (* (E)SP decrements by 4 *)

FrameTemp := ESP; FI;

ELSE (* OperandSize = 16 *)

Push(BP); (* RSP or (E)SP decrements by 2 *)

FrameTemp := SP;

FI;

IF NestingLevel = 0

THEN GOTO CONTINUE;

FI;

IF (NestingLevel > 1)

THEN FOR i := 1 to (NestingLevel - 1)

IF (OperandSize = 64)

THEN

RBP := RBP - 8;

Push([RBP]); (* Quadword push *)

ELSE IF OperandSize = 32

THEN

IF StackSize = 32

EBP := EBP - 4;

Push([EBP]); (* Doubleword push *)

ELSE (* StackSize = 16 *)

BP := BP - 4;

Push([BP]); (* Doubleword push *)

FI;

ELSE (* OperandSize = 16 *)

IF StackSize = 64

THEN

RBP := RBP - 2;

Push([RBP]); (* Word push *)

ELSE IF StackSize = 32

THEN

EBP := EBP - 2;

Push([EBP]); (* Word push *)

ELSE (* StackSize = 16 *)

BP := BP - 2;

Push([BP]); (* Word push *)

FI;

OD;

FI;

IF (OperandSize = 64) (* nestinglevel 1 *)

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ENTER-Make Stack Frame for Procedure Parameters

INSTRUCTION SET REFERENCE, A-L

THEN

Push(FrameTemp); (* Quadword push and RSP decrements by 8 *)

ELSE IF OperandSize = 32

THEN

Push(FrameTemp); FI; (* Doubleword push and (E)SP decrements by 4 *)

ELSE (* OperandSize = 16 *)

Push(FrameTemp); (* Word push and RSP|ESP|SP decrements by 2 *)

FI;

CONTINUE:

IF 64-Bit Mode (StackSize = 64)

THEN

RBP := FrameTemp;

RSP := RSP - AllocSize;

ELSE IF OperandSize = 32

THEN

EBP := FrameTemp;

ESP := ESP - AllocSize; FI;

ELSE (* OperandSize = 16 *)

BP := FrameTemp[15:1]; (* Bits 16 and above of applicable RBP/EBP are unmodified *)

SP := SP - AllocSize;

FI;

END;

Flags Affected

None.

Protected Mode Exceptions

#SS(0)

If the new value of the SP or ESP register is outside the stack segment limit.

#PF(fault-code)

If a page fault occurs or if a write using the final value of the stack pointer (within the current

stack segment) would cause a page fault.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

#SS

If the new value of the SP or ESP register is outside the stack segment limit.

#UD

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#SS(0)

If the new value of the SP or ESP register is outside the stack segment limit.

#PF(fault-code)

If a page fault occurs or if a write using the final value of the stack pointer (within the current

stack segment) would cause a page fault.

#UD

If the LOCK prefix is used.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0)

If the stack address is in a non-canonical form.

#PF(fault-code)

If a page fault occurs or if a write using the final value of the stack pointer (within the current

stack segment) would cause a page fault.

#UD

If the LOCK prefix is used.

ENTER-Make Stack Frame for Procedure Parameters

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INSTRUCTION SET REFERENCE, A-L

ENQCMD-Enqueue Command

Opcode/

Op/

64/32 bit

CPUID Feature

Description

Instruction

Mode

Flag

Support

F2 0F 38 F8 !(11):rrr:bbb

V/V

ENQCMD

Atomically enqueue 64-byte user command from

ENQCMD r32/r64, m512

source memory operand to destination offset in

ES segment specified in register operand as

offset in ES segment.

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

The ENQCMD instruction allows software to write commands to enqueue registers, which are special device

registers accessed using memory-mapped I/O (MMIO).

Enqueue registers expect writes to have the following format:

511

20 19

DEVICE SPECIFIC COMMAND

PRIV

RESERVED

PASID

Figure 3-16. 64-Byte Data Written to Enqueue Registers

Bits 19:0 convey the process address space identifier (PASID), a value which system software may assign to indi-

vidual software threads. Bit 31 contains privilege identification (0 = user; 1 = supervisor). Devices implementing

enqueue registers may use these two values along with a device-specific command in the upper 60 bytes.

The ENQCMD instruction begins by reading 64 bytes of command data from its source memory operand. This is an

ordinary load with cacheability and memory ordering implied normally by the memory type. The source operand

need not be aligned, and there is no guarantee that all 64 bytes are loaded atomically. Bits 31:0 of the source

operand must be zero.

The instruction then formats those 64 bytes into command data with a format consistent with that given in

Figure 3-16:

• Command[19:0] get IA32_PASID[19:0].¹

• Command[30:20] are zero.

• Command[31] is 0 (indicating user; this value is used regardless of CPL).

• Command[511:32] get bits 511:32 of the source operand that was read from memory.

The ENQCMD instruction uses an enqueue store (defined below) to write this command data to the destination

operand. The address of the destination operand is specified in a general-purpose register as an offset into the ES

segment (the segment cannot be overridden).² The destination linear address must be 64-byte aligned. The oper-

ation of an enqueue store disregards the memory type of the destination memory address.

1. It is expected that system software will load the IA32_PASID MSR so that bits 19:0 contain the PASID of the current soft-

ware thread. The MSR’s valid bit, IA32_PASID[31], must be 1. For additional details on the IA32_PASID MSR, see the Intel^®

64 and IA-32 Architectures Software Developer’s Manual, Volume 4.

2. In 64-bit mode, the width of the register operand is 64 bits (32 bits with a 67H prefix). Outside 64-bit mode when CS.D =

1, the width is 32 bits (16 bits with a 67H prefix). Outside 64-bit mode when CS.D=0, the width is 16 bits (32 bits with a

67H prefix).

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ENQCMD-Enqueue Command

INSTRUCTION SET REFERENCE, A-L

An enqueue store is not ordered relative to older stores to WB or WC memory (including non-temporal stores) or

to executions of the CLFLUSHOPT or CLWB (when applied to addresses other than that of the enqueue store). Soft-

ware can enforce such ordering by executing a fencing instruction such as SFENCE or MFENCE before the enqueue

store.

An enqueue store does not write the data into the cache hierarchy, nor does it fetch any data into the cache hier-

archy. An enqueue store’s command data is never combined with that of any other store to the same address.

Unlike other stores, an enqueue store returns a status, which the ENQCMD instruction loads into the ZF flag in the

RFLAGS register:

• ZF = 0 (success) reports that the 64-byte command data was written atomically to a device’s enqueue register

and has been accepted by the device. (It does not guarantee that the device has acted on the command; it may

have queued it for later execution.)

• ZF = 1 (retry) reports that the command data was not accepted. This status is returned if the destination

address is an enqueue register but the command was not accepted due to capacity or other temporal reasons.

This status is also returned if the destination address was not an enqueue register (including the case of a

memory address); in these cases, the store is dropped and is written neither to MMIO nor to memory.

Availability of the ENQCMD instruction is indicated by the presence of the CPUID feature flag ENQCMD

(CPUID.(EAX=07H, ECX=0H):ECX[bit 29]).

Operation

IF IA32_PASID[31] = 0

THEN #GP;

ELSE

COMMAND := (SRC & ~FFFFFFFFH) | (IA32_PASID & FFFFFH);

DEST := COMMAND;

FI;

Intel C/C++ Compiler Intrinsic Equivalent

ENQCMD int_enqcmd(void *dst, const void *src)

Flags Affected

The ZF flag is set if the enqueue-store completion returns the retry status; otherwise it is cleared. All other flags

are cleared.

SIMD Floating-Point Exceptions

None.

Protected Mode Exceptions

#GP(0)

For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.

If destination linear address is not aligned to a 64-byte boundary.

If the PASID Valid field (bit 31) is 0 in IA32_PASID MSR.

If bits 31:0 of the source operand are not all zero.

#SS(0)

For an illegal address in the SS segment.

#PF(fault-code)

For a page fault.

#UD

If CPUID.07H.0H:ECX.ENQCMD[bit 29] = 0.

If the LOCK prefix is used.

ENQCMD-Enqueue Command

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INSTRUCTION SET REFERENCE, A-L

Real-Address Mode Exceptions

#GP

If any part of the operand lies outside the effective address space from 0 to FFFFH.

If destination linear address is not aligned to a 64-byte boundary.

If the PASID Valid field (bit 31) is 0 in IA32_PASID MSR.

If bits 31:0 of the source operand are not all zero.

#UD

If CPUID.07H.0H:ECX.ENQCMD[bit 29] = 0.

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

Same exceptions as in real-address mode. Additionally:

#PF(fault-code)

For a page fault.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0)

If a memory address referencing the SS segment is in non-canonical form.

#GP(0)

If the memory address is in non-canonical form.

If destination linear address is not aligned to a 64-byte boundary.

If the PASID Valid field (bit 31) is 0 in IA32_PASID MSR.

If bits 31:0 of the source operand are not all zero.

#PF(fault-code)

For a page fault.

#UD

If CPUID.07H.0H:ECX.ENQCMD[bit 29].

If the LOCK prefix is used.

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ENQCMD-Enqueue Command

INSTRUCTION SET REFERENCE, A-L

ENQCMDS-Enqueue Command Supervisor

Opcode/

Op/

64/32 bit

CPUID Feature

Description

Instruction

Mode

Flag

Support

F3 0F 38 F8 !(11):rrr:bbb

V/V

ENQCMD

Atomically enqueue 64-byte command with

ENQCMDS r32/r64, m512

PASID from source memory operand to

destination offset in ES segment specified in

Instruction Operand Encoding

Op/En

Tuple

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:reg (w)

ModRM:r/m (r)

N/A

Description

The ENQCMDS instruction allows system software to write commands to enqueue registers, which are special

device registers accessed using memory-mapped I/O (MMIO).

Enqueue registers expect writes to have the format given in Figure 3-16 and explained in the section on

“ENQCMD-Enqueue Command.”

The ENQCMDS instruction begins by reading 64 bytes of command data from its source memory operand. This is

an ordinary load with cacheability and memory ordering implied normally by the memory type. The source operand

need not be aligned, and there is no guarantee that all 64 bytes are loaded atomically. Bits 30:20 of the source

operand must be zero.

ENQCMDS formats its source data differently from ENQCMD. Specifically, it formats them into command data as

follows:

• Command[19:0] get bits 19:0 of the source operand that was read from memory. These 20 bits communicate

a process address-space identifier (PASID).

• Command[30:20] are zero.

• Command[511:31] get bits 511:31 of the source operand that was read from memory. Bit 31 communicates a

privilege identification (0 = user; 1 = supervisor).

The ENQCMDS instruction then uses an enqueue store (defined below) to write this command data to the desti-

nation operand. The address of the destination operand is specified in a general-purpose register as an offset into

the ES segment (the segment cannot be overridden).¹ The destination linear address must be 64-byte aligned. The

operation of an enqueue store disregards the memory type of the destination memory address.

An enqueue store is not ordered relative to older stores to WB or WC memory (including non-temporal stores) or

to executions of the CLFLUSHOPT or CLWB (when applied to addresses other than that of the enqueue store). Soft-

ware can enforce such ordering by executing a fencing instruction such as SFENCE or MFENCE before the enqueue

store.

An enqueue store does not write the data into the cache hierarchy, nor does it fetch any data into the cache hier-

archy. An enqueue store’s command data is never combined with that of any other store to the same address.

Unlike other stores, an enqueue store returns a status, which the ENQCMDS instruction loads into the ZF flag in the

RFLAGS register:

• ZF = 0 (success) reports that the 64-byte command data was written atomically to a device’s enqueue register

and has been accepted by the device. (It does not guarantee that the device has acted on the command; it may

have queued it for later execution.)

• ZF = 1 (retry) reports that the command data was not accepted. This status is returned if the destination

address is an enqueue register but the command was not accepted due to capacity or other temporal reasons.

1. In 64-bit mode, the width of the register operand is 64 bits (32 bits with a 67H prefix). Outside 64-bit mode when CS.D =

1, the width is 32 bits (16 bits with a 67H prefix). Outside 64-bit mode when CS.D=0, the width is 16 bits (32 bits with a

67H prefix).

ENQCMDS-Enqueue Command Supervisor

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INSTRUCTION SET REFERENCE, A-L

This status is also returned if the destination address was not an enqueue register (including the case of a

memory address); in these cases, the store is dropped and is written neither to MMIO nor to memory.

The ENQCMDS instruction may be executed only if CPL = 0. Availability of the ENQCMDS instruction is indicated by

the presence of the CPUID feature flag ENQCMD (CPUID.(EAX=07H, ECX=0H):ECX[bit 29]).

Operation

DEST := SRC;

Intel C/C++ Compiler Intrinsic Equivalent

ENQCMDS int_enqcmds(void *dst, const void *src)

Flags Affected

The ZF flag is set if the enqueue-store completion returns the retry status; otherwise it is cleared. All other flags

are cleared.

SIMD Floating-Point Exceptions

None.

Protected Mode Exceptions

#GP(0)

For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.

If destination linear address is not aligned to a 64-byte boundary.

If the current privilege level is not 0.

If bits 30:20 of the source operand are not all zero.

#SS(0)

For an illegal address in the SS segment.

#PF(fault-code)

For a page fault.

#UD

If CPUID.07H.0H:ECX.ENQCMD[bit 29] = 0.

If the LOCK prefix is used.

Real-Address Mode Exceptions

#GP

If any part of the operand lies outside the effective address space from 0 to FFFFH.

If destination linear address is not aligned to a 64-byte boundary.

If bits 30:20 of the source operand are not all zero.

#UD

If CPUID.07H.0H:ECX.ENQCMD[bit 29] = 0.

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#GP(0)

The ENQCMDS instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0)

If a memory address referencing the SS segment is in non-canonical form.

#GP(0)

If the memory address is in non-canonical form.

If destination linear address is not aligned to a 64-byte boundary.

If the current privilege level is not 0.

If bits 30:20 of the source operand are not all zero.

#PF(fault-code)

For a page fault.

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ENQCMDS-Enqueue Command Supervisor

INSTRUCTION SET REFERENCE, A-L

EXTRACTPS-Extract Packed Floating-Point Values

Opcode/

Op /

64/32 bit

CPUID

Description

Instruction

Mode

Feature Flag

Support

66 0F 3A 17 /r ib

SSE4_1

Extract one single precision floating-point value from

EXTRACTPS reg/m32, xmm1, imm8

xmm1 at the offset specified by imm8 and store the

result in reg or m32. Zero extend the results in 64-bit

VEX.128.66.0F3A.WIG 17 /r ib

V/V

AVX

Extract one single precision floating-point value from

VEXTRACTPS reg/m32, xmm1, imm8

xmm1 at the offset specified by imm8 and store the

result in reg or m32. Zero extend the results in 64-bit

EVEX.128.66.0F3A.WIG 17 /r ib

V/V

AVX512F

Extract one single precision floating-point value from

VEXTRACTPS reg/m32, xmm1, imm8

xmm1 at the offset specified by imm8 and store the

result in reg or m32. Zero extend the results in 64-bit

Instruction Operand Encoding

Op/En

Tuple Type

Operand 1

Operand 2

Operand 3

Operand 4

N/A

ModRM:r/m (w)

ModRM:reg (r)

imm8

N/A

Tuple1 Scalar

ModRM:r/m (w)

ModRM:reg (r)

imm8

N/A

Description

Extracts a single precision floating-point value from the source operand (second operand) at the 32-bit offset spec-

ified from imm8. Immediate bits higher than the most significant offset for the vector length are ignored.

The extracted single precision floating-point value is stored in the low 32-bits of the destination operand

In 64-bit mode, destination register operand has default operand size of 64 bits. The upper 32-bits of the register

are filled with zero. REX.W is ignored.

VEX.128 and EVEX encoded version: When VEX.W1 or EVEX.W1 form is used in 64-bit mode with a general purpose

VEX.vvvv/EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

128-bit Legacy SSE version: When a REX.W prefix is used in 64-bit mode with a general purpose register (GPR) as

a destination operand, the packed single quantity is zero extended to 64 bits.

The source register is an XMM register. Imm8[1:0] determine the starting DWORD offset from which to extract the

32-bit floating-point value.

If VEXTRACTPS is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause

an #UD exception.

Operation

VEXTRACTPS (EVEX and VEX.128 Encoded Version)

SRC_OFFSET := IMM8[1:0]

IF (64-Bit Mode and DEST is register)

DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh

DEST[63:32] := 0

ELSE

DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh

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EXTRACTPS-Extract Packed Floating-Point Values

INSTRUCTION SET REFERENCE, A-L

EXTRACTPS (128-bit Legacy SSE Version)

SRC_OFFSET := IMM8[1:0]

IF (64-Bit Mode and DEST is register)

DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh

DEST[63:32] := 0

ELSE

DEST[31:0] := (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh

Intel C/C++ Compiler Intrinsic Equivalent

EXTRACTPS int _mm_extract_ps (__m128 a, const int nidx);

SIMD Floating-Point Exceptions

None.

Other Exceptions

VEX-encoded instructions, see Table 2-22, “Type 5 Class Exception Conditions.”

EVEX-encoded instructions, see Table 2-57, “Type E9NF Class Exception Conditions.”

Additionally:

#UD

IF VEX.L = 0.

#UD

If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.

EXTRACTPS-Extract Packed Floating-Point Values

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INSTRUCTION SET REFERENCE, A-L

F2XM1-Compute 2^x-1

Opcode

Instruction

64-Bit

Compat/

Description

Mode

Leg Mode

D9 F0

F2XM1

Valid

Replace ST(0) with (2ST(0) - 1).

Description

Computes the exponential value of 2 to the power of the source operand minus 1. The source operand is located in

+1.0. If the source value is outside this range, the result is undefined.

The following table shows the results obtained when computing the exponential value of various classes of

numbers, assuming that neither overflow nor underflow occurs.

Table 3-16. Results Obtained from F2XM1

ST(0) SRC

ST(0) DEST

− 1.0 to -0

- 0.5 to - 0

- 0

+ 0

+ 0 to +1.0

+ 0 to 1.0

Values other than 2 can be exponentiated using the following formula:

x^y := 2(y ∗ log2^x)

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

ST(0) := (2^ST(0) - 1);

FPU Flags Affected

Set to 0 if stack underflow occurred.

Set if result was rounded up; cleared otherwise.

C0, C2, C3

Undefined.

Floating-Point Exceptions

#IS

Stack underflow occurred.

#IA

Source operand is an SNaN value or unsupported format.

Source is a denormal value.

Result is too small for destination format.

Value cannot be represented exactly in destination format.

Protected Mode Exceptions

#NM

CR0.EM[bit 2] or CR0.TS[bit 3] = 1.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as in protected mode.

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F2XM1-Compute 2x-1

INSTRUCTION SET REFERENCE, A-L

FABS-Absolute Value

Opcode

Instruction

64-Bit

Compat/

Description

Mode

Leg Mode

D9 E1

FABS

Valid

Replace ST with its absolute value.

Description

Clears the sign bit of ST(0) to create the absolute value of the operand. The following table shows the results

obtained when creating the absolute value of various classes of numbers.

Table 3-17. Results Obtained from FABS

ST(0) SRC

ST(0) DEST

- ∞

+ ∞

- F

+ F

− 0

+ 0

+ F

+ ∞

NaN

NOTES:

F Means finite floating-point value.

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

ST(0) := |ST(0)|;

FPU Flags Affected

Set to 0.

C0, C2, C3

Undefined.

Floating-Point Exceptions

#IS

Stack underflow occurred.

Protected Mode Exceptions

#NM

CR0.EM[bit 2] or CR0.TS[bit 3] = 1.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as in protected mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

Same exceptions as in protected mode.

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FABS-Absolute Value

INSTRUCTION SET REFERENCE, A-L

FADD/FADDP/FIADD-Add

Opcode

Instruction

64-Bit

Compat/

Description

Mode

Leg Mode

D8 /0

FADD m32fp

Valid

Add m32fp to ST(0) and store result in ST(0).

DC /0

FADD m64fp

Valid

Add m64fp to ST(0) and store result in ST(0).

D8 C0+i

FADD ST(0), ST(i)

Valid

Add ST(0) to ST(i) and store result in ST(0).

DC C0+i

FADD ST(i), ST(0)

Valid

Add ST(i) to ST(0) and store result in ST(i).

DE C0+i

FADDP ST(i), ST(0)

Valid

Add ST(0) to ST(i), store result in ST(i), and pop the

DE C1

FADDP

Valid

Add ST(0) to ST(1), store result in ST(1), and pop the

DA /0

FIADD m32int

Valid

Add m32int to ST(0) and store result in ST(0).

DE /0

FIADD m16int

Valid

Add m16int to ST(0) and store result in ST(0).

Description

Adds the destination and source operands and stores the sum in the destination location. The destination operand

is always an FPU register; the source operand can be a register or a memory location. Source operands in memory

can be in single precision or double precision floating-point format or in word or doubleword integer format.

The no-operand version of the instruction adds the contents of the ST(0) register to the ST(1) register. The one-

operand version adds the contents of a memory location (either a floating-point or an integer value) to the

contents of the ST(0) register. The two-operand version, adds the contents of the ST(0) register to the ST(i)

FADD ST(0), ST(0);

The FADDP instructions perform the additional operation of popping the FPU register stack after storing the result.

To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP)

by 1. (The no-operand version of the floating-point add instructions always results in the register stack being

popped. In some assemblers, the mnemonic for this instruction is FADD rather than FADDP.)

The FIADD instructions convert an integer source operand to double extended-precision floating-point format

before performing the addition.

The table on the following page shows the results obtained when adding various classes of numbers, assuming that

neither overflow nor underflow occurs.

When the sum of two operands with opposite signs is 0, the result is +0, except for the round toward -∞ mode, in

which case the result is -0. When the source operand is an integer 0, it is treated as a +0.

When both operand are infinities of the same sign, the result is ∞ of the expected sign. If both operands are infini-

ties of opposite signs, an invalid-operation exception is generated. See Table 3-18.

FADD/FADDP/FIADD-Add

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INSTRUCTION SET REFERENCE, A-L

Table 3-18. FADD/FADDP/FIADD Results

DEST

- ∞

- F

- 0

+ 0

+ F

+ ∞

NaN

− ∞

- ∞

NaN

− F or - I

- ∞

- F

SRC

± F or ± 0

+ ∞

NaN

SRC

-0

- ∞

DEST

- 0

± 0

DEST

+ ∞

NaN

+ 0

- ∞

DEST

± 0

+ 0

DEST

+ ∞

NaN

+ F or + I

- ∞

± F or ± 0

SRC

+ F

+ ∞

NaN

+ ∞

NaN

NOTES:

F Means finite floating-point value.

Means integer.

* Indicates floating-point invalid-arithmetic-operand (#IA) exception.

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

IF Instruction = FIADD

THEN

DEST := DEST + ConvertToDoubleExtendedPrecisionFP(SRC);

ELSE (* Source operand is floating-point value *)

DEST := DEST + SRC;

FI;

IF Instruction = FADDP

THEN

PopRegisterStack;

FI;

FPU Flags Affected

Set to 0 if stack underflow occurred.

Set if result was rounded up; cleared otherwise.

C0, C2, C3

Undefined.

Floating-Point Exceptions

#IS

Stack underflow occurred.

#IA

Operand is an SNaN value or unsupported format.

Operands are infinities of unlike sign.

Source operand is a denormal value.

Result is too small for destination format.

Result is too large for destination format.

Value cannot be represented exactly in destination format.

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INSTRUCTION SET REFERENCE, A-L

Protected Mode Exceptions

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register contains a NULL segment selector.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#NM

CR0.EM[bit 2] or CR0.TS[bit 3] = 1.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

#GP

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS

If a memory operand effective address is outside the SS segment limit.

#NM

CR0.EM[bit 2] or CR0.TS[bit 3] = 1.

#UD

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#NM

CR0.EM[bit 2] or CR0.TS[bit 3] = 1.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made.

#UD

If the LOCK prefix is used.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0)

If a memory address referencing the SS segment is in a non-canonical form.

#GP(0)

If the memory address is in a non-canonical form.

#NM

CR0.EM[bit 2] or CR0.TS[bit 3] = 1.

#MF

If there is a pending x87 FPU exception.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used.

FADD/FADDP/FIADD-Add

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INSTRUCTION SET REFERENCE, A-L

FBLD-Load Binary Coded Decimal

Opcode

Instruction

64-Bit

Compat/

Description

Mode

Leg Mode

DF /4

FBLD m80bcd

Valid

Convert BCD value to floating-point and push onto the

FPU stack.

Description

Converts the BCD source operand into double extended-precision floating-point format and pushes the value onto

the FPU stack. The source operand is loaded without rounding errors. The sign of the source operand is preserved,

including that of -0.

The packed BCD digits are assumed to be in the range 0 through 9; the instruction does not check for invalid digits

(AH through FH). Attempting to load an invalid encoding produces an undefined result.

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

TOP := TOP - 1;

ST(0) := ConvertToDoubleExtendedPrecisionFP(SRC);

FPU Flags Affected

Set to 1 if stack overflow occurred; otherwise, set to 0.

C0, C2, C3

Undefined.

Floating-Point Exceptions

#IS

Stack overflow occurred.

Protected Mode Exceptions

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register contains a NULL segment selector.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#NM

CR0.EM[bit 2] or CR0.TS[bit 3] = 1.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

#GP

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS

If a memory operand effective address is outside the SS segment limit.

#NM

CR0.EM[bit 2] or CR0.TS[bit 3] = 1.

#UD

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#NM

CR0.EM[bit 2] or CR0.TS[bit 3] = 1.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made.

#UD

If the LOCK prefix is used.

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INSTRUCTION SET REFERENCE, A-L

FBSTP-Store BCD Integer and Pop

Opcode

Instruction

64-Bit

Compat/

Description

Mode

Leg Mode

DF /6

FBSTP m80bcd

Valid

Store ST(0) in m80bcd and pop ST(0).

Description

Converts the value in the ST(0) register to an 18-digit packed BCD integer, stores the result in the destination

operand, and pops the register stack. If the source value is a non-integral value, it is rounded to an integer value,

according to rounding mode specified by the RC field of the FPU control word. To pop the register stack, the

processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.

The destination operand specifies the address where the first byte destination value is to be stored. The BCD value

(including its sign bit) requires 10 bytes of space in memory.

The following table shows the results obtained when storing various classes of numbers in packed BCD format.

Table 3-19. FBSTP Results

ST(0)

DEST

− ∞ or Value Too Large for DEST Format

F ≤ - 1

- D

−1 < F < -0

- 0

+ 0

+ 0 < F < +1

F ≥ +1

+ D

+ ∞ or Value Too Large for DEST Format

NaN

NOTES:

F Means finite floating-point value.

D Means packed-BCD number.

* Indicates floating-point invalid-operation (#IA) exception.

** ±0 or ±1, depending on the rounding mode.

If the converted value is too large for the destination format, or if the source operand is an ∞, SNaN, QNAN, or is in

an unsupported format, an invalid-arithmetic-operand condition is signaled. If the invalid-operation exception is

not masked, an invalid-arithmetic-operand exception (#IA) is generated and no value is stored in the destination

operand. If the invalid-operation exception is masked, the packed BCD indefinite value is stored in memory.

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

DEST := BCD(ST(0));

PopRegisterStack;

FPU Flags Affected

Set to 0 if stack underflow occurred.

Set if result was rounded up; cleared otherwise.

C0, C2, C3

Undefined.

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INSTRUCTION SET REFERENCE, A-L

Floating-Point Exceptions

#IS

Stack underflow occurred.

#IA

Converted value that exceeds 18 BCD digits in length.

Source operand is an SNaN, QNaN, ±∞, or in an unsupported format.

Value cannot be represented exactly in destination format.

Protected Mode Exceptions

#GP(0)

If a segment register is being loaded with a segment selector that points to a non-writable

segment.

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

If the DS, ES, FS, or GS register contains a NULL segment selector.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#NM

CR0.EM[bit 2] or CR0.TS[bit 3] = 1.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

#GP

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS

If a memory operand effective address is outside the SS segment limit.

#NM

CR0.EM[bit 2] or CR0.TS[bit 3] = 1.

#UD

If the LOCK prefix is used.

Virtual-8086 Mode Exceptions

#GP(0)

If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.

#SS(0)

If a memory operand effective address is outside the SS segment limit.

#NM

CR0.EM[bit 2] or CR0.TS[bit 3] = 1.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made.

#UD

If the LOCK prefix is used.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

64-Bit Mode Exceptions

#SS(0)

If a memory address referencing the SS segment is in a non-canonical form.

#GP(0)

If the memory address is in a non-canonical form.

#NM

CR0.EM[bit 2] or CR0.TS[bit 3] = 1.

#MF

If there is a pending x87 FPU exception.

#PF(fault-code)

If a page fault occurs.

#AC(0)

If alignment checking is enabled and an unaligned memory reference is made while the

current privilege level is 3.

#UD

If the LOCK prefix is used.

FBSTP-Store BCD Integer and Pop

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INSTRUCTION SET REFERENCE, A-L

FCHS-Change Sign

Opcode

Instruction

64-Bit

Compat/

Description

Mode

Leg Mode

D9 E0

FCHS

Valid

Complements sign of ST(0).

Description

Complements the sign bit of ST(0). This operation changes a positive value into a negative value of equal magni-

tude or vice versa. The following table shows the results obtained when changing the sign of various classes of

numbers.

Table 3-20. FCHS Results

ST(0) SRC

ST(0) DEST

− ∞

+ ∞

− F

+ F

- 0

+ 0

- 0

+ F

- F

+ ∞

- ∞

NaN

NOTES:

* F means finite floating-point value.

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

SignBit(ST(0)) := NOT (SignBit(ST(0)));

FPU Flags Affected

Set to 0.

C0, C2, C3

Undefined.

Floating-Point Exceptions

#IS

Stack underflow occurred.

Protected Mode Exceptions

#NM

CR0.EM[bit 2] or CR0.TS[bit 3] = 1.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions

Same exceptions as in protected mode.

Compatibility Mode Exceptions

Same exceptions as in protected mode.

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INSTRUCTION SET REFERENCE, A-L

FCLEX/FNCLEX-Clear Exceptions

Opcode¹

Instruction

64-Bit

Compat/

Description

Mode

Leg Mode

9B DB E2

FCLEX

Valid

Clear floating-point exception flags after checking for

pending unmasked floating-point exceptions.

DB E2

FNCLEX¹

Valid

Clear floating-point exception flags without checking for

pending unmasked floating-point exceptions.

NOTES:

1. See IA-32 Architecture Compatibility section below.

Description

Clears the floating-point exception flags (PE, UE, OE, ZE, DE, and IE), the exception summary status flag (ES), the

stack fault flag (SF), and the busy flag (B) in the FPU status word. The FCLEX instruction checks for and handles

any pending unmasked floating-point exceptions before clearing the exception flags; the FNCLEX instruction does

not.

The assembler issues two instructions for the FCLEX instruction (an FWAIT instruction followed by an FNCLEX

instruction), and the processor executes each of these instructions separately. If an exception is generated for

either of these instructions, the save EIP points to the instruction that caused the exception.

IA-32 Architecture Compatibility

When operating a Pentium or Intel486 processor in MS-DOS* compatibility mode, it is possible (under unusual

circumstances) for an FNCLEX instruction to be interrupted prior to being executed to handle a pending FPU excep-

tion. See the section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of the Intel^®

64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of these circumstances. An

FNCLEX instruction cannot be interrupted in this way on later Intel processors, except for the Intel Quark^TM X1000

processor.

This instruction affects only the x87 FPU floating-point exception flags. It does not affect the SIMD floating-point

exception flags in the MXCSR register.

This instruction’s operation is the same in non-64-bit modes and 64-bit mode.

Operation

FPUStatusWord[0:7] := 0;

FPUStatusWord[15] := 0;

FPU Flags Affected

The PE, UE, OE, ZE, DE, IE, ES, SF, and B flags in the FPU status word are cleared. The C0, C1, C2, and C3 flags are

undefined.

Floating-Point Exceptions

None.

Protected Mode Exceptions

#NM

CR0.EM[bit 2] or CR0.TS[bit 3] = 1.

#UD

If the LOCK prefix is used.

Real-Address Mode Exceptions

Same exceptions as in protected mode.

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Intel 64 and IA-32 Architectures. Software Developer’s Manual (Collection, 2023) - page 22