|
|
|
Bits
Name
Read/Write
Description
0
IsTLBR
RW
1 indicates that it is currently in the context of TLB refill exception
processing.
The hardware sets this bit to 1 when a TLB refill exception is
triggered.
When this bit is 1, execution of the ERTN instruction will clear it to
0 only if CSR.MERRCTL.IsMERR=0, otherwise it remains
unchanged.
Because the architecture defines a separate set of CSRs for TLB
refill exceptions, when this bit is 1.
•
When ERTN returns, the information used to recover
CSR.CRMD will come from CSR.TLBRPRMD;
•
ERTN return address will come from CSR.TLBRERA;
•
The table entries to be written by TLBWR and TLBFILL
instructions will come from CSR.TLBREHI, CSR.TLBELO0
and CSR.TLBELO1;
• TLBSRCH
instruction
queries
information
from
CSR.TLBREHI;
•
The bad virtual address required for LDDIR and LDPTE
instruction execution will come from CSR.TLBRBADV.
R
1
0
Read-only constant 0, writing to this field is ignored.
RW
GRLEN-1:2
PC
Record the [GRLEN-1:2] bits of the PC of the instruction that
triggered the TLB refill exception. When the execution of ERTN
instruction returns from the TLB refill exception handler (at this
time, this register IsTLBR=1 and CSR.MERRCTL.IsMERR=0).
7.5.14. TLB Refill Exception Data Save Register (TLBRSAVE)
This register is used to store data temporarily for the system software. Each dava save register can hold
the data of one general-purpose register.
The reason for the additional SAVE register for TLB refill exception processing is to address the case where
a TLB refill exception is triggered during the processing of exceptions except the TLB refill exception.
Table 49. Definition of TLB refill exception data save register
Bits
Name
Read/Write
Description
GRLEN-1:0
Data
RW
Data for software to read and write only. The hardware does not
modify the contents of this field except for the execution of CSR
instructions.
7.5.15. TLB Refill Exception Entry Low-order Bits (TLBRELO0, TLBRELO1)
The TLBRELO0/TLBRELO1 registers are used to store the information related to the physical page number
of the low-order bits of the TLB table entry during executing the TLB-related instructions (when the TLB
refill exception context CSR.TLBRERA.IsTLBR=1). The format of TLBRELO0/TLBRELO1 registers and the
142
meaning of each field are the same as TLBELO0/TLBELO1 registers.
However, the TLBRELO0/TLBRELO1 registers are not an exact copy of the TLBELO0/TLBELO1 registers in
the case of CSR.TLBRERA.IsTLBR=1. This is reflected in two points:
•
Regardless of the value of CSR.TLBRERA.IsTLBR, the TLBRD instruction updates only the TLBELO0
/TLBELO1 registers.
•
Regardless of the value of CSR.TLBRERA.IsTLBR, the LDPTE instruction updates only the TLBRELO0
/TLBRELO1 registers.
Table 50. Definition of TLB refill exception entry low order bits register in LA64
Bits
Name
Read/Write
Description
RW
0
V
Valid bit (V) of the page table entry.
1
D
RW
Dirty bit (D) of the page table entry.
3:2
PLV
RW
Privilege LeVel (PLV) of the page table entry.
5:4
MAT
RW
Memory Access Type (MAT) of the page table entry.
RW
6
G
Global flag bit (G) of the page table entry.
When executing the TLBFILL and TLBWR instructions, the G bit of
the page table entry filled into the TLB is 1 only when the G bit in
both TLBELO0 and TLBELO1 is 1.
R
11:7
0
Read-only constant 0, writing to this field is ignored.
RW
PALEN-
PPN
Physical Page Number (PPN) of the page table.
1:12
60:PALEN
0
R
Read-only constant 0, writing to this field is ignored.
61
NR
RW
Non-Readable bit (NR) of the page table entry.
RW
62
NX
Non-eXecutable bit (NX) of the page table entry.
RW
63
RPLV
Restricted Privilege LeVel enable (RPLV) for the page table. When
RPLV=0, the page table entry can be accessed by any program
whose privilege level is not lower than PLV; when RPLV=1, the
page table entry can only be accessed by programs whose
privilege level is equal to PLV.
Table 51. Definition of tlb refill exception entry low order bits register in LA32
Bits
Name
Read/Write
Description
RW
0
V
Valid bit (V) of the page table entry.
RW
1
D
Dirty bit (D) of the page table entry.
RW
3:2
PLV
Privilege LeVel of the page table entry (PLV).
RW
5:4
MAT
Memory Access Type (MAT) of the page table entry.
143
Bits
Name
Read/Write
Description
6
G
RW
Global flag bit (G) of the page table entry. When executing
TLBFILL and TLBWR instructions, the G bit of the page table entry
filled into the TLB is 1 only when the G bits in both TLBELO0 and
TLBELO1 are 1.
11:7
0
R
Read-only constant 0, writing to this field is ignored.
RW
31:12
PPN
Physical Page Number (PPN) of the page table.
7.5.16. TLB Refill Exception Entry High-order Bits (TLBREHI)
When in the TLB refill exception context (CSR.TLBRERA.IsTLBR=1), the TLBREHI register stores the
information related to the physical page number of the low-order bits of the TLB table entry during
executing TLB-related instructions, etc. The format of the TLBREHI register and the meaning of each field
are the same as the TLBEHI register.
However, the TLBREHI register is not an exact replica of the TLBEHI register in the case of
CSR.TLBRERA.IsTLBR=1. This is reflected in:
•
Regardless of the value of CSR.TLBRERA.IsTLBR equals, the execution of the TLBRD instruction
updates only the TLBEHI register.
Table 52. Definition of TLB refill exception entry high order bits register in LA64
Bits
Name
Read/Write
Description
RW
Page size specified by TLB refill exception. That is, when
5:0
PS
CSR.TLBRERA.IsTLBR=1, when executing TLBWR and TLBFILL
instructions and the value of the PS field of the written TLB table
entry comes from this.
R
12:0
0
The read-only constant is 0, and writes are ignored.
RW
VALEN-
VPPN
When CSR.TLBRERA.IsTLBR=1, the value of VPPN used for
1:13
querying TLB when executing TLBSRCH instruction, and the value
of VPPN field of TLB table entry written when executing TLBWR
and TLBFILL instructions come from here. When a TLB refill
exception is triggered, the [VALEN-1:13] bits of the virtual
address that triggered the exception are recorded here.
R
The return value read from these bits is a signed extension of the
63:VALEN
Sign_Ext
highest bits of the VPPN field; writing to these bits is ignored.
Table 53. Definition of tlb refill exception entry high order bits register in LA32
Bits
Name
Read/Write
Description
R
12:0
0
Read-only is constant to 0, and writes are ignored.
31:13
VPPN
RW
With CSR.TLBRERA.ISTLBR=1, the VPPN value used to query
the TLB when executing the TLBSRCH instruction, and the value of
the VPPN field written to the TLB table entry when executing the
TLBWR and TLBFILL instructions come from here. When a TLB
refill exception is triggered, the [31:13] bits of the virtual
address that triggered the exception are recorded here.
144
7.5.17. TLB Refill Exception Pre-exception Mode Information (TLBRPRMD)
When a TLB refill exception is triggered, the hardware saves the processor core’s privilege level, Guest
mode, global interrupt enable bit, and watchpoint enable bit into this register at that time, which is used to
restore the processor core to the field when the exception returns.
Table 54. Definition of TLB refill exception pre-exception mode information register
Bits
Name
Read/Write
Description
1:0
PPLV
RW
When the TLB refill exception is triggered, the hardware records
the old value of the PLV field in CSR.CRMD in this field. When
CSR.TLBRERAIsTLBR=1, the hardware restores the value of this
field to the PLV field of CSR.CRMD when the ERTN instruction is
executed to return from the exception handler.
RW
When the TLB refill exception is triggered, the hardware records
2
PIE
the old value of the IE field in the CSR.CRMD in this field. When
CSR.TLBRERAIsTLBR=1, the hardware restores the value of this
field to the IE field of CSR.CRMD when the ERTN instruction is
executed to return from the exception handler.
3
0
R
If the virtualization extension is not implemented, this bit is read-
only constant to 0 and writes are ignored.
4
PWE
RW
When the TLB refill exception is triggered, the hardware records
the old value of the WE field in the CSR.CRMD in this field. When
CSR.TLBRERAIsTLBR=1, the hardware restores the value of this
field to the WE field of CSR.CRMD when the ERTN instruction is
executed to return from the exception handler.
R0
31:5
0
Reserved field. Return 0 if read this field, and software is not
allowed to change its value.
7.5.18. Direct Mapping Configuration Window n (DMW0-DMW3)
This -group sender is involved in completing the direct mapping address translation mode. See Direct
Mapped Address Translation Mode for more information about this address translation mode.
Table 55. Definition of direct mapping configuration window n register in LA64
Bits
Name
Read/Write
Description
RW
0
PLV0
1 indicates that the configuration of this window can be used for
direct mapping address translation at the PLV0 privilege level.
RW
1
PLV1
1 indicates that the configuration of this window can be used for
direct mapping address translation at the PLV1 privilege level.
2
PLV2
RW
1 indicates that the configuration of this window can be used for
direct map address translation at the PLV2 privilege level.
RW
3
PLV3
1 indicates that the configuration of this window can be used for
direct mapping address translation at the PLV3 privilege level.
RW
The virtual address falls under the memory access type of the
5:4
MAT
access operation in this mapping window.
59:6
0
R0
Reserved field. Return 0 if read this field and software is not
allowed to change its value.
145
Bits
Name
Read/Write
Description
63:60
VSEG
RW
The [63:60] bits of the virtual address of the direct mapping
window.
Table 56. Definition of direct mapping configuration window n register in LA32
Bits
Name
Read/Write
Description
RW
0
PLV0
1 indicates that the configuration of this window can be used for
direct mapping address translation at the PLV0 privilege level.
RW
1
PLV1
1 indicates that the configuration of this window can be used for
direct mapping address translation at the PLV1 privilege level.
2
PLV2
RW
1 indicates that the configuration of this window can be used for
direct map address translation at the PLV2 privilege level.
RW
3
PLV3
1 indicates that the configuration of this window can be used for
direct mapping address translation at the PLV3 privilege level.
RW
The virtual address falls under the memory access type of the
5:4
MAT
access operation in this mapping window.
24:6
0
R0
Reserved field. Return 0 if read this field and software is not
allowed to change its value.
RW
27:25
PSEG
The [31:29] bits of the physical address of the direct mapping
window.
28
0
R0
Reserved field. Return 0 if read this field and software is not
allowed to change its value.
31:29
VSEG
RW
The [31:29] bits of the virtual address of the direct mapping
window.
7.6. Control and Status Registers Related to Timers
7.6.1. Timer Identity (TID)
Each timer in the processor has a unique identifiable number, which is configured by the software in this
register. Each timer also uniquely corresponds to a timer, and when the software reads the timer value
using the RDTIME instruction, the timer ID number that is returned along with it is the corresponding timer
number.
Table 57. Definition of timer identity register
Bits
Name
Read/Write
Description
31:0
TID
RW
Timer number. It can be configured via software. During a
processor core reset, the hardware can reset it to the same value
as the CoreID in CSR.CPUID.
7.6.2. Timer Configuration (TCFG)
This register is the interface to the software configuration timer. The number of valid bits of the timer is
determined by the implementation, so the length of the TimeVal field in this register will change
accordingly.
Table 58. Definition of timer configuration register
146
Bits
Name
Read/Write
Description
0
En
RW
Timer enable bit. Only when this bit is 1, the timer will perform
countdown self decrement and set up the timing interrupt signal
when it decrements to 0 value.
RW
1
Periodic
Timer cycle mode control bit. If this bit is 1, when the timer
decreases to 0, the timer will set up the timer interrupt signal and
reload the timer to the initial value configured in the TimeVal field,
and then continue to decrement itself in the next clock cycle. If
this bit is 0, the timer will stop counting until the software
configures the timer again when the countdown reaches 0.
RW
The initial value of the timer countdown self decrement count.
n-1:2
InitVal
This initial value must be an integer multiple of 4. The hardware
will automatically fill in the lowest bit of the field value. Two bits
of 0 are added before it is used.
R
GRLEN-1:n
0
Read-only constant 0, writing to this field is ignored.
7.6.3. Timer Value (TVAL)
The software can read this register to know the current count value of the timer. The number of valid bits of
the timer is determined by the implementation, so the length of the TimeVal field in this register will also
change.
Table 59. Definition of timer value register
Bits
Name
Read/Write
Description
n-1:0
TimeVal
R
The count value of the current timer.
R
GRLEN-1:n
0
Read-only constant 0, writing to this field is ignored.
7.6.4. Counter Compensation (CNTC)
This register can be configured by the software to correct the timer’s readout value. The final readout value
will be the original timer count value plus the timer compensation value. It is important to note that
configuring this register does not directly change the timer’s count value.
In LA32, this register is 32-bit and its value will be sign extended to 64 bits and then added to the original
counter value.
Table 60. Definition of counter compensation register
Bits
Name
Read/Write
Description
GRLEN-1:0
Compensta
RW
Software-configurable counter compensation values.
ion
7.6.5. Timer Interrupt Clearing (TICLR)
The software clears the timed interrupt signal set by the timer by writing 1 to bit 0 of this register.
Table 61. Definition of timer interrupt clearing register
147
Bits
Name
Read/Write
Description
0
CLR
W1
When 1 is written to this bit, the clock interrupt flag is cleared. The
value read from this register is always 0.
R0
31:1
0
Reserved field. Return 0 if read this field and software is not
allowed to change its value.
7.7. Control and Status Registers Related to RAS
7.7.1. Machine Error Controller (MERRCTL)
Since the timing of machine error exceptions cannot be predicted and controlled by the software, a
separate set of CSRs is defined for machine error exceptions in order not to destroy any other site when
triggering machine error exceptions, which is used by the system software to save and restore other sites.
This set of independent CSRs except MERRERA and MERRSAVE, the rest are concentrated in MERRCTL
register.
Table 62. Definition of machine error controller register
Bits
Name
Read/Write
Description
0
IsMERR
R
1 indicates that it is currently in the context of machine error
exception processing. The hardware sets this bit to 1 when a
machine error exception is triggered.
When this bit is 1, execution of the ERTN instruction will clear it to
0.
Because the architecture defines a separate set of CSRs for
machine error exceptions, when this bit is 1,
* when ERTN returns, information used to restore the CSRs will
come from PPLV, PLV and so on of this field;
* when ERTN returns, address information will come from
CSR.MERRERA.
1
Repairabl
RW
1 means that the hardware can automatically fix machine errors
that occur, so the exception handler can return directly without
e
any processing.
3:2
PPLV
RW
When a machine error exception is triggered, the hardware
records the old value of the PLV field in CSR.CRMD in this field.
When the IsMERR of this register is 1, the hardware returns from
the exception handler by executing the ERTN instruction. The
hardware restores the value of this field to the PLV field of
CSR.CRMD.
R
When a machine error exception is triggered, the hardware
4
PIE
records the old value of the IE field in CSR.CRMD in this field.
When IsMERR of this register is 1, the hardware restores the
value of this field to the IE field of CSR.CRMD when the ERTN
instruction is executed to return from the exception handler.
148
Bits
Name
Read/Write
Description
5
0
RW
If the virtualization expansion is not implemented, this field is
read-only constant 0 and writing to this field is ignored.
6
PWE
RW
When a machine error exception is triggered, the hardware
records the old value of the WE field in CSR.CRMD in this field.
When IsMERR of this register is 1, the hardware restores the
value of this field to the WE field in CSR.CRMD when the ERTN
instruction is executed to return from the exception handler.
RW
When a machine error exception is triggered, the hardware
7
PDA
records the old value of the DA field in the CSR.CRMD in this field.
When IsMERR of this register is 1, the hardware restores the
value of this field to the DA field of CSR.CRMD when the ERTN
instruction is executed to return from the exception handler.
8
PPG
RW
When a machine error exception is triggered, the hardware
records the old value of the PG field in the CSR.CRMD in this field.
When IsMERR of this register is 1, the hardware restores the value
of this field to the PG field of CSR.CRMD when the ERTN
instruction is executed to return from the exception handler.
RW
When a machine error exception is triggered, the hardware
10:9
PDATF
records the old value of the DATF field in the CSR.CRMD in this
field.
When IsMERR of this register is 1, the hardware restores the
value of this field to the DATF field of CSR.CRMD when the ERTN
instruction is executed to return from the exception handler.
12:11
PDATM
RW
When a machine error exception is triggered, the hardware
records the old value of the DATM field in the CSR.CRMD in this
field.
When IsMERR of this register is 1, the hardware restores the
value of this field to the DATM field of CSR.CRMD when the ERTN
instruction is executed to return from the exception handler.
R0
15:13
0
Reserved field. Return 0 if read this field and software must write
0, or mask out this field by csr mask write.
R
23:16
Cause
Machine error type code. Currently only the 0x1 value is defined
for Cache checksum errors.
The rest of the encoded values are reserved.
31:24
0
R0
Reserved field. Return 0 if read this field and software is not
allowed to change its value.
7.7.2. Machine Error Information (MERRINFO1, MERRINFO2)
When a machine error exception is triggered, the hardware will store more information related to that error
into these two registers for system software diagnostic purposes. The format and the meaning of each
field are defined by the implementation.
149
7.7.3. Machine Error Exception Entry Base Address (MERRENTRY)
This register is used to configure the entry base address of the machine error exception. Since the
processor core will enter the direct address translation mode after the machine error exception is triggered,
the entry base address filled here should be the physical address.
Table 63. Definition of machine error exception entry base address register in LA64
Bits
Name
Read/Write
Description
11:0
0
R
Read-only constant 0, writing to this field is ignored.
PALEN-
PPN
RW
The [PALEN-1:12] bits of the entry base address of the
machine error exception. The address filled in here by the system
1:12
software should be the physical address.
63:PALEN
0
R
Read-only constant 0, writing to this field is ignored.
Table 64. Definition of machine error exception entry base address register in LA32
Bits
Name
Read/Write
Description
11:0
0
R
Read-only constant 0, writing to this field is ignored.
RW
31:12
PPN
The [31:12] bits of the entry base address of the machine error
exception. The address entered here by the system software
should be a physical address.
7.7.4. Machine Error Exception Return Address (MERRERA)
This register is used to record the PC of the instruction that triggered the machine error exception.
Table 65. Definition of machine error exception return address register
Bits
Name
Read/Write
Description
GRLEN-1:0
PC
RW
The PC of the instruction that triggered the machine error
exception is recorded. The value stored here is used as the return
address when the ERTN instruction is executed to return from the
machine error exception handler (when
CSR.MERRCTL.IsMERR=1).
7.7.5. Machine Error Exception Data Save Register (MERRSAVE)
This register is used to store data temporarily for the system software. Each dava save register can hold
the data of one general-purpose register.
The reason for the additional SAVE register for the machine error exception handler is that the timing of the
machine error exception cannot be predicted and controlled by the software, and it may occur during the
processing of any other exception.
Table 66. Definition of machine error exception data save register
Bits
Name
Read/Write
Description
RW
Data for software to read and write only. The hardware will not
GRLEN-1:0
DATA
modify the contents of this field except for the execution of CSR
instructions.
150
7.8. Control and Status Registers Related to Performance
Monitoring
LoongArch defines a hardware performance monitoring mechanism to support software performance
analysis. The main body of this mechanism is a series of performance monitors. At least one performance
monitor is implemented, and up to 32 monitors are implemented, the number is determined by the
implementation. The software can determine how many performance monitors are available by reading the
CPUCFG.6.PMNUM[bit7:4].
Each performance monitor contains two CSRs: a Performance Monitoring ConFiGuration register (PMCFG)
and a Performance Monitoring CouNTer register (PMCNT).
All CSRs related to performance monitoring are alternately addressed starting at address 0x200, with the
nth performance monitoring configuration register at address
0x200+n, and the nth performance
monitoring counter at address 0x201+n. The format of all performance monitoring configuration registers
is the same, as described in Performance Monitor Configuration n (PMCFG); the format of all performance
monitoring counters is the same, as described in Performance Monitor Overall Counter n (PMCNT).
7.8.1. Performance Monitor Configuration n (PMCFG)
Table 67. Definition of performance monitor configuration n register
Bits
Name
Read/Write
Description
9:0
EvCode
RW
The event number of the performance event being monitored. The
definition of event numbers is divided into two parts, a part whose
meaning is specified in the architecture specification and must be
implemented by all processors compatible with this architecture,
and a remaining part whose meaning is implementation specific
and is defined by the processor’s implementer.
R0
15:10
0
Reserved fields. Return 0 if read this field, and software is not
allowed to change its value.
16
PLV0
RW
PLV0 privilege level enables counting for this performance
monitor. 1 - count, 0 - stop.
17
PLV1
RW
PLV1 privilege level enables counting for this performance
monitor. 1 - count, 0 - stop.
18
PLV2
RW
PLV2 privilege level enables counting for this performance
monitor. 1 - count, 0 - stop.
RW
Count enable for this performance monitor at the PLV3 privilege
19
PLV3
level. 1 - count, 0 - stop.
RW
Performance monitoring count overflow interrupt enable bit for
20
PMIEn
this performance monitor. 1 - enable, 0 - disable.
R
If the virtualization expansion is not implemented, this field is
22:21
0
read-only constant 0 and writing to this field is ignored.
R0
31:23
0
Reserved field. Return 0 if read this field and software is not
allowed to change its value.
7.8.2. Performance Monitor Overall Counter n (PMCNT)
Table 68. Definition of performance monitor overall counter n register
151
Bits
Name
Read/Write
Description
GRLEN-1:0
Count
RW
The counter is incremented by 1 for each performance event
monitored by the performance monitor.
If the performance monitor has enabled the performance
monitoring count overflow interrupt, and when the highest bit of
Count is 1, the interrupt is triggered. This also means that the
software can cancel the interrupt by clearing the highest bit of
Count to 0.
7.9. Control and Status Registers Related to Watchpoints
LoongArch defines hardware watchpoint functions for fetch and load/store operations. After the software
configures the watchpoints for fetch and load/store, the processor hardware will monitor the access
addresses of the fetch and load/store operations and trigger a watchpoint exception when the watchpoint
setting conditions are met.
The control and status registers associated with the watchpoints are used as interfaces for software to
configure the watchpoints for fetch and load/store operations. Load/store watchpoints and fetch
watchpoints each have a similar layout of control and status registers, a register for the overall
configuration of all watchpoints, a register for the status of all watchpoints, and the four registers. The
address of the overall configuration register of the load/store watchpoint is 0x300, the address of the
overall status register of the load/store watchpoint is 0x301, and the addresses of the four configuration
registers from 1 to 4 of the nth load/store watchpoint are 0x310+8n, 0x311+8n, 0x312+8n, and
0x313+8n, respectively. The address of the overall configuration register of the fetch instruction
watchpoint is 0x380, the address of the overall status register of the fetch instruction watchpoint is 0x381,
and the addresses of the four configuration registers 1-4 of the nth fetch instruction watchpoint are
0x390+8n, 0x391+8n, 0x392+8n, 0x393+8n in order.
The maximum number of load/store watchpoints and fetch instruction watchpoints is 14 each, and the
actual number is determined by the implementation. The software can determine how many hardware
watchpoints can be used by reading the values of CSR.MWPC.Num and CSR.FWPC.Num.
7.9.1. Memory Load/Store Watchpoint Overall Controller (MWPC)
This register contains configuration information to inform the software of the exact number of load/store
watchpoints.
It is important to note that the global enable control signal for all watchpoints is in the WE bit of CSR.CRMD.
Table 69. Definition of memory load/store watchpoint overall controller register
Bits
Name
Read/Write
Description
5:0
Num
R
The number of load/store watchpoints.
R
If no virtualization extension is implemented, the field is read-only
19:16
0
constant to 0 and writes are ignored.
R0
31:20
0
Reserved field. Reads return 0 and the software does not allow to
change its value.
7.9.2. Memory Load/Store Watchpoint Overall Status (MWPS)
Table 70. Definition of memory load/store watchpoint overall status register
152
Bits
Name
Read/Write
Description
n-1:0
Status
RW1[2]
The hit status of the load/store watchpoint. It corresponds to the
watchpoint one by one, and bit i corresponds to watchpoint i.
When an address with a load/store operation hits a watchpoint,
the corresponding bit is set to 1. The hardware does not clear the
bits in this field except during a reset.
The software can only clear them by writing 1, writing 0 is
ignored.
15:n
0
R
Read-only constant 0, writing to this field is ignored.
16
Skip
RW
The software notifies the hardware to ignore the next load/store
watchpoint hit by setting this location to 1. By ignoring, it means
that neither the corresponding bit in the Stauts field of this
register is set to 1 nor the watchpoint exception is triggered. This
function can avoid endlessly triggering the same watchpoint
repeatedly without canceling it, thus simplifying the handling of
watchpoint exceptions.
When the Skip bit is 1, if the hardware encounters a loadjstore hit,
it will ignore the hit and clear the Skip bit to 0. This means that
each time the software sets the Skip bit to 1, the hardware will
ignore at most one hit. This feature also causes the software to
write 1 to this bit and then read out the value which may not be 1.
This Skip bit corresponds to all load/store watchpoints. If the
software modifies the configuration of the breakpoint and
replaces it, do not set this bit, or even write 0 to clear it for safety
reasons.
R
31:17
0
Read-only constant 0, writing to this field is ignored.
7.9.3. Memory Load/Store Watchpoint n Configuration (MWPnCFG1-MWPnCFG4)
The information contained in the configuration 1 to 3 registers of each load/store watchpoint is used
directly for the comparison judgment of the watchpoint check. Assuming that the address of the operation
to be compared is maddr and the byte range is mbyten, the process of determining the hit of each
watchpoint is as follows:
1.
If CSR.CRMD.WE=0, the judgment is terminated, otherwise turn 2;
2.
If the current is not in debug mode but the DMOnly bit of MWPCFG3 is equal to 1, the judgment is
terminated, otherwise turn to 3;
3.
If the bit corresponding to the current privilege level in PLV0-PLV3 of MWPCFG3 is equal to 0, the
judgment is terminated, otherwise turn to 4;
4.
If the operation is a load operation but the LoadEn bit in MWPCFG3 is equal to 0, or the operation is a
store operation but the StoreEn bit in MWPCFG3 is equal to 0, the judgment is terminated, otherwise go
to 5;
5.
If the LCL bit in MWPCFG3 is equal to 1, but the CSR.ASID.ASID is not equal to the ASID in MWPCFG4,
the judgment is terminated, otherwise go to 6;
6.
If
(maddr &
(~MWPCFG2.Mask))
!=
(MWPCFG1.VAaddr &
(~MWPCFG2.Mak)), that is, the
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address comparison is not equal, the judgment terminates, otherwise turn 7;
7.
If
(~bytemask[7:0] & mbyten[7:0]) is equal to all 0 values, the judgment is terminated,
otherwise the watchpoint is considered to be hit.
The concepts of mbyten and bytemask, which appear in the description of the judgment process above,
are explained further below.
mbyten represents the bytes involved in the operation, which is an 8-bit bit vector whose value is related to
the type of load/store operation and the low value of the address, as defined in the table:
Table 71. Definition of load/store watchpoint judgment process mbyten
Intsruction Name
maddr[2:0]
0
1
2
3
4
5
6
7
LD[X].B[U], ST[X].B,
0x01
0x02
0x04
0x08
0x10
0x20
0x40
0x80
LD{GT/LE}.B, ST{GT/LE}.B
LD[X].H[U], ST[X].H
0x30
0x0C
0x30
0xC0
LD{GT/LE}.H, ST{GT/LE}.H
LD[X].W[U], ST[X].W,
0x0F
0xF0
LD{GT/LE}.W, ST{GT/LE}.W,
LDPTR.W, STPTR.W,
LL.W, SC.W,
AM{SWAP/ADD/AND/OR/XOR/MA
X/MIN}[.DB].W,
AM{MAX/MIN}[_DBI].WU,
FLD[X].S, FST[X]S,
FLD{GT/LE}.S,
FST{GT/LE}.S
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Intsruction Name
maddr[2:0]
LD[X].D, ST[X].D,
0xFF
LD{GT/LE}.D, ST[GT/LE].D,
LDPTR.D, STPTR.D,
LL.D, SC.D,
AM{SWAP/ADD/AND/OR/XOR/MA
X/MIN}[_DB].D,
AM{MAX/MIN}[_DB].DU,
FLD[X].D, FST[X].D,
FLD{GT/LE}.D,
FST{GT/LE}.D
bytemask indicates which bytes do not participate in the comparison mask when watchpoint comparison,
which is an 8-bit bit vector whose value is related to the low bit of VAddr in MWPCFG1 and Size in
MWPCF`G3, as defined as shown.
Table 72. Definition of load store watchpoint bytemask
MWPCFG3.Size
MWPCFG1.Vaddr[2:0]
0
1
2
3
4
5
6
7
0b00
0x00
0b01
0xF0
0x0F
0b10
0xFC
0xF3
0xCF
0x3F
0b11
0xFE
0xFD
0xFB
0xF7
0xEF
0xDF
0xBF
0x7F
Table 73. Definition of memory load/store watchpoint n configuration 1 register
Bits
Name
Read/Write
Description
RW
The virtual address to be compared for this load/store
GRLEN-1:0
VAddr
watchpoint.
Table 74. Definition of memory load/store watchpoint n configuration 2 register
Bits
Name
Read/Write
Description
GRLEN-1:0
Mask
RW
Mask bit for address comparison for this load/store watchpoint.
If bit i (0
≤ i < GRLEN) is 1, it means that bit i of the address
is not involved in the comparison.
Table 75. Definition of memory load/store watchpoint n configuration 3 register
155
Bits
Name
Read/Write
Description
0
DMOnly
RW
A bit of 1 indicates that the load/store watchpoint is only
available in debug mode. Here “available” contains two meanings:
first, the configuration register of the watchpoint can be modified
by software in this mode, and second, the check hit of the
watchpoint will trigger the watchpoint exception and mark the
status of the watchpoint only in this mode.
This bit can only be modified in debug mode (CSR.DBG.DM=1).
This means that the (Host) software running in debug mode has
the priority to use the watchpoint.
RW
This watchpoint triggers the enable of the watchpoint exception
1
PLV0
at the PLV0 privilege level. 1 - enable, 0 - disable.
RW
The watchpoint triggers the watchpoint exception enable at the
2
PLV1
PLV1 privilege level. 1 - enable, 0 - disable.
RW
The watchpoint triggers the enable of the watchpoint exception at
3
PLV2
the PLV2 privilege level. 1 - enable, 0 - disable.
RW
The watchpoint triggers the enablement of the watchpoint
4
PLV3
exception at the PLV3 privilege level. 1 - enable, 0 - disable.
R
If virtualization extensions are not implemented, the field is read-
6:5
0
only constant at 0 and writes are ignored.
RW
7
LCL
1 indicates that the ASID comparison is performed during the
watchpoint check
RW
8
LoadEn
1 indicates a watchpoint check for load operations, otherwise no
check.
9
StoreEn
RW
1 means that a watchpoint check is performed for the store
operation, otherwise, no check is performed.
RW
Which bytes fall within the comparison range when the
11:10
Size
watchpoint check is performed.
R0
31:12
0
Reserved field. Return 0 if read this field, and the software does
not allow to change its value.
Table 76. Definition of memory load/store watchpoint n configuration 4 register
Bits
Name
Read/Write
Description
9:0
ASID
RW
The ASID being compared
R
15:10
0
Read-only is always 0, writes are ignored.
23:16
0
R
If the virtualization extension is not implemented, the field is read-
only constant to 0 and writes are ignored.
31:24
0
R
Read-only constant 0, writing to this field is ignored.
7.9.4. Fetch Watchpoint Overall Controller (FWPC)
This register contains configuration information to inform the software of the exact number of watchpoints
to be fetched.
It is important to note that the global enable control signal for all watchpoints is in the WE bit of the
CSR.CRMD.
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